1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, SchedulerType} 19import xiangshan.backend.issue.EntryBundles._ 20import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 21import xiangshan.backend.rob.RobPtr 22import xiangshan.frontend._ 23import xiangshan.mem.{LqPtr, SqPtr} 24 25object Bundles { 26 /** 27 * Connect Same Name Port like bundleSource := bundleSinkBudle. 28 * 29 * There is no limit to the number of ports on both sides. 30 * 31 * Don't forget to connect the remaining ports! 32 */ 33 def connectSamePort (bundleSource: Bundle, bundleSink: Bundle):Unit = { 34 bundleSource.elements.foreach { case (name, data) => 35 if (bundleSink.elements.contains(name)) 36 data := bundleSink.elements(name) 37 } 38 } 39 // frontend -> backend 40 class StaticInst(implicit p: Parameters) extends XSBundle { 41 val instr = UInt(32.W) 42 val pc = UInt(VAddrBits.W) 43 val foldpc = UInt(MemPredPCWidth.W) 44 val exceptionVec = ExceptionVec() 45 val trigger = new TriggerCf 46 val preDecodeInfo = new PreDecodeInfo 47 val pred_taken = Bool() 48 val crossPageIPFFix = Bool() 49 val ftqPtr = new FtqPtr 50 val ftqOffset = UInt(log2Up(PredictWidth).W) 51 52 def connectCtrlFlow(source: CtrlFlow): Unit = { 53 this.instr := source.instr 54 this.pc := source.pc 55 this.foldpc := source.foldpc 56 this.exceptionVec := source.exceptionVec 57 this.trigger := source.trigger 58 this.preDecodeInfo := source.pd 59 this.pred_taken := source.pred_taken 60 this.crossPageIPFFix := source.crossPageIPFFix 61 this.ftqPtr := source.ftqPtr 62 this.ftqOffset := source.ftqOffset 63 } 64 } 65 66 // StaticInst --[Decode]--> DecodedInst 67 class DecodedInst(implicit p: Parameters) extends XSBundle { 68 def numSrc = backendParams.numSrc 69 // passed from StaticInst 70 val instr = UInt(32.W) 71 val pc = UInt(VAddrBits.W) 72 val foldpc = UInt(MemPredPCWidth.W) 73 val exceptionVec = ExceptionVec() 74 val trigger = new TriggerCf 75 val preDecodeInfo = new PreDecodeInfo 76 val pred_taken = Bool() 77 val crossPageIPFFix = Bool() 78 val ftqPtr = new FtqPtr 79 val ftqOffset = UInt(log2Up(PredictWidth).W) 80 // decoded 81 val srcType = Vec(numSrc, SrcType()) 82 val lsrc = Vec(numSrc, UInt(6.W)) 83 val ldest = UInt(6.W) 84 val fuType = FuType() 85 val fuOpType = FuOpType() 86 val rfWen = Bool() 87 val fpWen = Bool() 88 val vecWen = Bool() 89 val isXSTrap = Bool() 90 val waitForward = Bool() // no speculate execution 91 val blockBackward = Bool() 92 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 93 val canRobCompress = Bool() 94 val selImm = SelImm() 95 val imm = UInt(ImmUnion.maxLen.W) 96 val fpu = new FPUCtrlSignals 97 val vpu = new VPUCtrlSignals 98 val vlsInstr = Bool() 99 val wfflags = Bool() 100 val isMove = Bool() 101 val uopIdx = UopIdx() 102 val uopSplitType = UopSplitType() 103 val isVset = Bool() 104 val firstUop = Bool() 105 val lastUop = Bool() 106 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 107 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 108 val commitType = CommitType() // Todo: remove it 109 110 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 111 112 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 113 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 114 115 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 116 val decoder: Seq[UInt] = ListLookup( 117 inst, XDecode.decodeDefault.map(bitPatToUInt), 118 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 119 ) 120 allSignals zip decoder foreach { case (s, d) => s := d } 121 debug_fuType.foreach(_ := fuType) 122 this 123 } 124 125 def isSoftPrefetch: Bool = { 126 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 127 } 128 129 def connectStaticInst(source: StaticInst): Unit = { 130 for ((name, data) <- this.elements) { 131 if (source.elements.contains(name)) { 132 data := source.elements(name) 133 } 134 } 135 } 136 } 137 138 // DecodedInst --[Rename]--> DynInst 139 class DynInst(implicit p: Parameters) extends XSBundle { 140 def numSrc = backendParams.numSrc 141 // passed from StaticInst 142 val instr = UInt(32.W) 143 val pc = UInt(VAddrBits.W) 144 val foldpc = UInt(MemPredPCWidth.W) 145 val exceptionVec = ExceptionVec() 146 val trigger = new TriggerCf 147 val preDecodeInfo = new PreDecodeInfo 148 val pred_taken = Bool() 149 val crossPageIPFFix = Bool() 150 val ftqPtr = new FtqPtr 151 val ftqOffset = UInt(log2Up(PredictWidth).W) 152 // passed from DecodedInst 153 val srcType = Vec(numSrc, SrcType()) 154 val ldest = UInt(6.W) 155 val fuType = FuType() 156 val fuOpType = FuOpType() 157 val rfWen = Bool() 158 val fpWen = Bool() 159 val vecWen = Bool() 160 val isXSTrap = Bool() 161 val waitForward = Bool() // no speculate execution 162 val blockBackward = Bool() 163 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 164 val canRobCompress = Bool() 165 val selImm = SelImm() 166 val imm = UInt(32.W) 167 val fpu = new FPUCtrlSignals 168 val vpu = new VPUCtrlSignals 169 val vlsInstr = Bool() 170 val wfflags = Bool() 171 val isMove = Bool() 172 val uopIdx = UopIdx() 173 val isVset = Bool() 174 val firstUop = Bool() 175 val lastUop = Bool() 176 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 177 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 178 val commitType = CommitType() 179 // rename 180 val srcState = Vec(numSrc, SrcState()) 181 val srcLoadDependency = Vec(numSrc, Vec(LoadPipelineWidth, UInt(3.W))) 182 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 183 val pdest = UInt(PhyRegIdxWidth.W) 184 val robIdx = new RobPtr 185 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 186 val dirtyFs = Bool() 187 val dirtyVs = Bool() 188 189 val eliminatedMove = Bool() 190 // Take snapshot at this CFI inst 191 val snapshot = Bool() 192 val debugInfo = new PerfDebugInfo 193 val storeSetHit = Bool() // inst has been allocated an store set 194 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 195 // Load wait is needed 196 // load inst will not be executed until former store (predicted by mdp) addr calcuated 197 val loadWaitBit = Bool() 198 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 199 // load inst will not be executed until ALL former store addr calcuated 200 val loadWaitStrict = Bool() 201 val ssid = UInt(SSIDWidth.W) 202 // Todo 203 val lqIdx = new LqPtr 204 val sqIdx = new SqPtr 205 // debug module 206 val singleStep = Bool() 207 // schedule 208 val replayInst = Bool() 209 210 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 211 212 def getDebugFuType: UInt = debug_fuType.getOrElse(fuType) 213 214 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 215 def isLUI32: Bool = this.selImm === SelImm.IMM_LUI32 216 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 217 218 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 219 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 220 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 221 222 def isHls: Bool = { 223 fuType === FuType.ldu.U && LSUOpType.isHlv(fuOpType) || fuType === FuType.stu.U && LSUOpType.isHsv(fuOpType) 224 } 225 226 def srcIsReady: Vec[Bool] = { 227 VecInit(this.srcType.zip(this.srcState).map { 228 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 229 }) 230 } 231 232 def clearExceptions( 233 exceptionBits: Seq[Int] = Seq(), 234 flushPipe : Boolean = false, 235 replayInst : Boolean = false 236 ): DynInst = { 237 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 238 if (!flushPipe) { this.flushPipe := false.B } 239 if (!replayInst) { this.replayInst := false.B } 240 this 241 } 242 243 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen 244 } 245 246 trait BundleSource { 247 var wakeupSource = "undefined" 248 var idx = 0 249 } 250 251 /** 252 * 253 * @param pregIdxWidth index width of preg 254 * @param exuIndices exu indices of wakeup bundle 255 */ 256 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int]) extends Bundle { 257 val rfWen = Bool() 258 val fpWen = Bool() 259 val vecWen = Bool() 260 val pdest = UInt(pregIdxWidth.W) 261 262 /** 263 * @param successor Seq[(psrc, srcType)] 264 * @return Seq[if wakeup psrc] 265 */ 266 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 267 successor.map { case (thatPsrc, srcType) => 268 val pdestMatch = pdest === thatPsrc 269 pdestMatch && ( 270 SrcType.isFp(srcType) && this.fpWen || 271 SrcType.isXp(srcType) && this.rfWen || 272 SrcType.isVp(srcType) && this.vecWen 273 ) && valid 274 } 275 } 276 def wakeUpFromIQ(successor: Seq[(UInt, UInt)]): Seq[Bool] = { 277 successor.map { case (thatPsrc, srcType) => 278 val pdestMatch = pdest === thatPsrc 279 pdestMatch && ( 280 SrcType.isFp(srcType) && this.fpWen || 281 SrcType.isXp(srcType) && this.rfWen || 282 SrcType.isVp(srcType) && this.vecWen 283 ) 284 } 285 } 286 287 def hasOnlyOneSource: Boolean = exuIndices.size == 1 288 289 def hasMultiSources: Boolean = exuIndices.size > 1 290 291 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 292 293 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 294 295 def exuIdx: Int = { 296 require(hasOnlyOneSource) 297 this.exuIndices.head 298 } 299 } 300 301 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 302 303 } 304 305class IssueQueueIQWakeUpBundle( 306 exuIdx: Int, 307 backendParams: BackendParams, 308 copyWakeupOut: Boolean = false, 309 copyNum: Int = 0 310) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 311 val loadDependency = Vec(backendParams.LduCnt + backendParams.HyuCnt, UInt(3.W)) 312 val is0Lat = Bool() 313 val params = backendParams.allExuParams.filter(_.exuIdx == exuIdx).head 314 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 315 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 316 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 317 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 318 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum,Vec(backendParams.LdExuCnt, UInt(3.W)))) 319 def fromExuInput(exuInput: ExuInput, l2ExuVecs: Vec[UInt]): Unit = { 320 this.rfWen := exuInput.rfWen.getOrElse(false.B) 321 this.fpWen := exuInput.fpWen.getOrElse(false.B) 322 this.vecWen := exuInput.vecWen.getOrElse(false.B) 323 this.pdest := exuInput.pdest 324 } 325 326 def fromExuInput(exuInput: ExuInput): Unit = { 327 this.rfWen := exuInput.rfWen.getOrElse(false.B) 328 this.fpWen := exuInput.fpWen.getOrElse(false.B) 329 this.vecWen := exuInput.vecWen.getOrElse(false.B) 330 this.pdest := exuInput.pdest 331 } 332 } 333 334 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 335 // vtype 336 val vill = Bool() 337 val vma = Bool() // 1: agnostic, 0: undisturbed 338 val vta = Bool() // 1: agnostic, 0: undisturbed 339 val vsew = VSew() 340 val vlmul = VLmul() // 1/8~8 --> -3~3 341 342 val vm = Bool() // 0: need v0.t 343 val vstart = Vl() 344 345 // float rounding mode 346 val frm = Frm() 347 // scalar float instr and vector float reduction 348 val fpu = Fpu() 349 // vector fix int rounding mode 350 val vxrm = Vxrm() 351 // vector uop index, exclude other non-vector uop 352 val vuopIdx = UopIdx() 353 val lastUop = Bool() 354 // maybe used if data dependancy 355 val vmask = UInt(MaskSrcData().dataWidth.W) 356 val vl = Vl() 357 358 // vector load/store 359 val nf = Nf() 360 val veew = VEew() 361 362 val isReverse = Bool() // vrsub, vrdiv 363 val isExt = Bool() 364 val isNarrow = Bool() 365 val isDstMask = Bool() // vvm, vvvm, mmm 366 val isOpMask = Bool() // vmand, vmnand 367 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 368 369 def vtype: VType = { 370 val res = Wire(VType()) 371 res.illegal := this.vill 372 res.vma := this.vma 373 res.vta := this.vta 374 res.vsew := this.vsew 375 res.vlmul := this.vlmul 376 res 377 } 378 379 def vconfig: VConfig = { 380 val res = Wire(VConfig()) 381 res.vtype := this.vtype 382 res.vl := this.vl 383 res 384 } 385 386 def connectVType(source: VType): Unit = { 387 this.vill := source.illegal 388 this.vma := source.vma 389 this.vta := source.vta 390 this.vsew := source.vsew 391 this.vlmul := source.vlmul 392 } 393 } 394 395 // DynInst --[IssueQueue]--> DataPath 396 class IssueQueueIssueBundle( 397 iqParams: IssueBlockParams, 398 val exuParams: ExeUnitParams, 399 )(implicit 400 p: Parameters 401 ) extends Bundle { 402 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 403 // check which set both have fp and vec and remove fp 404 private val rfReadDataCfgSetFilterFp = rfReadDataCfgSet.map((set: Set[DataConfig]) => 405 if (set.contains(FpData()) && set.contains(VecData())) set.filter(_ != FpData()) 406 else set 407 ) 408 409 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 410 rfReadDataCfgSetFilterFp.map((set: Set[DataConfig]) => 411 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 412 ) 413 )) 414 415 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 416 val immType = SelImm() // used to select imm extractor 417 val common = new ExuInput(exuParams) 418 val addrOH = UInt(iqParams.numEntries.W) 419 420 def exuIdx = exuParams.exuIdx 421 def getSource: SchedulerType = exuParams.getWBSource 422 def getIntWbBusyBundle = common.rfWen.toSeq 423 def getVfWbBusyBundle = common.getVfWen.toSeq 424 425 def getIntRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 426 rf.zip(srcType).map { 427 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 428 makeValid(issueValid, rfRd.head) 429 }.toSeq 430 } 431 432 def getVfRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 433 rf.zip(srcType).map { 434 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 435 makeValid(issueValid, rfRd.head) 436 }.toSeq 437 } 438 439 def getIntRfWriteValidBundle(issueValid: Bool) = { 440 441 } 442 } 443 444 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 445 val issueQueueParams = this.params 446 val og0resp = Valid(new EntryDeqRespBundle) 447 val og1resp = Valid(new EntryDeqRespBundle) 448 } 449 450 class fuBusyRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 451 val respType = RSFeedbackType() // update credit if needs replay 452 val rfWen = Bool() // TODO: use params to identify IntWB/VfWB 453 val fuType = FuType() 454 } 455 456 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 457 private val intCertainLat = params.intLatencyCertain 458 private val vfCertainLat = params.vfLatencyCertain 459 private val intLat = params.intLatencyValMax 460 private val vfLat = params.vfLatencyValMax 461 462 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 463 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 464 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 465 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 466 } 467 468 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 469 private val intCertainLat = params.intLatencyCertain 470 private val vfCertainLat = params.vfLatencyCertain 471 private val intLat = params.intLatencyValMax 472 private val vfLat = params.vfLatencyValMax 473 474 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 475 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 476 } 477 478 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 479 private val intCertainLat = params.intLatencyCertain 480 private val vfCertainLat = params.vfLatencyCertain 481 482 val intConflict = OptionWrapper(intCertainLat, Bool()) 483 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 484 } 485 486 class ImmInfo extends Bundle { 487 val imm = UInt(32.W) 488 val immType = SelImm() 489 } 490 491 // DataPath --[ExuInput]--> Exu 492 class ExuInput(val params: ExeUnitParams, copyWakeupOut:Boolean = false, copyNum:Int = 0)(implicit p: Parameters) extends XSBundle { 493 val fuType = FuType() 494 val fuOpType = FuOpType() 495 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 496 val imm = UInt(32.W) 497 val robIdx = new RobPtr 498 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 499 val isFirstIssue = Bool() // Only used by store yet 500 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 501 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 502 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 503 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 504 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum,Vec(LoadPipelineWidth, UInt(3.W)))) 505 val pdest = UInt(params.wbPregIdxWidth.W) 506 val rfWen = if (params.needIntWen) Some(Bool()) else None 507 val fpWen = if (params.needFpWen) Some(Bool()) else None 508 val vecWen = if (params.needVecWen) Some(Bool()) else None 509 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 510 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 511 val flushPipe = if (params.flushPipe) Some(Bool()) else None 512 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 513 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 514 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 515 Some(new FtqPtr) else None 516 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 517 Some(UInt(log2Up(PredictWidth).W)) else None 518 val predictInfo = if (params.needPdInfo) Some(new Bundle { 519 val target = UInt(VAddrData().dataWidth.W) 520 val taken = Bool() 521 }) else None 522 val loadWaitBit = OptionWrapper(params.hasLoadExu, Bool()) 523 val waitForRobIdx = OptionWrapper(params.hasLoadExu, new RobPtr) // store set predicted previous store robIdx 524 val storeSetHit = OptionWrapper(params.hasLoadExu, Bool()) // inst has been allocated an store set 525 val loadWaitStrict = OptionWrapper(params.hasLoadExu, Bool()) // load inst will not be executed until ALL former store addr calcuated 526 val ssid = OptionWrapper(params.hasLoadExu, UInt(SSIDWidth.W)) 527 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 528 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 529 val dataSources = Vec(params.numRegSrc, DataSource()) 530 val l1ExuOH = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuOH())) 531 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 532 val loadDependency = OptionWrapper(params.isIQWakeUpSink, Vec(LoadPipelineWidth, UInt(3.W))) 533 534 val perfDebugInfo = new PerfDebugInfo() 535 536 def exuIdx = this.params.exuIdx 537 538 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = { 539 if (params.isIQWakeUpSink) { 540 require( 541 og0CancelOH.getWidth == l1ExuOH.get.head.getWidth, 542 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}" 543 ) 544 val l1Cancel: Bool = l1ExuOH.get.zip(srcTimer.get).map { 545 case(exuOH: UInt, srcTimer: UInt) => 546 (exuOH & og0CancelOH).orR && srcTimer === 1.U 547 }.reduce(_ | _) 548 l1Cancel 549 } else { 550 false.B 551 } 552 } 553 554 def getVfWen = { 555 if (params.writeFpRf) this.fpWen 556 else if(params.writeVecRf) this.vecWen 557 else None 558 } 559 560 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 561 // src is assigned to rfReadData 562 this.fuType := source.common.fuType 563 this.fuOpType := source.common.fuOpType 564 this.imm := source.common.imm 565 this.robIdx := source.common.robIdx 566 this.pdest := source.common.pdest 567 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 568 this.iqIdx := source.common.iqIdx // Only used by mem feedback 569 this.dataSources := source.common.dataSources 570 this.l1ExuOH .foreach(_ := source.common.l1ExuOH.get) 571 this.rfWen .foreach(_ := source.common.rfWen.get) 572 this.fpWen .foreach(_ := source.common.fpWen.get) 573 this.vecWen .foreach(_ := source.common.vecWen.get) 574 this.fpu .foreach(_ := source.common.fpu.get) 575 this.vpu .foreach(_ := source.common.vpu.get) 576 this.flushPipe .foreach(_ := source.common.flushPipe.get) 577 this.pc .foreach(_ := source.common.pc.get) 578 this.preDecode .foreach(_ := source.common.preDecode.get) 579 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 580 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 581 this.predictInfo .foreach(_ := source.common.predictInfo.get) 582 this.loadWaitBit .foreach(_ := source.common.loadWaitBit.get) 583 this.waitForRobIdx .foreach(_ := source.common.waitForRobIdx.get) 584 this.storeSetHit .foreach(_ := source.common.storeSetHit.get) 585 this.loadWaitStrict.foreach(_ := source.common.loadWaitStrict.get) 586 this.ssid .foreach(_ := source.common.ssid.get) 587 this.lqIdx .foreach(_ := source.common.lqIdx.get) 588 this.sqIdx .foreach(_ := source.common.sqIdx.get) 589 this.srcTimer .foreach(_ := source.common.srcTimer.get) 590 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 591 } 592 } 593 594 // ExuInput --[FuncUnit]--> ExuOutput 595 class ExuOutput( 596 val params: ExeUnitParams, 597 )(implicit 598 val p: Parameters 599 ) extends Bundle with BundleSource with HasXSParameter { 600 val data = UInt(params.dataBitsMax.W) 601 val pdest = UInt(params.wbPregIdxWidth.W) 602 val robIdx = new RobPtr 603 val intWen = if (params.needIntWen) Some(Bool()) else None 604 val fpWen = if (params.needFpWen) Some(Bool()) else None 605 val vecWen = if (params.needVecWen) Some(Bool()) else None 606 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 607 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 608 val wflags = if (params.writeFflags) Some(Bool()) else None 609 val vxsat = if (params.writeVxsat) Some(Bool()) else None 610 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 611 val flushPipe = if (params.flushPipe) Some(Bool()) else None 612 val replay = if (params.replayInst) Some(Bool()) else None 613 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 614 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 615 Some(new SqPtr()) else None 616 val trigger = if (params.trigger) Some(new TriggerCf) else None 617 // uop info 618 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 619 // vldu used only 620 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 621 val vpu = new VPUCtrlSignals 622 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 623 val vdIdx = UInt(3.W) 624 val vdIdxInField = UInt(3.W) 625 val isIndexed = Bool() 626 val isMasked = Bool() 627 }) 628 val debug = new DebugBundle 629 val debugInfo = new PerfDebugInfo 630 } 631 632 // ExuOutput + DynInst --> WriteBackBundle 633 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 634 val rfWen = Bool() 635 val fpWen = Bool() 636 val vecWen = Bool() 637 val pdest = UInt(params.pregIdxWidth(backendParams).W) 638 val data = UInt(params.dataWidth.W) 639 val robIdx = new RobPtr()(p) 640 val flushPipe = Bool() 641 val replayInst = Bool() 642 val redirect = ValidIO(new Redirect) 643 val fflags = UInt(5.W) 644 val vxsat = Bool() 645 val exceptionVec = ExceptionVec() 646 val debug = new DebugBundle 647 val debugInfo = new PerfDebugInfo 648 649 this.wakeupSource = s"WB(${params.toString})" 650 651 def fromExuOutput(source: ExuOutput) = { 652 this.rfWen := source.intWen.getOrElse(false.B) 653 this.fpWen := source.fpWen.getOrElse(false.B) 654 this.vecWen := source.vecWen.getOrElse(false.B) 655 this.pdest := source.pdest 656 this.data := source.data 657 this.robIdx := source.robIdx 658 this.flushPipe := source.flushPipe.getOrElse(false.B) 659 this.replayInst := source.replay.getOrElse(false.B) 660 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 661 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 662 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 663 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 664 this.debug := source.debug 665 this.debugInfo := source.debugInfo 666 } 667 668 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 669 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 670 rfWrite.wen := this.rfWen && fire 671 rfWrite.addr := this.pdest 672 rfWrite.data := this.data 673 rfWrite.intWen := this.rfWen 674 rfWrite.fpWen := false.B 675 rfWrite.vecWen := false.B 676 rfWrite 677 } 678 679 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 680 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 681 rfWrite.wen := (this.fpWen || this.vecWen) && fire 682 rfWrite.addr := this.pdest 683 rfWrite.data := this.data 684 rfWrite.intWen := false.B 685 rfWrite.fpWen := this.fpWen 686 rfWrite.vecWen := this.vecWen 687 rfWrite 688 } 689 } 690 691 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 692 // / 693 // [IssueQueue]--> ExuInput -- 694 class ExuBypassBundle( 695 val params: ExeUnitParams, 696 )(implicit 697 val p: Parameters 698 ) extends Bundle { 699 val data = UInt(params.dataBitsMax.W) 700 val pdest = UInt(params.wbPregIdxWidth.W) 701 } 702 703 class ExceptionInfo(implicit p: Parameters) extends XSBundle { 704 val pc = UInt(VAddrData().dataWidth.W) 705 val instr = UInt(32.W) 706 val commitType = CommitType() 707 val exceptionVec = ExceptionVec() 708 val gpaddr = UInt(GPAddrBits.W) 709 val singleStep = Bool() 710 val crossPageIPFFix = Bool() 711 val isInterrupt = Bool() 712 val isHls = Bool() 713 val vls = Bool() 714 val trigger = new TriggerCf 715 } 716 717 object UopIdx { 718 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 719 } 720 721 object FuLatency { 722 def apply(): UInt = UInt(width.W) 723 724 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 725 } 726 727 object ExuOH { 728 def apply(exuNum: Int): UInt = UInt(exuNum.W) 729 730 def apply()(implicit p: Parameters): UInt = UInt(width.W) 731 732 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 733 } 734 735 object ExuVec { 736 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 737 738 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 739 740 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 741 } 742 743 class CancelSignal(implicit p: Parameters) extends XSBundle { 744 val rfWen = Bool() 745 val fpWen = Bool() 746 val vecWen = Bool() 747 val pdest = UInt(PhyRegIdxWidth.W) 748 749 def needCancel(srcType: UInt, psrc: UInt, valid: Bool): Bool = { 750 val pdestMatch = pdest === psrc 751 pdestMatch && ( 752 SrcType.isFp(srcType) && !this.rfWen || 753 SrcType.isXp(srcType) && this.rfWen || 754 SrcType.isVp(srcType) && !this.rfWen 755 ) && valid 756 } 757 } 758 759 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 760 val uop = new DynInst 761 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 762 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 763 val isFirstIssue = Bool() 764 765 def src_rs1 = src(0) 766 def src_stride = src(1) 767 def src_vs3 = src(2) 768 def src_mask = if (isVector) src(3) else 0.U 769 def src_vl = if (isVector) src(4) else 0.U 770 } 771 772 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 773 val uop = new DynInst 774 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 775 val mask = if (isVector) Some(UInt(VLEN.W)) else None 776 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 777 val vdIdxInField = if (isVector) Some(UInt(3.W)) else None 778 val debug = new DebugBundle 779 780 def isVls = FuType.isVls(uop.fuType) 781 } 782 783 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 784 val uop = new DynInst 785 val flag = UInt(1.W) 786 } 787 788 object LoadShouldCancel { 789 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 790 val ld1Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld1Cancel)).map { case (dep, cancel) => cancel && dep(1)}.reduce(_ || _)) 791 val ld2Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld2Cancel)).map { case (dep, cancel) => cancel && dep(2)}.reduce(_ || _)) 792 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 793 } 794 } 795} 796