1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, SchedulerType} 19import xiangshan.backend.issue.EntryBundles._ 20import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 21import xiangshan.backend.rob.RobPtr 22import xiangshan.frontend._ 23import xiangshan.mem.{LqPtr, SqPtr} 24import yunsuan.vector.VIFuParam 25import xiangshan.backend.trace._ 26 27object Bundles { 28 /** 29 * Connect Same Name Port like bundleSource := bundleSinkBudle. 30 * 31 * There is no limit to the number of ports on both sides. 32 * 33 * Don't forget to connect the remaining ports! 34 */ 35 def connectSamePort (bundleSource: Bundle, bundleSink: Bundle):Unit = { 36 bundleSource.elements.foreach { case (name, data) => 37 if (bundleSink.elements.contains(name)) 38 data := bundleSink.elements(name) 39 } 40 } 41 // frontend -> backend 42 class StaticInst(implicit p: Parameters) extends XSBundle { 43 val instr = UInt(32.W) 44 val pc = UInt(VAddrBits.W) 45 val foldpc = UInt(MemPredPCWidth.W) 46 val exceptionVec = ExceptionVec() 47 val isFetchMalAddr = Bool() 48 val trigger = TriggerAction() 49 val preDecodeInfo = new PreDecodeInfo 50 val pred_taken = Bool() 51 val crossPageIPFFix = Bool() 52 val ftqPtr = new FtqPtr 53 val ftqOffset = UInt(log2Up(PredictWidth).W) 54 55 def connectCtrlFlow(source: CtrlFlow): Unit = { 56 this.instr := source.instr 57 this.pc := source.pc 58 this.foldpc := source.foldpc 59 this.exceptionVec := source.exceptionVec 60 this.isFetchMalAddr := source.exceptionFromBackend 61 this.trigger := source.trigger 62 this.preDecodeInfo := source.pd 63 this.pred_taken := source.pred_taken 64 this.crossPageIPFFix := source.crossPageIPFFix 65 this.ftqPtr := source.ftqPtr 66 this.ftqOffset := source.ftqOffset 67 } 68 } 69 70 // StaticInst --[Decode]--> DecodedInst 71 class DecodedInst(implicit p: Parameters) extends XSBundle { 72 def numSrc = backendParams.numSrc 73 // passed from StaticInst 74 val instr = UInt(32.W) 75 val pc = UInt(VAddrBits.W) 76 val foldpc = UInt(MemPredPCWidth.W) 77 val exceptionVec = ExceptionVec() 78 val isFetchMalAddr = Bool() 79 val trigger = TriggerAction() 80 val preDecodeInfo = new PreDecodeInfo 81 val pred_taken = Bool() 82 val crossPageIPFFix = Bool() 83 val ftqPtr = new FtqPtr 84 val ftqOffset = UInt(log2Up(PredictWidth).W) 85 // decoded 86 val srcType = Vec(numSrc, SrcType()) 87 val lsrc = Vec(numSrc, UInt(LogicRegsWidth.W)) 88 val ldest = UInt(LogicRegsWidth.W) 89 val fuType = FuType() 90 val fuOpType = FuOpType() 91 val rfWen = Bool() 92 val fpWen = Bool() 93 val vecWen = Bool() 94 val v0Wen = Bool() 95 val vlWen = Bool() 96 val isXSTrap = Bool() 97 val waitForward = Bool() // no speculate execution 98 val blockBackward = Bool() 99 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 100 val canRobCompress = Bool() 101 val selImm = SelImm() 102 val imm = UInt(ImmUnion.maxLen.W) 103 val fpu = new FPUCtrlSignals 104 val vpu = new VPUCtrlSignals 105 val vlsInstr = Bool() 106 val wfflags = Bool() 107 val isMove = Bool() 108 val uopIdx = UopIdx() 109 val uopSplitType = UopSplitType() 110 val isVset = Bool() 111 val firstUop = Bool() 112 val lastUop = Bool() 113 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 114 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 115 val commitType = CommitType() // Todo: remove it 116 val needFrm = new NeedFrmBundle 117 118 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 119 120 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 121 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 122 123 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 124 val decoder: Seq[UInt] = ListLookup( 125 inst, XDecode.decodeDefault.map(bitPatToUInt), 126 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 127 ) 128 allSignals zip decoder foreach { case (s, d) => s := d } 129 debug_fuType.foreach(_ := fuType) 130 this 131 } 132 133 def isSoftPrefetch: Bool = { 134 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 135 } 136 137 def connectStaticInst(source: StaticInst): Unit = { 138 for ((name, data) <- this.elements) { 139 if (source.elements.contains(name)) { 140 data := source.elements(name) 141 } 142 } 143 } 144 } 145 146 class TrapInstInfo(implicit p: Parameters) extends XSBundle { 147 val instr = UInt(32.W) 148 val ftqPtr = new FtqPtr 149 val ftqOffset = UInt(log2Up(PredictWidth).W) 150 151 def needFlush(ftqPtr: FtqPtr, ftqOffset: UInt): Bool ={ 152 val sameFlush = this.ftqPtr === ftqPtr && this.ftqOffset > ftqOffset 153 sameFlush || isAfter(this.ftqPtr, ftqPtr) 154 } 155 156 def fromDecodedInst(decodedInst: DecodedInst): this.type = { 157 this.instr := decodedInst.instr 158 this.ftqPtr := decodedInst.ftqPtr 159 this.ftqOffset := decodedInst.ftqOffset 160 this 161 } 162 } 163 164 // DecodedInst --[Rename]--> DynInst 165 class DynInst(implicit p: Parameters) extends XSBundle { 166 def numSrc = backendParams.numSrc 167 // passed from StaticInst 168 val instr = UInt(32.W) 169 val pc = UInt(VAddrBits.W) 170 val foldpc = UInt(MemPredPCWidth.W) 171 val exceptionVec = ExceptionVec() 172 val isFetchMalAddr = Bool() 173 val hasException = Bool() 174 val trigger = TriggerAction() 175 val preDecodeInfo = new PreDecodeInfo 176 val pred_taken = Bool() 177 val crossPageIPFFix = Bool() 178 val ftqPtr = new FtqPtr 179 val ftqOffset = UInt(log2Up(PredictWidth).W) 180 // passed from DecodedInst 181 val srcType = Vec(numSrc, SrcType()) 182 val ldest = UInt(LogicRegsWidth.W) 183 val fuType = FuType() 184 val fuOpType = FuOpType() 185 val rfWen = Bool() 186 val fpWen = Bool() 187 val vecWen = Bool() 188 val v0Wen = Bool() 189 val vlWen = Bool() 190 val isXSTrap = Bool() 191 val waitForward = Bool() // no speculate execution 192 val blockBackward = Bool() 193 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 194 val canRobCompress = Bool() 195 val selImm = SelImm() 196 val imm = UInt(32.W) 197 val fpu = new FPUCtrlSignals 198 val vpu = new VPUCtrlSignals 199 val vlsInstr = Bool() 200 val wfflags = Bool() 201 val isMove = Bool() 202 val uopIdx = UopIdx() 203 val isVset = Bool() 204 val firstUop = Bool() 205 val lastUop = Bool() 206 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 207 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 208 val commitType = CommitType() 209 // rename 210 val srcState = Vec(numSrc, SrcState()) 211 val srcLoadDependency = Vec(numSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 212 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 213 val pdest = UInt(PhyRegIdxWidth.W) 214 // reg cache 215 val useRegCache = Vec(backendParams.numIntRegSrc, Bool()) 216 val regCacheIdx = Vec(backendParams.numIntRegSrc, UInt(RegCacheIdxWidth.W)) 217 val robIdx = new RobPtr 218 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 219 val dirtyFs = Bool() 220 val dirtyVs = Bool() 221 val traceBlockInPipe = new TracePipe(log2Up(RenameWidth * 2)) 222 223 val eliminatedMove = Bool() 224 // Take snapshot at this CFI inst 225 val snapshot = Bool() 226 val debugInfo = new PerfDebugInfo 227 val storeSetHit = Bool() // inst has been allocated an store set 228 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 229 // Load wait is needed 230 // load inst will not be executed until former store (predicted by mdp) addr calcuated 231 val loadWaitBit = Bool() 232 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 233 // load inst will not be executed until ALL former store addr calcuated 234 val loadWaitStrict = Bool() 235 val ssid = UInt(SSIDWidth.W) 236 // Todo 237 val lqIdx = new LqPtr 238 val sqIdx = new SqPtr 239 // debug module 240 val singleStep = Bool() 241 // schedule 242 val replayInst = Bool() 243 244 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 245 246 val numLsElem = NumLsElem() 247 248 def getDebugFuType: UInt = debug_fuType.getOrElse(fuType) 249 250 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 251 def isLUI32: Bool = this.selImm === SelImm.IMM_LUI32 252 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 253 254 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 255 def isSvinval(flush: Bool) = FuType.isFence(fuType) && 256 Cat(Seq(FenceOpType.sfence, FenceOpType.hfence_v, FenceOpType.hfence_g).map(_ === fuOpType)).orR && !flush 257 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 258 def isNotSvinval = !FuType.isFence(fuType) 259 260 def isHls: Bool = { 261 fuType === FuType.ldu.U && LSUOpType.isHlv(fuOpType) || fuType === FuType.stu.U && LSUOpType.isHsv(fuOpType) 262 } 263 264 def srcIsReady: Vec[Bool] = { 265 VecInit(this.srcType.zip(this.srcState).map { 266 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 267 }) 268 } 269 270 def clearExceptions( 271 exceptionBits: Seq[Int] = Seq(), 272 flushPipe : Boolean = false, 273 replayInst : Boolean = false 274 ): DynInst = { 275 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 276 if (!flushPipe) { this.flushPipe := false.B } 277 if (!replayInst) { this.replayInst := false.B } 278 this 279 } 280 281 def needWriteRf: Bool = rfWen || fpWen || vecWen || v0Wen || vlWen 282 } 283 284 trait BundleSource { 285 var wakeupSource = "undefined" 286 var idx = 0 287 } 288 289 /** 290 * 291 * @param pregIdxWidth index width of preg 292 * @param exuIndices exu indices of wakeup bundle 293 */ 294 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int])(implicit p: Parameters) extends XSBundle { 295 val rfWen = Bool() 296 val fpWen = Bool() 297 val vecWen = Bool() 298 val v0Wen = Bool() 299 val vlWen = Bool() 300 val pdest = UInt(pregIdxWidth.W) 301 302 /** 303 * @param successor Seq[(psrc, srcType)] 304 * @return Seq[if wakeup psrc] 305 */ 306 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 307 successor.map { case (thatPsrc, srcType) => 308 val pdestMatch = pdest === thatPsrc 309 pdestMatch && ( 310 SrcType.isFp(srcType) && this.fpWen || 311 SrcType.isXp(srcType) && this.rfWen || 312 SrcType.isVp(srcType) && this.vecWen 313 ) && valid 314 } 315 } 316 def wakeUpV0(successor: (UInt, UInt), valid: Bool): Bool = { 317 val (thatPsrc, srcType) = successor 318 val pdestMatch = pdest === thatPsrc 319 pdestMatch && ( 320 SrcType.isV0(srcType) && this.v0Wen 321 ) && valid 322 } 323 def wakeUpVl(successor: (UInt, UInt), valid: Bool): Bool = { 324 val (thatPsrc, srcType) = successor 325 val pdestMatch = pdest === thatPsrc 326 pdestMatch && ( 327 SrcType.isVp(srcType) && this.vlWen 328 ) && valid 329 } 330 def wakeUpFromIQ(successor: Seq[(UInt, UInt)]): Seq[Bool] = { 331 successor.map { case (thatPsrc, srcType) => 332 val pdestMatch = pdest === thatPsrc 333 pdestMatch && ( 334 SrcType.isFp(srcType) && this.fpWen || 335 SrcType.isXp(srcType) && this.rfWen || 336 SrcType.isVp(srcType) && this.vecWen 337 ) 338 } 339 } 340 def wakeUpV0FromIQ(successor: (UInt, UInt)): Bool = { 341 val (thatPsrc, srcType) = successor 342 val pdestMatch = pdest === thatPsrc 343 pdestMatch && ( 344 SrcType.isV0(srcType) && this.v0Wen 345 ) 346 } 347 def wakeUpVlFromIQ(successor: (UInt, UInt)): Bool = { 348 val (thatPsrc, srcType) = successor 349 val pdestMatch = pdest === thatPsrc 350 pdestMatch && ( 351 SrcType.isVp(srcType) && this.vlWen 352 ) 353 } 354 355 def hasOnlyOneSource: Boolean = exuIndices.size == 1 356 357 def hasMultiSources: Boolean = exuIndices.size > 1 358 359 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 360 361 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 362 363 def exuIdx: Int = { 364 require(hasOnlyOneSource) 365 this.exuIndices.head 366 } 367 } 368 369 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams)(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 370 371 } 372 373 class IssueQueueIQWakeUpBundle( 374 exuIdx: Int, 375 backendParams: BackendParams, 376 copyWakeupOut: Boolean = false, 377 copyNum: Int = 0 378 )(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 379 val loadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 380 val is0Lat = Bool() 381 val params = backendParams.allExuParams.filter(_.exuIdx == exuIdx).head 382 val rcDest = OptionWrapper(params.needWriteRegCache, UInt(RegCacheIdxWidth.W)) 383 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 384 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 385 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 386 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 387 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 388 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 389 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 390 391 def fromExuInput(exuInput: ExuInput): Unit = { 392 this.rfWen := exuInput.rfWen.getOrElse(false.B) 393 this.fpWen := exuInput.fpWen.getOrElse(false.B) 394 this.vecWen := exuInput.vecWen.getOrElse(false.B) 395 this.v0Wen := exuInput.v0Wen.getOrElse(false.B) 396 this.vlWen := exuInput.vlWen.getOrElse(false.B) 397 this.pdest := exuInput.pdest 398 } 399 } 400 401 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 402 // vtype 403 val vill = Bool() 404 val vma = Bool() // 1: agnostic, 0: undisturbed 405 val vta = Bool() // 1: agnostic, 0: undisturbed 406 val vsew = VSew() 407 val vlmul = VLmul() // 1/8~8 --> -3~3 408 409 // spec vtype 410 val specVill = Bool() 411 val specVma = Bool() // 1: agnostic, 0: undisturbed 412 val specVta = Bool() // 1: agnostic, 0: undisturbed 413 val specVsew = VSew() 414 val specVlmul = VLmul() // 1/8~8 --> -3~3 415 416 val vm = Bool() // 0: need v0.t 417 val vstart = Vl() 418 419 // float rounding mode 420 val frm = Frm() 421 // scalar float instr and vector float reduction 422 val fpu = Fpu() 423 // vector fix int rounding mode 424 val vxrm = Vxrm() 425 // vector uop index, exclude other non-vector uop 426 val vuopIdx = UopIdx() 427 val lastUop = Bool() 428 // maybe used if data dependancy 429 val vmask = UInt(V0Data().dataWidth.W) 430 val vl = Vl() 431 432 // vector load/store 433 val nf = Nf() 434 val veew = VEew() 435 436 val isReverse = Bool() // vrsub, vrdiv 437 val isExt = Bool() 438 val isNarrow = Bool() 439 val isDstMask = Bool() // vvm, vvvm, mmm 440 val isOpMask = Bool() // vmand, vmnand 441 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 442 443 val isDependOldvd = Bool() // some instruction's computation depends on oldvd 444 val isWritePartVd = Bool() // some instruction's computation writes part of vd, such as vredsum 445 446 val isVleff = Bool() // vleff 447 448 def vtype: VType = { 449 val res = Wire(VType()) 450 res.illegal := this.vill 451 res.vma := this.vma 452 res.vta := this.vta 453 res.vsew := this.vsew 454 res.vlmul := this.vlmul 455 res 456 } 457 458 def specVType: VType = { 459 val res = Wire(VType()) 460 res.illegal := this.specVill 461 res.vma := this.specVma 462 res.vta := this.specVta 463 res.vsew := this.specVsew 464 res.vlmul := this.specVlmul 465 res 466 } 467 468 def vconfig: VConfig = { 469 val res = Wire(VConfig()) 470 res.vtype := this.vtype 471 res.vl := this.vl 472 res 473 } 474 475 def connectVType(source: VType): Unit = { 476 this.vill := source.illegal 477 this.vma := source.vma 478 this.vta := source.vta 479 this.vsew := source.vsew 480 this.vlmul := source.vlmul 481 } 482 } 483 484 class NeedFrmBundle(implicit p: Parameters) extends XSBundle { 485 val scalaNeedFrm = Bool() 486 val vectorNeedFrm = Bool() 487 } 488 489 // DynInst --[IssueQueue]--> DataPath 490 class IssueQueueIssueBundle( 491 iqParams: IssueBlockParams, 492 val exuParams: ExeUnitParams, 493 )(implicit 494 p: Parameters 495 ) extends XSBundle { 496 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 497 498 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 499 rfReadDataCfgSet.map((set: Set[DataConfig]) => 500 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 501 ) 502 )) 503 504 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 505 val rcIdx = OptionWrapper(exuParams.needReadRegCache, Vec(exuParams.numRegSrc, UInt(RegCacheIdxWidth.W))) // used to select regcache data 506 val immType = SelImm() // used to select imm extractor 507 val common = new ExuInput(exuParams) 508 val addrOH = UInt(iqParams.numEntries.W) 509 510 def exuIdx = exuParams.exuIdx 511 def getSource: SchedulerType = exuParams.getWBSource 512 513 def getRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 514 rf.zip(srcType).map { 515 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 516 makeValid(issueValid, rfRd.head) 517 }.toSeq 518 } 519 } 520 521 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 522 val issueQueueParams = this.params 523 val og0resp = Valid(new EntryDeqRespBundle) 524 val og1resp = Valid(new EntryDeqRespBundle) 525 } 526 527 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 528 private val intCertainLat = params.intLatencyCertain 529 private val fpCertainLat = params.fpLatencyCertain 530 private val vfCertainLat = params.vfLatencyCertain 531 private val v0CertainLat = params.v0LatencyCertain 532 private val vlCertainLat = params.vlLatencyCertain 533 private val intLat = params.intLatencyValMax 534 private val fpLat = params.fpLatencyValMax 535 private val vfLat = params.vfLatencyValMax 536 private val v0Lat = params.v0LatencyValMax 537 private val vlLat = params.vlLatencyValMax 538 539 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 540 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 541 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 542 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 543 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 544 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 545 val fpDeqRespSet = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 546 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 547 val v0DeqRespSet = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 548 val vlDeqRespSet = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 549 } 550 551 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 552 private val intCertainLat = params.intLatencyCertain 553 private val fpCertainLat = params.fpLatencyCertain 554 private val vfCertainLat = params.vfLatencyCertain 555 private val v0CertainLat = params.v0LatencyCertain 556 private val vlCertainLat = params.vlLatencyCertain 557 private val intLat = params.intLatencyValMax 558 private val fpLat = params.fpLatencyValMax 559 private val vfLat = params.vfLatencyValMax 560 private val v0Lat = params.v0LatencyValMax 561 private val vlLat = params.vlLatencyValMax 562 563 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 564 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 565 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 566 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 567 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 568 } 569 570 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 571 private val intCertainLat = params.intLatencyCertain 572 private val fpCertainLat = params.fpLatencyCertain 573 private val vfCertainLat = params.vfLatencyCertain 574 private val v0CertainLat = params.v0LatencyCertain 575 private val vlCertainLat = params.vlLatencyCertain 576 577 val intConflict = OptionWrapper(intCertainLat, Bool()) 578 val fpConflict = OptionWrapper(fpCertainLat, Bool()) 579 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 580 val v0Conflict = OptionWrapper(v0CertainLat, Bool()) 581 val vlConflict = OptionWrapper(vlCertainLat, Bool()) 582 } 583 584 class ImmInfo extends Bundle { 585 val imm = UInt(32.W) 586 val immType = SelImm() 587 } 588 589 // DataPath --[ExuInput]--> Exu 590 class ExuInput(val params: ExeUnitParams, copyWakeupOut:Boolean = false, copyNum:Int = 0)(implicit p: Parameters) extends XSBundle { 591 val fuType = FuType() 592 val fuOpType = FuOpType() 593 val src = Vec(params.numRegSrc, UInt(params.srcDataBitsMax.W)) 594 val imm = UInt(32.W) 595 val robIdx = new RobPtr 596 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 597 val isFirstIssue = Bool() // Only used by store yet 598 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 599 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 600 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 601 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 602 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 603 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 604 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 605 val pdest = UInt(params.wbPregIdxWidth.W) 606 val rfWen = if (params.needIntWen) Some(Bool()) else None 607 val fpWen = if (params.needFpWen) Some(Bool()) else None 608 val vecWen = if (params.needVecWen) Some(Bool()) else None 609 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 610 val vlWen = if (params.needVlWen) Some(Bool()) else None 611 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 612 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 613 val flushPipe = if (params.flushPipe) Some(Bool()) else None 614 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 615 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 616 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 617 Some(new FtqPtr) else None 618 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 619 Some(UInt(log2Up(PredictWidth).W)) else None 620 val predictInfo = if (params.needPdInfo) Some(new Bundle { 621 val target = UInt(VAddrData().dataWidth.W) 622 val taken = Bool() 623 }) else None 624 val loadWaitBit = OptionWrapper(params.hasLoadExu, Bool()) 625 val waitForRobIdx = OptionWrapper(params.hasLoadExu, new RobPtr) // store set predicted previous store robIdx 626 val storeSetHit = OptionWrapper(params.hasLoadExu, Bool()) // inst has been allocated an store set 627 val loadWaitStrict = OptionWrapper(params.hasLoadExu, Bool()) // load inst will not be executed until ALL former store addr calcuated 628 val ssid = OptionWrapper(params.hasLoadExu, UInt(SSIDWidth.W)) 629 // only vector load store need 630 val numLsElem = OptionWrapper(params.hasVecLsFu, NumLsElem()) 631 632 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 633 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 634 val dataSources = Vec(params.numRegSrc, DataSource()) 635 val l1ExuOH = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuVec())) 636 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 637 val loadDependency = OptionWrapper(params.needLoadDependency, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 638 639 val perfDebugInfo = new PerfDebugInfo() 640 641 def exuIdx = this.params.exuIdx 642 643 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = { 644 if (params.isIQWakeUpSink) { 645 require( 646 og0CancelOH.getWidth == l1ExuOH.get.head.getWidth, 647 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}" 648 ) 649 val l1Cancel: Bool = l1ExuOH.get.zip(srcTimer.get).map { 650 case(exuOH: Vec[Bool], srcTimer: UInt) => 651 (exuOH.asUInt & og0CancelOH).orR && srcTimer === 1.U 652 }.reduce(_ | _) 653 l1Cancel 654 } else { 655 false.B 656 } 657 } 658 659 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 660 // src is assigned to rfReadData 661 this.fuType := source.common.fuType 662 this.fuOpType := source.common.fuOpType 663 this.imm := source.common.imm 664 this.robIdx := source.common.robIdx 665 this.pdest := source.common.pdest 666 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 667 this.iqIdx := source.common.iqIdx // Only used by mem feedback 668 this.dataSources := source.common.dataSources 669 this.l1ExuOH .foreach(_ := source.common.l1ExuOH.get) 670 this.rfWen .foreach(_ := source.common.rfWen.get) 671 this.fpWen .foreach(_ := source.common.fpWen.get) 672 this.vecWen .foreach(_ := source.common.vecWen.get) 673 this.v0Wen .foreach(_ := source.common.v0Wen.get) 674 this.vlWen .foreach(_ := source.common.vlWen.get) 675 this.fpu .foreach(_ := source.common.fpu.get) 676 this.vpu .foreach(_ := source.common.vpu.get) 677 this.flushPipe .foreach(_ := source.common.flushPipe.get) 678 this.pc .foreach(_ := source.common.pc.get) 679 this.preDecode .foreach(_ := source.common.preDecode.get) 680 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 681 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 682 this.predictInfo .foreach(_ := source.common.predictInfo.get) 683 this.loadWaitBit .foreach(_ := source.common.loadWaitBit.get) 684 this.waitForRobIdx .foreach(_ := source.common.waitForRobIdx.get) 685 this.storeSetHit .foreach(_ := source.common.storeSetHit.get) 686 this.loadWaitStrict.foreach(_ := source.common.loadWaitStrict.get) 687 this.ssid .foreach(_ := source.common.ssid.get) 688 this.lqIdx .foreach(_ := source.common.lqIdx.get) 689 this.sqIdx .foreach(_ := source.common.sqIdx.get) 690 this.numLsElem .foreach(_ := source.common.numLsElem.get) 691 this.srcTimer .foreach(_ := source.common.srcTimer.get) 692 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 693 } 694 } 695 696 // ExuInput --[FuncUnit]--> ExuOutput 697 class ExuOutput( 698 val params: ExeUnitParams, 699 )(implicit 700 val p: Parameters 701 ) extends Bundle with BundleSource with HasXSParameter { 702 val data = Vec(params.wbPathNum, UInt(params.destDataBitsMax.W)) 703 val pdest = UInt(params.wbPregIdxWidth.W) 704 val robIdx = new RobPtr 705 val intWen = if (params.needIntWen) Some(Bool()) else None 706 val fpWen = if (params.needFpWen) Some(Bool()) else None 707 val vecWen = if (params.needVecWen) Some(Bool()) else None 708 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 709 val vlWen = if (params.needVlWen) Some(Bool()) else None 710 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 711 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 712 val wflags = if (params.writeFflags) Some(Bool()) else None 713 val vxsat = if (params.writeVxsat) Some(Bool()) else None 714 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 715 val flushPipe = if (params.flushPipe) Some(Bool()) else None 716 val replay = if (params.replayInst) Some(Bool()) else None 717 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 718 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 719 Some(new SqPtr()) else None 720 val trigger = if (params.trigger) Some(TriggerAction()) else None 721 // uop info 722 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 723 // vldu used only 724 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 725 val vpu = new VPUCtrlSignals 726 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 727 val vdIdx = UInt(3.W) 728 val vdIdxInField = UInt(3.W) 729 val isIndexed = Bool() 730 val isMasked = Bool() 731 val isStrided = Bool() 732 val isWhole = Bool() 733 val isVecLoad = Bool() 734 val isVlm = Bool() 735 }) 736 val debug = new DebugBundle 737 val debugInfo = new PerfDebugInfo 738 } 739 740 // ExuOutput + DynInst --> WriteBackBundle 741 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 742 val rfWen = Bool() 743 val fpWen = Bool() 744 val vecWen = Bool() 745 val v0Wen = Bool() 746 val vlWen = Bool() 747 val pdest = UInt(params.pregIdxWidth(backendParams).W) 748 val data = UInt(params.dataWidth.W) 749 val robIdx = new RobPtr()(p) 750 val flushPipe = Bool() 751 val replayInst = Bool() 752 val redirect = ValidIO(new Redirect) 753 val fflags = UInt(5.W) 754 val vxsat = Bool() 755 val exceptionVec = ExceptionVec() 756 val debug = new DebugBundle 757 val debugInfo = new PerfDebugInfo 758 759 this.wakeupSource = s"WB(${params.toString})" 760 761 def fromExuOutput(source: ExuOutput, wbType: String) = { 762 val typeMap = Map("int" -> 0, "fp" -> 1, "vf" -> 2, "v0" -> 3, "vl" -> 4) 763 this.rfWen := source.intWen.getOrElse(false.B) 764 this.fpWen := source.fpWen.getOrElse(false.B) 765 this.vecWen := source.vecWen.getOrElse(false.B) 766 this.v0Wen := source.v0Wen.getOrElse(false.B) 767 this.vlWen := source.vlWen.getOrElse(false.B) 768 this.pdest := source.pdest 769 this.data := source.data(source.params.wbIndex(typeMap(wbType))) 770 this.robIdx := source.robIdx 771 this.flushPipe := source.flushPipe.getOrElse(false.B) 772 this.replayInst := source.replay.getOrElse(false.B) 773 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 774 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 775 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 776 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 777 this.debug := source.debug 778 this.debugInfo := source.debugInfo 779 } 780 781 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 782 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 783 rfWrite.wen := this.rfWen && fire 784 rfWrite.addr := this.pdest 785 rfWrite.data := this.data 786 rfWrite.intWen := this.rfWen 787 rfWrite.fpWen := false.B 788 rfWrite.vecWen := false.B 789 rfWrite.v0Wen := false.B 790 rfWrite.vlWen := false.B 791 rfWrite 792 } 793 794 def asFpRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 795 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(FpData()).addrWidth))) 796 rfWrite.wen := this.fpWen && fire 797 rfWrite.addr := this.pdest 798 rfWrite.data := this.data 799 rfWrite.intWen := false.B 800 rfWrite.fpWen := this.fpWen 801 rfWrite.vecWen := false.B 802 rfWrite.v0Wen := false.B 803 rfWrite.vlWen := false.B 804 rfWrite 805 } 806 807 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 808 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 809 rfWrite.wen := this.vecWen && fire 810 rfWrite.addr := this.pdest 811 rfWrite.data := this.data 812 rfWrite.intWen := false.B 813 rfWrite.fpWen := false.B 814 rfWrite.vecWen := this.vecWen 815 rfWrite.v0Wen := false.B 816 rfWrite.vlWen := false.B 817 rfWrite 818 } 819 820 def asV0RfWriteBundle(fire: Bool): RfWritePortWithConfig = { 821 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(V0Data()).addrWidth))) 822 rfWrite.wen := this.v0Wen && fire 823 rfWrite.addr := this.pdest 824 rfWrite.data := this.data 825 rfWrite.intWen := false.B 826 rfWrite.fpWen := false.B 827 rfWrite.vecWen := false.B 828 rfWrite.v0Wen := this.v0Wen 829 rfWrite.vlWen := false.B 830 rfWrite 831 } 832 833 def asVlRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 834 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VlData()).addrWidth))) 835 rfWrite.wen := this.vlWen && fire 836 rfWrite.addr := this.pdest 837 rfWrite.data := this.data 838 rfWrite.intWen := false.B 839 rfWrite.fpWen := false.B 840 rfWrite.vecWen := false.B 841 rfWrite.v0Wen := false.B 842 rfWrite.vlWen := this.vlWen 843 rfWrite 844 } 845 } 846 847 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 848 // / 849 // [IssueQueue]--> ExuInput -- 850 class ExuBypassBundle( 851 val params: ExeUnitParams, 852 )(implicit p: Parameters) extends XSBundle { 853 val intWen = Bool() 854 val data = UInt(params.destDataBitsMax.W) 855 val pdest = UInt(params.wbPregIdxWidth.W) 856 } 857 858 class ExceptionInfo(implicit p: Parameters) extends XSBundle { 859 val pc = UInt(VAddrData().dataWidth.W) 860 val instr = UInt(32.W) 861 val commitType = CommitType() 862 val exceptionVec = ExceptionVec() 863 val isFetchMalAddr = Bool() 864 val gpaddr = UInt(XLEN.W) 865 val singleStep = Bool() 866 val crossPageIPFFix = Bool() 867 val isInterrupt = Bool() 868 val isHls = Bool() 869 val vls = Bool() 870 val trigger = TriggerAction() 871 val isForVSnonLeafPTE = Bool() 872 } 873 874 object UopIdx { 875 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 876 } 877 878 object FuLatency { 879 def apply(): UInt = UInt(width.W) 880 881 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 882 } 883 884 object ExuOH { 885 def apply(exuNum: Int): UInt = UInt(exuNum.W) 886 887 def apply()(implicit p: Parameters): UInt = UInt(width.W) 888 889 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 890 } 891 892 object ExuVec { 893 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 894 895 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 896 897 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 898 } 899 900 class CancelSignal(implicit p: Parameters) extends XSBundle { 901 val rfWen = Bool() 902 val fpWen = Bool() 903 val vecWen = Bool() 904 val v0Wen = Bool() 905 val vlWen = Bool() 906 val pdest = UInt(PhyRegIdxWidth.W) 907 } 908 909 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 910 val uop = new DynInst 911 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 912 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 913 val isFirstIssue = Bool() 914 val flowNum = OptionWrapper(isVector, NumLsElem()) 915 916 def src_rs1 = src(0) 917 def src_stride = src(1) 918 def src_vs3 = src(2) 919 def src_mask = if (isVector) src(3) else 0.U 920 def src_vl = if (isVector) src(4) else 0.U 921 } 922 923 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 924 val uop = new DynInst 925 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 926 val mask = if (isVector) Some(UInt(VLEN.W)) else None 927 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 928 val vdIdxInField = if (isVector) Some(UInt(3.W)) else None 929 val debug = new DebugBundle 930 931 def isVls = FuType.isVls(uop.fuType) 932 } 933 934 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 935 val uop = new DynInst 936 val flag = UInt(1.W) 937 } 938 939 object LoadShouldCancel { 940 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 941 val ld1Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld1Cancel)).map { case (dep, cancel) => cancel && dep(0)}.reduce(_ || _)) 942 val ld2Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld2Cancel)).map { case (dep, cancel) => cancel && dep(1)}.reduce(_ || _)) 943 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 944 } 945 } 946} 947