1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, SchedulerType} 19import xiangshan.backend.issue.EntryBundles._ 20import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 21import xiangshan.backend.rob.RobPtr 22import xiangshan.frontend._ 23import xiangshan.mem.{LqPtr, SqPtr} 24import yunsuan.vector.VIFuParam 25 26object Bundles { 27 /** 28 * Connect Same Name Port like bundleSource := bundleSinkBudle. 29 * 30 * There is no limit to the number of ports on both sides. 31 * 32 * Don't forget to connect the remaining ports! 33 */ 34 def connectSamePort (bundleSource: Bundle, bundleSink: Bundle):Unit = { 35 bundleSource.elements.foreach { case (name, data) => 36 if (bundleSink.elements.contains(name)) 37 data := bundleSink.elements(name) 38 } 39 } 40 // frontend -> backend 41 class StaticInst(implicit p: Parameters) extends XSBundle { 42 val instr = UInt(32.W) 43 val pc = UInt(VAddrBits.W) 44 val foldpc = UInt(MemPredPCWidth.W) 45 val exceptionVec = ExceptionVec() 46 val trigger = new TriggerCf 47 val preDecodeInfo = new PreDecodeInfo 48 val pred_taken = Bool() 49 val crossPageIPFFix = Bool() 50 val ftqPtr = new FtqPtr 51 val ftqOffset = UInt(log2Up(PredictWidth).W) 52 53 def connectCtrlFlow(source: CtrlFlow): Unit = { 54 this.instr := source.instr 55 this.pc := source.pc 56 this.foldpc := source.foldpc 57 this.exceptionVec := source.exceptionVec 58 this.trigger := source.trigger 59 this.preDecodeInfo := source.pd 60 this.pred_taken := source.pred_taken 61 this.crossPageIPFFix := source.crossPageIPFFix 62 this.ftqPtr := source.ftqPtr 63 this.ftqOffset := source.ftqOffset 64 } 65 } 66 67 // StaticInst --[Decode]--> DecodedInst 68 class DecodedInst(implicit p: Parameters) extends XSBundle { 69 def numSrc = backendParams.numSrc 70 // passed from StaticInst 71 val instr = UInt(32.W) 72 val pc = UInt(VAddrBits.W) 73 val foldpc = UInt(MemPredPCWidth.W) 74 val exceptionVec = ExceptionVec() 75 val trigger = new TriggerCf 76 val preDecodeInfo = new PreDecodeInfo 77 val pred_taken = Bool() 78 val crossPageIPFFix = Bool() 79 val ftqPtr = new FtqPtr 80 val ftqOffset = UInt(log2Up(PredictWidth).W) 81 // decoded 82 val srcType = Vec(numSrc, SrcType()) 83 val lsrc = Vec(numSrc, UInt(LogicRegsWidth.W)) 84 val ldest = UInt(LogicRegsWidth.W) 85 val fuType = FuType() 86 val fuOpType = FuOpType() 87 val rfWen = Bool() 88 val fpWen = Bool() 89 val vecWen = Bool() 90 val v0Wen = Bool() 91 val vlWen = Bool() 92 val isXSTrap = Bool() 93 val waitForward = Bool() // no speculate execution 94 val blockBackward = Bool() 95 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 96 val canRobCompress = Bool() 97 val selImm = SelImm() 98 val imm = UInt(ImmUnion.maxLen.W) 99 val fpu = new FPUCtrlSignals 100 val vpu = new VPUCtrlSignals 101 val vlsInstr = Bool() 102 val wfflags = Bool() 103 val isMove = Bool() 104 val uopIdx = UopIdx() 105 val uopSplitType = UopSplitType() 106 val isVset = Bool() 107 val firstUop = Bool() 108 val lastUop = Bool() 109 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 110 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 111 val commitType = CommitType() // Todo: remove it 112 val needFrm = new NeedFrmBundle 113 114 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 115 116 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 117 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 118 119 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 120 val decoder: Seq[UInt] = ListLookup( 121 inst, XDecode.decodeDefault.map(bitPatToUInt), 122 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 123 ) 124 allSignals zip decoder foreach { case (s, d) => s := d } 125 debug_fuType.foreach(_ := fuType) 126 this 127 } 128 129 def isSoftPrefetch: Bool = { 130 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 131 } 132 133 def connectStaticInst(source: StaticInst): Unit = { 134 for ((name, data) <- this.elements) { 135 if (source.elements.contains(name)) { 136 data := source.elements(name) 137 } 138 } 139 } 140 } 141 142 // DecodedInst --[Rename]--> DynInst 143 class DynInst(implicit p: Parameters) extends XSBundle { 144 def numSrc = backendParams.numSrc 145 // passed from StaticInst 146 val instr = UInt(32.W) 147 val pc = UInt(VAddrBits.W) 148 val foldpc = UInt(MemPredPCWidth.W) 149 val exceptionVec = ExceptionVec() 150 val hasException = Bool() 151 val trigger = new TriggerCf 152 val preDecodeInfo = new PreDecodeInfo 153 val pred_taken = Bool() 154 val crossPageIPFFix = Bool() 155 val ftqPtr = new FtqPtr 156 val ftqOffset = UInt(log2Up(PredictWidth).W) 157 // passed from DecodedInst 158 val srcType = Vec(numSrc, SrcType()) 159 val ldest = UInt(LogicRegsWidth.W) 160 val fuType = FuType() 161 val fuOpType = FuOpType() 162 val rfWen = Bool() 163 val fpWen = Bool() 164 val vecWen = Bool() 165 val v0Wen = Bool() 166 val vlWen = Bool() 167 val isXSTrap = Bool() 168 val waitForward = Bool() // no speculate execution 169 val blockBackward = Bool() 170 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 171 val canRobCompress = Bool() 172 val selImm = SelImm() 173 val imm = UInt(32.W) 174 val fpu = new FPUCtrlSignals 175 val vpu = new VPUCtrlSignals 176 val vlsInstr = Bool() 177 val wfflags = Bool() 178 val isMove = Bool() 179 val uopIdx = UopIdx() 180 val isVset = Bool() 181 val firstUop = Bool() 182 val lastUop = Bool() 183 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 184 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 185 val commitType = CommitType() 186 // rename 187 val srcState = Vec(numSrc, SrcState()) 188 val srcLoadDependency = Vec(numSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 189 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 190 val pdest = UInt(PhyRegIdxWidth.W) 191 // reg cache 192 val useRegCache = Vec(backendParams.numIntRegSrc, Bool()) 193 val regCacheIdx = Vec(backendParams.numIntRegSrc, UInt(RegCacheIdxWidth.W)) 194 val robIdx = new RobPtr 195 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 196 val dirtyFs = Bool() 197 val dirtyVs = Bool() 198 199 val eliminatedMove = Bool() 200 // Take snapshot at this CFI inst 201 val snapshot = Bool() 202 val debugInfo = new PerfDebugInfo 203 val storeSetHit = Bool() // inst has been allocated an store set 204 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 205 // Load wait is needed 206 // load inst will not be executed until former store (predicted by mdp) addr calcuated 207 val loadWaitBit = Bool() 208 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 209 // load inst will not be executed until ALL former store addr calcuated 210 val loadWaitStrict = Bool() 211 val ssid = UInt(SSIDWidth.W) 212 // Todo 213 val lqIdx = new LqPtr 214 val sqIdx = new SqPtr 215 // debug module 216 val singleStep = Bool() 217 // schedule 218 val replayInst = Bool() 219 220 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 221 222 val numLsElem = NumLsElem() 223 224 def getDebugFuType: UInt = debug_fuType.getOrElse(fuType) 225 226 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 227 def isLUI32: Bool = this.selImm === SelImm.IMM_LUI32 228 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 229 230 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 231 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 232 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 233 def isNotSvinval = !FuType.isFence(fuType) 234 235 def isHls: Bool = { 236 fuType === FuType.ldu.U && LSUOpType.isHlv(fuOpType) || fuType === FuType.stu.U && LSUOpType.isHsv(fuOpType) 237 } 238 239 def srcIsReady: Vec[Bool] = { 240 VecInit(this.srcType.zip(this.srcState).map { 241 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 242 }) 243 } 244 245 def clearExceptions( 246 exceptionBits: Seq[Int] = Seq(), 247 flushPipe : Boolean = false, 248 replayInst : Boolean = false 249 ): DynInst = { 250 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 251 if (!flushPipe) { this.flushPipe := false.B } 252 if (!replayInst) { this.replayInst := false.B } 253 this 254 } 255 256 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen || v0Wen || vlWen 257 } 258 259 trait BundleSource { 260 var wakeupSource = "undefined" 261 var idx = 0 262 } 263 264 /** 265 * 266 * @param pregIdxWidth index width of preg 267 * @param exuIndices exu indices of wakeup bundle 268 */ 269 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int])(implicit p: Parameters) extends XSBundle { 270 val rfWen = Bool() 271 val fpWen = Bool() 272 val vecWen = Bool() 273 val v0Wen = Bool() 274 val vlWen = Bool() 275 val pdest = UInt(pregIdxWidth.W) 276 277 /** 278 * @param successor Seq[(psrc, srcType)] 279 * @return Seq[if wakeup psrc] 280 */ 281 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 282 successor.map { case (thatPsrc, srcType) => 283 val pdestMatch = pdest === thatPsrc 284 pdestMatch && ( 285 SrcType.isFp(srcType) && this.fpWen || 286 SrcType.isXp(srcType) && this.rfWen || 287 SrcType.isVp(srcType) && this.vecWen 288 ) && valid 289 } 290 } 291 def wakeUpV0(successor: (UInt, UInt), valid: Bool): Bool = { 292 val (thatPsrc, srcType) = successor 293 val pdestMatch = pdest === thatPsrc 294 pdestMatch && ( 295 SrcType.isV0(srcType) && this.v0Wen 296 ) && valid 297 } 298 def wakeUpVl(successor: (UInt, UInt), valid: Bool): Bool = { 299 val (thatPsrc, srcType) = successor 300 val pdestMatch = pdest === thatPsrc 301 pdestMatch && ( 302 SrcType.isVp(srcType) && this.vlWen 303 ) && valid 304 } 305 def wakeUpFromIQ(successor: Seq[(UInt, UInt)]): Seq[Bool] = { 306 successor.map { case (thatPsrc, srcType) => 307 val pdestMatch = pdest === thatPsrc 308 pdestMatch && ( 309 SrcType.isFp(srcType) && this.fpWen || 310 SrcType.isXp(srcType) && this.rfWen || 311 SrcType.isVp(srcType) && this.vecWen 312 ) 313 } 314 } 315 def wakeUpV0FromIQ(successor: (UInt, UInt)): Bool = { 316 val (thatPsrc, srcType) = successor 317 val pdestMatch = pdest === thatPsrc 318 pdestMatch && ( 319 SrcType.isV0(srcType) && this.v0Wen 320 ) 321 } 322 def wakeUpVlFromIQ(successor: (UInt, UInt)): Bool = { 323 val (thatPsrc, srcType) = successor 324 val pdestMatch = pdest === thatPsrc 325 pdestMatch && ( 326 SrcType.isVp(srcType) && this.vlWen 327 ) 328 } 329 330 def hasOnlyOneSource: Boolean = exuIndices.size == 1 331 332 def hasMultiSources: Boolean = exuIndices.size > 1 333 334 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 335 336 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 337 338 def exuIdx: Int = { 339 require(hasOnlyOneSource) 340 this.exuIndices.head 341 } 342 } 343 344 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams)(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 345 346 } 347 348 class IssueQueueIQWakeUpBundle( 349 exuIdx: Int, 350 backendParams: BackendParams, 351 copyWakeupOut: Boolean = false, 352 copyNum: Int = 0 353 )(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 354 val loadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 355 val is0Lat = Bool() 356 val params = backendParams.allExuParams.filter(_.exuIdx == exuIdx).head 357 val rcDest = OptionWrapper(params.needWriteRegCache, UInt(RegCacheIdxWidth.W)) 358 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 359 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 360 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 361 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 362 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 363 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 364 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 365 366 def fromExuInput(exuInput: ExuInput): Unit = { 367 this.rfWen := exuInput.rfWen.getOrElse(false.B) 368 this.fpWen := exuInput.fpWen.getOrElse(false.B) 369 this.vecWen := exuInput.vecWen.getOrElse(false.B) 370 this.v0Wen := exuInput.v0Wen.getOrElse(false.B) 371 this.vlWen := exuInput.vlWen.getOrElse(false.B) 372 this.pdest := exuInput.pdest 373 } 374 } 375 376 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 377 // vtype 378 val vill = Bool() 379 val vma = Bool() // 1: agnostic, 0: undisturbed 380 val vta = Bool() // 1: agnostic, 0: undisturbed 381 val vsew = VSew() 382 val vlmul = VLmul() // 1/8~8 --> -3~3 383 384 // spec vtype 385 val specVill = Bool() 386 val specVma = Bool() // 1: agnostic, 0: undisturbed 387 val specVta = Bool() // 1: agnostic, 0: undisturbed 388 val specVsew = VSew() 389 val specVlmul = VLmul() // 1/8~8 --> -3~3 390 391 val vm = Bool() // 0: need v0.t 392 val vstart = Vl() 393 394 // float rounding mode 395 val frm = Frm() 396 // scalar float instr and vector float reduction 397 val fpu = Fpu() 398 // vector fix int rounding mode 399 val vxrm = Vxrm() 400 // vector uop index, exclude other non-vector uop 401 val vuopIdx = UopIdx() 402 val lastUop = Bool() 403 // maybe used if data dependancy 404 val vmask = UInt(V0Data().dataWidth.W) 405 val vl = Vl() 406 407 // vector load/store 408 val nf = Nf() 409 val veew = VEew() 410 411 val isReverse = Bool() // vrsub, vrdiv 412 val isExt = Bool() 413 val isNarrow = Bool() 414 val isDstMask = Bool() // vvm, vvvm, mmm 415 val isOpMask = Bool() // vmand, vmnand 416 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 417 418 val isDependOldvd = Bool() // some instruction's computation depends on oldvd 419 val isWritePartVd = Bool() // some instruction's computation writes part of vd, such as vredsum 420 421 def vtype: VType = { 422 val res = Wire(VType()) 423 res.illegal := this.vill 424 res.vma := this.vma 425 res.vta := this.vta 426 res.vsew := this.vsew 427 res.vlmul := this.vlmul 428 res 429 } 430 431 def specVType: VType = { 432 val res = Wire(VType()) 433 res.illegal := this.specVill 434 res.vma := this.specVma 435 res.vta := this.specVta 436 res.vsew := this.specVsew 437 res.vlmul := this.specVlmul 438 res 439 } 440 441 def vconfig: VConfig = { 442 val res = Wire(VConfig()) 443 res.vtype := this.vtype 444 res.vl := this.vl 445 res 446 } 447 448 def connectVType(source: VType): Unit = { 449 this.vill := source.illegal 450 this.vma := source.vma 451 this.vta := source.vta 452 this.vsew := source.vsew 453 this.vlmul := source.vlmul 454 } 455 } 456 457 class NeedFrmBundle(implicit p: Parameters) extends XSBundle { 458 val scalaNeedFrm = Bool() 459 val vectorNeedFrm = Bool() 460 } 461 462 // DynInst --[IssueQueue]--> DataPath 463 class IssueQueueIssueBundle( 464 iqParams: IssueBlockParams, 465 val exuParams: ExeUnitParams, 466 )(implicit 467 p: Parameters 468 ) extends XSBundle { 469 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 470 471 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 472 rfReadDataCfgSet.map((set: Set[DataConfig]) => 473 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 474 ) 475 )) 476 477 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 478 val rcIdx = OptionWrapper(exuParams.needReadRegCache, Vec(exuParams.numRegSrc, UInt(RegCacheIdxWidth.W))) // used to select regcache data 479 val immType = SelImm() // used to select imm extractor 480 val common = new ExuInput(exuParams) 481 val addrOH = UInt(iqParams.numEntries.W) 482 483 def exuIdx = exuParams.exuIdx 484 def getSource: SchedulerType = exuParams.getWBSource 485 486 def getRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 487 rf.zip(srcType).map { 488 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 489 makeValid(issueValid, rfRd.head) 490 }.toSeq 491 } 492 } 493 494 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 495 val issueQueueParams = this.params 496 val og0resp = Valid(new EntryDeqRespBundle) 497 val og1resp = Valid(new EntryDeqRespBundle) 498 } 499 500 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 501 private val intCertainLat = params.intLatencyCertain 502 private val fpCertainLat = params.fpLatencyCertain 503 private val vfCertainLat = params.vfLatencyCertain 504 private val v0CertainLat = params.v0LatencyCertain 505 private val vlCertainLat = params.vlLatencyCertain 506 private val intLat = params.intLatencyValMax 507 private val fpLat = params.fpLatencyValMax 508 private val vfLat = params.vfLatencyValMax 509 private val v0Lat = params.v0LatencyValMax 510 private val vlLat = params.vlLatencyValMax 511 512 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 513 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 514 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 515 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 516 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 517 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 518 val fpDeqRespSet = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 519 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 520 val v0DeqRespSet = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 521 val vlDeqRespSet = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 522 } 523 524 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 525 private val intCertainLat = params.intLatencyCertain 526 private val fpCertainLat = params.fpLatencyCertain 527 private val vfCertainLat = params.vfLatencyCertain 528 private val v0CertainLat = params.v0LatencyCertain 529 private val vlCertainLat = params.vlLatencyCertain 530 private val intLat = params.intLatencyValMax 531 private val fpLat = params.fpLatencyValMax 532 private val vfLat = params.vfLatencyValMax 533 private val v0Lat = params.v0LatencyValMax 534 private val vlLat = params.vlLatencyValMax 535 536 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 537 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 538 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 539 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 540 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 541 } 542 543 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 544 private val intCertainLat = params.intLatencyCertain 545 private val fpCertainLat = params.fpLatencyCertain 546 private val vfCertainLat = params.vfLatencyCertain 547 private val v0CertainLat = params.v0LatencyCertain 548 private val vlCertainLat = params.vlLatencyCertain 549 550 val intConflict = OptionWrapper(intCertainLat, Bool()) 551 val fpConflict = OptionWrapper(fpCertainLat, Bool()) 552 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 553 val v0Conflict = OptionWrapper(v0CertainLat, Bool()) 554 val vlConflict = OptionWrapper(vlCertainLat, Bool()) 555 } 556 557 class ImmInfo extends Bundle { 558 val imm = UInt(32.W) 559 val immType = SelImm() 560 } 561 562 // DataPath --[ExuInput]--> Exu 563 class ExuInput(val params: ExeUnitParams, copyWakeupOut:Boolean = false, copyNum:Int = 0)(implicit p: Parameters) extends XSBundle { 564 val fuType = FuType() 565 val fuOpType = FuOpType() 566 val src = Vec(params.numRegSrc, UInt(params.srcDataBitsMax.W)) 567 val imm = UInt(32.W) 568 val robIdx = new RobPtr 569 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 570 val isFirstIssue = Bool() // Only used by store yet 571 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 572 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 573 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 574 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 575 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 576 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 577 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 578 val pdest = UInt(params.wbPregIdxWidth.W) 579 val rfWen = if (params.needIntWen) Some(Bool()) else None 580 val fpWen = if (params.needFpWen) Some(Bool()) else None 581 val vecWen = if (params.needVecWen) Some(Bool()) else None 582 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 583 val vlWen = if (params.needVlWen) Some(Bool()) else None 584 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 585 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 586 val flushPipe = if (params.flushPipe) Some(Bool()) else None 587 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 588 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 589 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 590 Some(new FtqPtr) else None 591 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 592 Some(UInt(log2Up(PredictWidth).W)) else None 593 val predictInfo = if (params.needPdInfo) Some(new Bundle { 594 val target = UInt(VAddrData().dataWidth.W) 595 val taken = Bool() 596 }) else None 597 val loadWaitBit = OptionWrapper(params.hasLoadExu, Bool()) 598 val waitForRobIdx = OptionWrapper(params.hasLoadExu, new RobPtr) // store set predicted previous store robIdx 599 val storeSetHit = OptionWrapper(params.hasLoadExu, Bool()) // inst has been allocated an store set 600 val loadWaitStrict = OptionWrapper(params.hasLoadExu, Bool()) // load inst will not be executed until ALL former store addr calcuated 601 val ssid = OptionWrapper(params.hasLoadExu, UInt(SSIDWidth.W)) 602 // only vector load store need 603 val numLsElem = OptionWrapper(params.hasVecLsFu, NumLsElem()) 604 605 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 606 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 607 val dataSources = Vec(params.numRegSrc, DataSource()) 608 val l1ExuOH = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuVec())) 609 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 610 val loadDependency = OptionWrapper(params.needLoadDependency, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 611 612 val perfDebugInfo = new PerfDebugInfo() 613 614 def exuIdx = this.params.exuIdx 615 616 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = { 617 if (params.isIQWakeUpSink) { 618 require( 619 og0CancelOH.getWidth == l1ExuOH.get.head.getWidth, 620 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}" 621 ) 622 val l1Cancel: Bool = l1ExuOH.get.zip(srcTimer.get).map { 623 case(exuOH: Vec[Bool], srcTimer: UInt) => 624 (exuOH.asUInt & og0CancelOH).orR && srcTimer === 1.U 625 }.reduce(_ | _) 626 l1Cancel 627 } else { 628 false.B 629 } 630 } 631 632 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 633 // src is assigned to rfReadData 634 this.fuType := source.common.fuType 635 this.fuOpType := source.common.fuOpType 636 this.imm := source.common.imm 637 this.robIdx := source.common.robIdx 638 this.pdest := source.common.pdest 639 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 640 this.iqIdx := source.common.iqIdx // Only used by mem feedback 641 this.dataSources := source.common.dataSources 642 this.l1ExuOH .foreach(_ := source.common.l1ExuOH.get) 643 this.rfWen .foreach(_ := source.common.rfWen.get) 644 this.fpWen .foreach(_ := source.common.fpWen.get) 645 this.vecWen .foreach(_ := source.common.vecWen.get) 646 this.v0Wen .foreach(_ := source.common.v0Wen.get) 647 this.vlWen .foreach(_ := source.common.vlWen.get) 648 this.fpu .foreach(_ := source.common.fpu.get) 649 this.vpu .foreach(_ := source.common.vpu.get) 650 this.flushPipe .foreach(_ := source.common.flushPipe.get) 651 this.pc .foreach(_ := source.common.pc.get) 652 this.preDecode .foreach(_ := source.common.preDecode.get) 653 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 654 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 655 this.predictInfo .foreach(_ := source.common.predictInfo.get) 656 this.loadWaitBit .foreach(_ := source.common.loadWaitBit.get) 657 this.waitForRobIdx .foreach(_ := source.common.waitForRobIdx.get) 658 this.storeSetHit .foreach(_ := source.common.storeSetHit.get) 659 this.loadWaitStrict.foreach(_ := source.common.loadWaitStrict.get) 660 this.ssid .foreach(_ := source.common.ssid.get) 661 this.lqIdx .foreach(_ := source.common.lqIdx.get) 662 this.sqIdx .foreach(_ := source.common.sqIdx.get) 663 this.numLsElem .foreach(_ := source.common.numLsElem.get) 664 this.srcTimer .foreach(_ := source.common.srcTimer.get) 665 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 666 } 667 } 668 669 // ExuInput --[FuncUnit]--> ExuOutput 670 class ExuOutput( 671 val params: ExeUnitParams, 672 )(implicit 673 val p: Parameters 674 ) extends Bundle with BundleSource with HasXSParameter { 675 val data = Vec(params.wbPathNum, UInt(params.destDataBitsMax.W)) 676 val pdest = UInt(params.wbPregIdxWidth.W) 677 val robIdx = new RobPtr 678 val intWen = if (params.needIntWen) Some(Bool()) else None 679 val fpWen = if (params.needFpWen) Some(Bool()) else None 680 val vecWen = if (params.needVecWen) Some(Bool()) else None 681 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 682 val vlWen = if (params.needVlWen) Some(Bool()) else None 683 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 684 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 685 val wflags = if (params.writeFflags) Some(Bool()) else None 686 val vxsat = if (params.writeVxsat) Some(Bool()) else None 687 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 688 val flushPipe = if (params.flushPipe) Some(Bool()) else None 689 val replay = if (params.replayInst) Some(Bool()) else None 690 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 691 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 692 Some(new SqPtr()) else None 693 val trigger = if (params.trigger) Some(new TriggerCf) else None 694 // uop info 695 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 696 // vldu used only 697 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 698 val vpu = new VPUCtrlSignals 699 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 700 val vdIdx = UInt(3.W) 701 val vdIdxInField = UInt(3.W) 702 val isIndexed = Bool() 703 val isMasked = Bool() 704 }) 705 val debug = new DebugBundle 706 val debugInfo = new PerfDebugInfo 707 } 708 709 // ExuOutput + DynInst --> WriteBackBundle 710 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 711 val rfWen = Bool() 712 val fpWen = Bool() 713 val vecWen = Bool() 714 val v0Wen = Bool() 715 val vlWen = Bool() 716 val pdest = UInt(params.pregIdxWidth(backendParams).W) 717 val data = UInt(params.dataWidth.W) 718 val robIdx = new RobPtr()(p) 719 val flushPipe = Bool() 720 val replayInst = Bool() 721 val redirect = ValidIO(new Redirect) 722 val fflags = UInt(5.W) 723 val vxsat = Bool() 724 val exceptionVec = ExceptionVec() 725 val debug = new DebugBundle 726 val debugInfo = new PerfDebugInfo 727 728 this.wakeupSource = s"WB(${params.toString})" 729 730 def fromExuOutput(source: ExuOutput, wbType: String) = { 731 val typeMap = Map("int" -> 0, "fp" -> 1, "vf" -> 2, "v0" -> 3, "vl" -> 4) 732 this.rfWen := source.intWen.getOrElse(false.B) 733 this.fpWen := source.fpWen.getOrElse(false.B) 734 this.vecWen := source.vecWen.getOrElse(false.B) 735 this.v0Wen := source.v0Wen.getOrElse(false.B) 736 this.vlWen := source.vlWen.getOrElse(false.B) 737 this.pdest := source.pdest 738 this.data := source.data(source.params.wbIndex(typeMap(wbType))) 739 this.robIdx := source.robIdx 740 this.flushPipe := source.flushPipe.getOrElse(false.B) 741 this.replayInst := source.replay.getOrElse(false.B) 742 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 743 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 744 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 745 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 746 this.debug := source.debug 747 this.debugInfo := source.debugInfo 748 } 749 750 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 751 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 752 rfWrite.wen := this.rfWen && fire 753 rfWrite.addr := this.pdest 754 rfWrite.data := this.data 755 rfWrite.intWen := this.rfWen 756 rfWrite.fpWen := false.B 757 rfWrite.vecWen := false.B 758 rfWrite.v0Wen := false.B 759 rfWrite.vlWen := false.B 760 rfWrite 761 } 762 763 def asFpRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 764 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(FpData()).addrWidth))) 765 rfWrite.wen := this.fpWen && fire 766 rfWrite.addr := this.pdest 767 rfWrite.data := this.data 768 rfWrite.intWen := false.B 769 rfWrite.fpWen := this.fpWen 770 rfWrite.vecWen := false.B 771 rfWrite.v0Wen := false.B 772 rfWrite.vlWen := false.B 773 rfWrite 774 } 775 776 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 777 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 778 rfWrite.wen := this.vecWen && fire 779 rfWrite.addr := this.pdest 780 rfWrite.data := this.data 781 rfWrite.intWen := false.B 782 rfWrite.fpWen := false.B 783 rfWrite.vecWen := this.vecWen 784 rfWrite.v0Wen := false.B 785 rfWrite.vlWen := false.B 786 rfWrite 787 } 788 789 def asV0RfWriteBundle(fire: Bool): RfWritePortWithConfig = { 790 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(V0Data()).addrWidth))) 791 rfWrite.wen := this.v0Wen && fire 792 rfWrite.addr := this.pdest 793 rfWrite.data := this.data 794 rfWrite.intWen := false.B 795 rfWrite.fpWen := false.B 796 rfWrite.vecWen := false.B 797 rfWrite.v0Wen := this.v0Wen 798 rfWrite.vlWen := false.B 799 rfWrite 800 } 801 802 def asVlRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 803 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VlData()).addrWidth))) 804 rfWrite.wen := this.vlWen && fire 805 rfWrite.addr := this.pdest 806 rfWrite.data := this.data 807 rfWrite.intWen := false.B 808 rfWrite.fpWen := false.B 809 rfWrite.vecWen := false.B 810 rfWrite.v0Wen := false.B 811 rfWrite.vlWen := this.vlWen 812 rfWrite 813 } 814 } 815 816 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 817 // / 818 // [IssueQueue]--> ExuInput -- 819 class ExuBypassBundle( 820 val params: ExeUnitParams, 821 )(implicit p: Parameters) extends XSBundle { 822 val intWen = Bool() 823 val data = UInt(params.destDataBitsMax.W) 824 val pdest = UInt(params.wbPregIdxWidth.W) 825 } 826 827 class ExceptionInfo(implicit p: Parameters) extends XSBundle { 828 val pc = UInt(VAddrData().dataWidth.W) 829 val instr = UInt(32.W) 830 val commitType = CommitType() 831 val exceptionVec = ExceptionVec() 832 val gpaddr = UInt(GPAddrBits.W) 833 val singleStep = Bool() 834 val crossPageIPFFix = Bool() 835 val isInterrupt = Bool() 836 val isHls = Bool() 837 val vls = Bool() 838 val trigger = new TriggerCf 839 } 840 841 object UopIdx { 842 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 843 } 844 845 object FuLatency { 846 def apply(): UInt = UInt(width.W) 847 848 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 849 } 850 851 object ExuOH { 852 def apply(exuNum: Int): UInt = UInt(exuNum.W) 853 854 def apply()(implicit p: Parameters): UInt = UInt(width.W) 855 856 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 857 } 858 859 object ExuVec { 860 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 861 862 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 863 864 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 865 } 866 867 class CancelSignal(implicit p: Parameters) extends XSBundle { 868 val rfWen = Bool() 869 val fpWen = Bool() 870 val vecWen = Bool() 871 val v0Wen = Bool() 872 val vlWen = Bool() 873 val pdest = UInt(PhyRegIdxWidth.W) 874 } 875 876 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 877 val uop = new DynInst 878 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 879 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 880 val isFirstIssue = Bool() 881 val flowNum = OptionWrapper(isVector, NumLsElem()) 882 883 def src_rs1 = src(0) 884 def src_stride = src(1) 885 def src_vs3 = src(2) 886 def src_mask = if (isVector) src(3) else 0.U 887 def src_vl = if (isVector) src(4) else 0.U 888 } 889 890 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 891 val uop = new DynInst 892 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 893 val mask = if (isVector) Some(UInt(VLEN.W)) else None 894 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 895 val vdIdxInField = if (isVector) Some(UInt(3.W)) else None 896 val debug = new DebugBundle 897 898 def isVls = FuType.isVls(uop.fuType) 899 } 900 901 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 902 val uop = new DynInst 903 val flag = UInt(1.W) 904 } 905 906 object LoadShouldCancel { 907 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 908 val ld1Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld1Cancel)).map { case (dep, cancel) => cancel && dep(0)}.reduce(_ || _)) 909 val ld2Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld2Cancel)).map { case (dep, cancel) => cancel && dep(1)}.reduce(_ || _)) 910 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 911 } 912 } 913} 914