1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15* 16* 17* Acknowledgement 18* 19* This implementation is inspired by several key papers: 20* [1] Robert. M. Tomasulo. "[An efficient algorithm for exploiting multiple arithmetic units.] 21* (https://doi.org/10.1147/rd.111.0025)" IBM Journal of Research and Development (IBMJ) 11.1: 25-33. 1967. 22***************************************************************************************/ 23 24package xiangshan.backend 25 26import org.chipsalliance.cde.config.Parameters 27import chisel3._ 28import chisel3.util._ 29import device.MsiInfoBundle 30import difftest._ 31import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 32import system.HasSoCParameter 33import utility._ 34import utility.sram.SramMbistBundle 35import xiangshan._ 36import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 37import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 38import xiangshan.backend.datapath.DataConfig.{IntData, VecData, FpData} 39import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 40import xiangshan.backend.datapath.WbConfig._ 41import xiangshan.backend.datapath.DataConfig._ 42import xiangshan.backend.datapath._ 43import xiangshan.backend.dispatch.CoreDispatchTopDownIO 44import xiangshan.backend.exu.ExuBlock 45import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 46import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PerfCounterIO} 47import xiangshan.backend.fu.NewCSR.PFEvent 48import xiangshan.backend.issue.EntryBundles._ 49import xiangshan.backend.issue.{Scheduler, SchedulerArithImp, SchedulerImpBase, SchedulerMemImp} 50import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 51import xiangshan.backend.trace.TraceCoreInterface 52import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 53import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 54 55import scala.collection.mutable 56 57class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 58 with HasXSParameter { 59 override def shouldBeInlined: Boolean = false 60 val inner = LazyModule(new BackendInlined(params)) 61 lazy val module = new BackendImp(this) 62} 63 64class BackendImp(wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) { 65 val io = IO(new BackendIO()(p, wrapper.params)) 66 io <> wrapper.inner.module.io 67 if (p(DebugOptionsKey).ResetGen) { 68 ResetGen(ResetGenNode(Seq(ModuleNode(wrapper.inner.module))), reset, sim = false, io.sramTest.mbistReset) 69 } 70} 71 72class BackendInlined(val params: BackendParams)(implicit p: Parameters) extends LazyModule 73 with HasXSParameter { 74 75 override def shouldBeInlined: Boolean = true 76 77 // check read & write port config 78 params.configChecks 79 80 /* Only update the idx in mem-scheduler here 81 * Idx in other schedulers can be updated the same way if needed 82 * 83 * Also note that we filter out the 'stData issue-queues' when counting 84 */ 85 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 86 ibp.updateIdx(idx) 87 } 88 89 println(params.iqWakeUpParams) 90 91 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 92 schdCfg.bindBackendParam(params) 93 } 94 95 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 96 iqCfg.bindBackendParam(params) 97 } 98 99 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 100 exuCfg.bindBackendParam(params) 101 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 102 exuCfg.updateExuIdx(i) 103 } 104 105 println("[Backend] ExuConfigs:") 106 for (exuCfg <- params.allExuParams) { 107 val fuConfigs = exuCfg.fuConfigs 108 val wbPortConfigs = exuCfg.wbPortConfigs 109 val immType = exuCfg.immType 110 111 println("[Backend] " + 112 s"${exuCfg.name}: " + 113 (if (exuCfg.fakeUnit) "fake, " else "") + 114 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 115 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 116 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 117 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 118 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 119 s"srcReg(${exuCfg.numRegSrc})" 120 ) 121 require( 122 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 123 fuConfigs.map(_.writeIntRf).reduce(_ || _), 124 s"${exuCfg.name} int wb port has no priority" 125 ) 126 require( 127 wbPortConfigs.collectFirst { case x: FpWB => x }.nonEmpty == 128 fuConfigs.map(x => x.writeFpRf).reduce(_ || _), 129 s"${exuCfg.name} fp wb port has no priority" 130 ) 131 require( 132 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 133 fuConfigs.map(x => x.writeVecRf).reduce(_ || _), 134 s"${exuCfg.name} vec wb port has no priority" 135 ) 136 } 137 138 println(s"[Backend] all fu configs") 139 for (cfg <- FuConfig.allConfigs) { 140 println(s"[Backend] $cfg") 141 } 142 143 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 144 for ((port, seq) <- params.getRdPortParams(IntData())) { 145 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 146 } 147 148 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 149 for ((port, seq) <- params.getWbPortParams(IntData())) { 150 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 151 } 152 153 println(s"[Backend] Fp RdConfigs: ExuName(Priority)") 154 for ((port, seq) <- params.getRdPortParams(FpData())) { 155 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 156 } 157 158 println(s"[Backend] Fp WbConfigs: ExuName(Priority)") 159 for ((port, seq) <- params.getWbPortParams(FpData())) { 160 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 161 } 162 163 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 164 for ((port, seq) <- params.getRdPortParams(VecData())) { 165 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 166 } 167 168 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 169 for ((port, seq) <- params.getWbPortParams(VecData())) { 170 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 171 } 172 173 println(s"[Backend] Dispatch Configs:") 174 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 175 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 176 177 params.updateCopyPdestInfo 178 println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}") 179 params.allExuParams.map(_.copyNum) 180 val ctrlBlock = LazyModule(new CtrlBlock(params)) 181 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 182 val fpScheduler = params.fpSchdParams.map(x => LazyModule(new Scheduler(x))) 183 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 184 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 185 val dataPath = LazyModule(new DataPath(params)) 186 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 187 val fpExuBlock = params.fpSchdParams.map(x => LazyModule(new ExuBlock(x))) 188 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 189 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 190 191 lazy val module = new BackendInlinedImp(this) 192} 193 194class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parameters) extends LazyModuleImp(wrapper) 195 with HasXSParameter 196 with HasPerfEvents 197 with HasCriticalErrors { 198 implicit private val params: BackendParams = wrapper.params 199 200 val io = IO(new BackendIO()(p, wrapper.params)) 201 202 private val ctrlBlock = wrapper.ctrlBlock.module 203 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 204 private val fpScheduler = wrapper.fpScheduler.get.module 205 private val vfScheduler = wrapper.vfScheduler.get.module 206 private val memScheduler = wrapper.memScheduler.get.module 207 private val dataPath = wrapper.dataPath.module 208 private val intExuBlock = wrapper.intExuBlock.get.module 209 private val fpExuBlock = wrapper.fpExuBlock.get.module 210 private val vfExuBlock = wrapper.vfExuBlock.get.module 211 private val og2ForVector = Module(new Og2ForVector(params)) 212 private val bypassNetwork = Module(new BypassNetwork) 213 private val wbDataPath = Module(new WbDataPath(params)) 214 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 215 private val vecExcpMod = Module(new VecExcpDataMergeModule) 216 217 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 218 intScheduler.io.toSchedulers.wakeupVec ++ 219 fpScheduler.io.toSchedulers.wakeupVec ++ 220 vfScheduler.io.toSchedulers.wakeupVec ++ 221 memScheduler.io.toSchedulers.wakeupVec 222 ).map(x => (x.bits.exuIdx, x)).toMap 223 224 private val iqWakeUpMappedBundleDelayed: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 225 intScheduler.io.toSchedulers.wakeupVec ++ 226 fpScheduler.io.toSchedulers.wakeupVec ++ 227 vfScheduler.io.toSchedulers.wakeupVec ++ 228 memScheduler.io.toSchedulers.wakeupVec 229 ).map{ case x => 230 val delayed = Wire(chiselTypeOf(x)) 231 // TODO: add clock gate use Wen, remove issuequeue wakeupToIQ logic Wen = Wen && valid 232 delayed := RegNext(x) 233 (x.bits.exuIdx, delayed) 234 }.toMap 235 236 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 237 238 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 239 wbFuBusyTable.io.in.fpSchdBusyTable := fpScheduler.io.wbFuBusyTable 240 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 241 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 242 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 243 fpScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.fpRespRead 244 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 245 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 246 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 247 248 private val og1Cancel = dataPath.io.og1Cancel 249 private val og0Cancel = dataPath.io.og0Cancel 250 private val vlFromIntIsZero = intExuBlock.io.vlIsZero.get 251 private val vlFromIntIsVlmax = intExuBlock.io.vlIsVlmax.get 252 private val vlFromVfIsZero = vfExuBlock.io.vlIsZero.get 253 private val vlFromVfIsVlmax = vfExuBlock.io.vlIsVlmax.get 254 255 private val backendCriticalError = Wire(Bool()) 256 257 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 258 ctrlBlock.io.frontend <> io.frontend 259 ctrlBlock.io.fromCSR.toDecode := intExuBlock.io.csrToDecode.get 260 ctrlBlock.io.fromCSR.traceCSR := intExuBlock.io.csrio.get.traceCSR 261 ctrlBlock.io.fromCSR.instrAddrTransType := RegNext(intExuBlock.io.csrio.get.instrAddrTransType) 262 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 263 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 264 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 265 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 266 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 267 268 io.mem.lsqEnqIO <> ctrlBlock.io.toMem.lsqEnqIO 269 ctrlBlock.io.fromMemToDispatch.scommit := io.mem.sqDeq 270 ctrlBlock.io.fromMemToDispatch.lcommit := io.mem.lqDeq 271 ctrlBlock.io.fromMemToDispatch.sqDeqPtr := io.mem.sqDeqPtr 272 ctrlBlock.io.fromMemToDispatch.lqDeqPtr := io.mem.lqDeqPtr 273 ctrlBlock.io.fromMemToDispatch.sqCancelCnt := io.mem.sqCancelCnt 274 ctrlBlock.io.fromMemToDispatch.lqCancelCnt := io.mem.lqCancelCnt 275 ctrlBlock.io.toDispatch.wakeUpInt := intScheduler.io.toSchedulers.wakeupVec 276 ctrlBlock.io.toDispatch.wakeUpFp := fpScheduler.io.toSchedulers.wakeupVec 277 ctrlBlock.io.toDispatch.wakeUpVec := vfScheduler.io.toSchedulers.wakeupVec 278 ctrlBlock.io.toDispatch.wakeUpMem := memScheduler.io.toSchedulers.wakeupVec 279 ctrlBlock.io.toDispatch.IQValidNumVec := intScheduler.io.IQValidNumVec ++ fpScheduler.io.IQValidNumVec ++ vfScheduler.io.IQValidNumVec ++ memScheduler.io.IQValidNumVec 280 ctrlBlock.io.toDispatch.ldCancel := io.mem.ldCancel 281 ctrlBlock.io.toDispatch.og0Cancel := og0Cancel 282 ctrlBlock.io.toDispatch.wbPregsInt.zip(wbDataPath.io.toIntPreg).map(x => { 283 x._1.valid := x._2.wen && x._2.intWen 284 x._1.bits := x._2.addr 285 }) 286 ctrlBlock.io.toDispatch.wbPregsFp.zip(wbDataPath.io.toFpPreg).map(x => { 287 x._1.valid := x._2.wen && x._2.fpWen 288 x._1.bits := x._2.addr 289 }) 290 ctrlBlock.io.toDispatch.wbPregsVec.zip(wbDataPath.io.toVfPreg).map(x => { 291 x._1.valid := x._2.wen && x._2.vecWen 292 x._1.bits := x._2.addr 293 }) 294 ctrlBlock.io.toDispatch.wbPregsV0.zip(wbDataPath.io.toV0Preg).map(x => { 295 x._1.valid := x._2.wen && x._2.v0Wen 296 x._1.bits := x._2.addr 297 }) 298 ctrlBlock.io.toDispatch.wbPregsVl.zip(wbDataPath.io.toVlPreg).map(x => { 299 x._1.valid := x._2.wen && x._2.vlWen 300 x._1.bits := x._2.addr 301 }) 302 ctrlBlock.io.toDispatch.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero 303 ctrlBlock.io.toDispatch.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax 304 ctrlBlock.io.toDispatch.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero 305 ctrlBlock.io.toDispatch.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax 306 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 307 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 308 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 309 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 310 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 311 ctrlBlock.io.robio.csr.criticalErrorState := intExuBlock.io.csrio.get.criticalErrorState 312 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 313 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 314 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 315 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 316 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 317 ctrlBlock.io.debugEnqLsq.req := ctrlBlock.io.toMem.lsqEnqIO.req 318 ctrlBlock.io.debugEnqLsq.needAlloc := ctrlBlock.io.toMem.lsqEnqIO.needAlloc 319 ctrlBlock.io.debugEnqLsq.iqAccept := ctrlBlock.io.toMem.lsqEnqIO.iqAccept 320 ctrlBlock.io.fromVecExcpMod.busy := vecExcpMod.o.status.busy 321 322 val intWriteBackDelayed = Wire(chiselTypeOf(wbDataPath.io.toIntPreg)) 323 intWriteBackDelayed.zip(wbDataPath.io.toIntPreg).map{ case (sink, source) => 324 sink := DontCare 325 sink.wen := RegNext(source.wen) 326 sink.intWen := RegNext(source.intWen) 327 sink.addr := RegEnable(source.addr, source.wen) 328 } 329 val fpWriteBackDelayed = Wire(chiselTypeOf(wbDataPath.io.toFpPreg)) 330 fpWriteBackDelayed.zip(wbDataPath.io.toFpPreg).map { case (sink, source) => 331 sink := DontCare 332 sink.wen := RegNext(source.wen) 333 sink.fpWen := RegNext(source.fpWen) 334 sink.addr := RegEnable(source.addr, source.wen) 335 } 336 val vfWriteBackDelayed = Wire(chiselTypeOf(wbDataPath.io.toVfPreg)) 337 vfWriteBackDelayed.zip(wbDataPath.io.toVfPreg).map { case (sink, source) => 338 sink := DontCare 339 sink.wen := RegNext(source.wen) 340 sink.vecWen := RegNext(source.vecWen) 341 sink.addr := RegEnable(source.addr, source.wen) 342 } 343 val v0WriteBackDelayed = Wire(chiselTypeOf(wbDataPath.io.toV0Preg)) 344 v0WriteBackDelayed.zip(wbDataPath.io.toV0Preg).map { case (sink, source) => 345 sink := DontCare 346 sink.wen := RegNext(source.wen) 347 sink.v0Wen := RegNext(source.v0Wen) 348 sink.addr := RegEnable(source.addr, source.wen) 349 } 350 val vlWriteBackDelayed = Wire(chiselTypeOf(wbDataPath.io.toVlPreg)) 351 vlWriteBackDelayed.zip(wbDataPath.io.toVlPreg).map { case (sink, source) => 352 sink := DontCare 353 sink.wen := RegNext(source.wen) 354 sink.vlWen := RegNext(source.vlWen) 355 sink.addr := RegEnable(source.addr, source.wen) 356 } 357 intScheduler.io.fromTop.hartId := io.fromTop.hartId 358 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 359 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 360 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 361 intScheduler.io.fpWriteBack := 0.U.asTypeOf(intScheduler.io.fpWriteBack) 362 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 363 intScheduler.io.v0WriteBack := 0.U.asTypeOf(intScheduler.io.v0WriteBack) 364 intScheduler.io.vlWriteBack := 0.U.asTypeOf(intScheduler.io.vlWriteBack) 365 intScheduler.io.intWriteBackDelayed := intWriteBackDelayed 366 intScheduler.io.fpWriteBackDelayed := 0.U.asTypeOf(intScheduler.io.fpWriteBackDelayed) 367 intScheduler.io.vfWriteBackDelayed := 0.U.asTypeOf(intScheduler.io.vfWriteBackDelayed) 368 intScheduler.io.v0WriteBackDelayed := 0.U.asTypeOf(intScheduler.io.v0WriteBackDelayed) 369 intScheduler.io.vlWriteBackDelayed := 0.U.asTypeOf(intScheduler.io.vlWriteBackDelayed) 370 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 371 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 372 intScheduler.io.fromSchedulers.wakeupVecDelayed.foreach { wakeup => wakeup := iqWakeUpMappedBundleDelayed(wakeup.bits.exuIdx) } 373 intScheduler.io.fromDataPath.og0Cancel := og0Cancel 374 intScheduler.io.fromDataPath.og1Cancel := og1Cancel 375 intScheduler.io.ldCancel := io.mem.ldCancel 376 intScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.take(params.getIntExuRCWriteSize) 377 intScheduler.io.vlWriteBackInfo.vlFromIntIsZero := false.B 378 intScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := false.B 379 intScheduler.io.vlWriteBackInfo.vlFromVfIsZero := false.B 380 intScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := false.B 381 382 fpScheduler.io.fromTop.hartId := io.fromTop.hartId 383 fpScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 384 fpScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.fpUops 385 fpScheduler.io.intWriteBack := 0.U.asTypeOf(fpScheduler.io.intWriteBack) 386 fpScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 387 fpScheduler.io.vfWriteBack := 0.U.asTypeOf(fpScheduler.io.vfWriteBack) 388 fpScheduler.io.v0WriteBack := 0.U.asTypeOf(fpScheduler.io.v0WriteBack) 389 fpScheduler.io.vlWriteBack := 0.U.asTypeOf(fpScheduler.io.vlWriteBack) 390 fpScheduler.io.intWriteBackDelayed := 0.U.asTypeOf(intWriteBackDelayed) 391 fpScheduler.io.fpWriteBackDelayed := fpWriteBackDelayed 392 fpScheduler.io.vfWriteBackDelayed := 0.U.asTypeOf(intScheduler.io.vfWriteBackDelayed) 393 fpScheduler.io.v0WriteBackDelayed := 0.U.asTypeOf(intScheduler.io.v0WriteBackDelayed) 394 fpScheduler.io.vlWriteBackDelayed := 0.U.asTypeOf(intScheduler.io.vlWriteBackDelayed) 395 fpScheduler.io.fromDataPath.resp := dataPath.io.toFpIQ 396 fpScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 397 fpScheduler.io.fromSchedulers.wakeupVecDelayed.foreach { wakeup => wakeup := iqWakeUpMappedBundleDelayed(wakeup.bits.exuIdx) } 398 fpScheduler.io.fromDataPath.og0Cancel := og0Cancel 399 fpScheduler.io.fromDataPath.og1Cancel := og1Cancel 400 fpScheduler.io.ldCancel := io.mem.ldCancel 401 fpScheduler.io.vlWriteBackInfo.vlFromIntIsZero := false.B 402 fpScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := false.B 403 fpScheduler.io.vlWriteBackInfo.vlFromVfIsZero := false.B 404 fpScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := false.B 405 406 memScheduler.io.fromTop.hartId := io.fromTop.hartId 407 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 408 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 409 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 410 memScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 411 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 412 memScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 413 memScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 414 memScheduler.io.intWriteBackDelayed := intWriteBackDelayed 415 memScheduler.io.fpWriteBackDelayed := fpWriteBackDelayed 416 memScheduler.io.vfWriteBackDelayed := vfWriteBackDelayed 417 memScheduler.io.v0WriteBackDelayed := v0WriteBackDelayed 418 memScheduler.io.vlWriteBackDelayed := vlWriteBackDelayed 419 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 420 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 421 memScheduler.io.fromMem.get.wakeup := io.mem.wakeup 422 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 423 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 424 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 425 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 426 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 427 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 428 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 429 sink.valid := source.valid 430 sink.bits := source.bits.robIdx 431 } 432 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 433 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 434 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 435 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 436 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 437 memScheduler.io.fromMem.get.vstuFeedback := io.mem.vstuIqFeedback 438 memScheduler.io.fromMem.get.vlduFeedback := io.mem.vlduIqFeedback 439 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 440 memScheduler.io.fromSchedulers.wakeupVecDelayed.foreach { wakeup => wakeup := iqWakeUpMappedBundleDelayed(wakeup.bits.exuIdx) } 441 memScheduler.io.fromDataPath.og0Cancel := og0Cancel 442 memScheduler.io.fromDataPath.og1Cancel := og1Cancel 443 memScheduler.io.ldCancel := io.mem.ldCancel 444 memScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.takeRight(params.getMemExuRCWriteSize) 445 memScheduler.io.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero 446 memScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax 447 memScheduler.io.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero 448 memScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax 449 memScheduler.io.fromOg2Resp.get := og2ForVector.io.toMemIQOg2Resp 450 451 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 452 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 453 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 454 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 455 vfScheduler.io.fpWriteBack := 0.U.asTypeOf(vfScheduler.io.fpWriteBack) 456 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 457 vfScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 458 vfScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 459 vfScheduler.io.intWriteBackDelayed := 0.U.asTypeOf(intWriteBackDelayed) 460 vfScheduler.io.fpWriteBackDelayed := 0.U.asTypeOf(fpWriteBackDelayed) 461 vfScheduler.io.vfWriteBackDelayed := vfWriteBackDelayed 462 vfScheduler.io.v0WriteBackDelayed := v0WriteBackDelayed 463 vfScheduler.io.vlWriteBackDelayed := vlWriteBackDelayed 464 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 465 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 466 vfScheduler.io.fromSchedulers.wakeupVecDelayed.foreach { wakeup => wakeup := iqWakeUpMappedBundleDelayed(wakeup.bits.exuIdx) } 467 vfScheduler.io.fromDataPath.og0Cancel := og0Cancel 468 vfScheduler.io.fromDataPath.og1Cancel := og1Cancel 469 vfScheduler.io.ldCancel := io.mem.ldCancel 470 vfScheduler.io.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero 471 vfScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax 472 vfScheduler.io.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero 473 vfScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax 474 vfScheduler.io.fromOg2Resp.get := og2ForVector.io.toVfIQOg2Resp 475 476 dataPath.io.hartId := io.fromTop.hartId 477 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 478 479 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 480 dataPath.io.fromFpIQ <> fpScheduler.io.toDataPathAfterDelay 481 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 482 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 483 484 dataPath.io.ldCancel := io.mem.ldCancel 485 486 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 487 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 488 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 489 dataPath.io.fromFpWb := wbDataPath.io.toFpPreg 490 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 491 dataPath.io.fromV0Wb := wbDataPath.io.toV0Preg 492 dataPath.io.fromVlWb := wbDataPath.io.toVlPreg 493 dataPath.io.diffIntRat.foreach(_ := ctrlBlock.io.diff_int_rat.get) 494 dataPath.io.diffFpRat .foreach(_ := ctrlBlock.io.diff_fp_rat.get) 495 dataPath.io.diffVecRat.foreach(_ := ctrlBlock.io.diff_vec_rat.get) 496 dataPath.io.diffV0Rat .foreach(_ := ctrlBlock.io.diff_v0_rat.get) 497 dataPath.io.diffVlRat .foreach(_ := ctrlBlock.io.diff_vl_rat.get) 498 dataPath.io.fromBypassNetwork := bypassNetwork.io.toDataPath 499 dataPath.io.fromVecExcpMod.r := vecExcpMod.o.toVPRF.r 500 dataPath.io.fromVecExcpMod.w := vecExcpMod.o.toVPRF.w 501 dataPath.io.topDownInfo.lqEmpty := DelayN(io.topDownInfo.lqEmpty, 2) 502 dataPath.io.topDownInfo.sqEmpty := DelayN(io.topDownInfo.sqEmpty, 2) 503 dataPath.io.topDownInfo.l1Miss := RegNext(io.topDownInfo.l1Miss) 504 dataPath.io.topDownInfo.l2TopMiss.l2Miss := io.topDownInfo.l2TopMiss.l2Miss 505 dataPath.io.topDownInfo.l2TopMiss.l3Miss := io.topDownInfo.l2TopMiss.l3Miss 506 507 og2ForVector.io.flush := ctrlBlock.io.toDataPath.flush 508 og2ForVector.io.ldCancel := io.mem.ldCancel 509 og2ForVector.io.fromOg1VfArith <> dataPath.io.toVecExu 510 og2ForVector.io.fromOg1VecMem.zip(dataPath.io.toMemExu.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1)) 511 .foreach { 512 case (og1Mem, datapathMem) => og1Mem <> datapathMem 513 } 514 og2ForVector.io.fromOg1ImmInfo := dataPath.io.og1ImmInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1) 515 516 println(s"[Backend] BypassNetwork OG1 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filterNot(_._2.needOg2Resp).size}") 517 println(s"[Backend] BypassNetwork OG2 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).size}") 518 println(s"[Backend] bypassNetwork.io.fromDataPath.mem: ${bypassNetwork.io.fromDataPath.mem.size}, dataPath.io.toMemExu: ${dataPath.io.toMemExu.size}") 519 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 520 bypassNetwork.io.fromDataPath.fp <> dataPath.io.toFpExu 521 bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfArithExu 522 bypassNetwork.io.fromDataPath.mem.lazyZip(params.memSchdParams.get.issueBlockParams).lazyZip(dataPath.io.toMemExu).filterNot(_._2.needOg2Resp) 523 .map(x => (x._1, x._3)).foreach { 524 case (bypassMem, datapathMem) => bypassMem <> datapathMem 525 } 526 bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1) 527 .zip(og2ForVector.io.toVecMemExu).foreach { 528 case (bypassMem, og2Mem) => bypassMem <> og2Mem 529 } 530 bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo 531 bypassNetwork.io.fromDataPath.immInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1) 532 .zip(og2ForVector.io.toBypassNetworkImmInfo).foreach { 533 case (immInfo, og2ImmInfo) => immInfo := og2ImmInfo 534 } 535 bypassNetwork.io.fromDataPath.rcData := dataPath.io.toBypassNetworkRCData 536 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 537 bypassNetwork.io.fromExus.connectExuOutput(_.fp)(fpExuBlock.io.out) 538 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 539 540 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 541 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 542 s"io.mem.writeback(${io.mem.writeBack.size})" 543 ) 544 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 545 sink.valid := source.valid 546 sink.bits.intWen := source.bits.uop.rfWen && source.bits.isFromLoadUnit 547 sink.bits.pdest := source.bits.uop.pdest 548 sink.bits.data := source.bits.data 549 } 550 551 552 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 553 for (i <- 0 until intExuBlock.io.in.length) { 554 for (j <- 0 until intExuBlock.io.in(i).length) { 555 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 556 NewPipelineConnect( 557 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 558 Mux( 559 bypassNetwork.io.toExus.int(i)(j).fire, 560 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 561 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 562 ), 563 Option("bypassNetwork2intExuBlock") 564 ) 565 } 566 } 567 568 ctrlBlock.io.toDataPath.pcToDataPathIO <> dataPath.io.fromPcTargetMem 569 570 private val csrin = intExuBlock.io.csrin.get 571 csrin.hartId := io.fromTop.hartId 572 csrin.msiInfo.valid := RegNext(io.fromTop.msiInfo.valid) 573 csrin.msiInfo.bits := RegEnable(io.fromTop.msiInfo.bits, io.fromTop.msiInfo.valid) 574 csrin.clintTime.valid := RegNext(io.fromTop.clintTime.valid) 575 csrin.clintTime.bits := RegEnable(io.fromTop.clintTime.bits, io.fromTop.clintTime.valid) 576 csrin.l2FlushDone := RegNext(io.fromTop.l2FlushDone) 577 csrin.trapInstInfo := ctrlBlock.io.toCSR.trapInstInfo 578 csrin.fromVecExcpMod.busy := vecExcpMod.o.status.busy 579 csrin.criticalErrorState := backendCriticalError 580 581 private val csrio = intExuBlock.io.csrio.get 582 csrio.hartId := io.fromTop.hartId 583 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 584 csrio.fpu.isIllegal := false.B // Todo: remove it 585 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 586 csrio.vpu <> WireDefault(0.U.asTypeOf(csrio.vpu)) // Todo 587 588 val fromIntExuVsetVType = intExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 589 val fromVfExuVsetVType = vfExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 590 val fromVsetVType = Mux(fromIntExuVsetVType.valid, fromIntExuVsetVType.bits, fromVfExuVsetVType.bits) 591 val vsetvlVType = RegEnable(fromVsetVType, 0.U.asTypeOf(new VType), fromIntExuVsetVType.valid || fromVfExuVsetVType.valid) 592 ctrlBlock.io.toDecode.vsetvlVType := vsetvlVType 593 594 val commitVType = ctrlBlock.io.robio.commitVType.vtype 595 val hasVsetvl = ctrlBlock.io.robio.commitVType.hasVsetvl 596 val vtype = VType.toVtypeStruct(Mux(hasVsetvl, vsetvlVType, commitVType.bits)).asUInt 597 598 // csr not store the value of vl, so when using difftest we assign the value of vl to debugVl 599 val debugVl_s0 = WireInit(UInt(VlData().dataWidth.W), 0.U) 600 val debugVl_s1 = WireInit(UInt(VlData().dataWidth.W), 0.U) 601 debugVl_s0 := dataPath.io.diffVl.getOrElse(0.U.asTypeOf(UInt(VlData().dataWidth.W))) 602 debugVl_s1 := RegNext(debugVl_s0) 603 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 604 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 605 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 606 ctrlBlock.io.toDecode.vstart := csrio.vpu.vstart 607 //Todo here need change design 608 csrio.vpu.set_vtype.valid := commitVType.valid 609 csrio.vpu.set_vtype.bits := ZeroExt(vtype, XLEN) 610 csrio.vpu.vl := ZeroExt(debugVl_s1, XLEN) 611 csrio.vpu.dirty_vs := ctrlBlock.io.robio.csr.dirty_vs 612 csrio.exception := ctrlBlock.io.robio.exception 613 csrio.robDeqPtr := ctrlBlock.io.robio.robDeqPtr 614 csrio.memExceptionVAddr := io.mem.exceptionAddr.vaddr 615 csrio.memExceptionGPAddr := io.mem.exceptionAddr.gpaddr 616 csrio.memExceptionIsForVSnonLeafPTE := io.mem.exceptionAddr.isForVSnonLeafPTE 617 csrio.externalInterrupt := RegNext(io.fromTop.externalInterrupt) 618 csrio.perf <> io.perf 619 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 620 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 621 private val fenceio = intExuBlock.io.fenceio.get 622 io.fenceio <> fenceio 623 624 // to fpExuBlock 625 fpExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 626 for (i <- 0 until fpExuBlock.io.in.length) { 627 for (j <- 0 until fpExuBlock.io.in(i).length) { 628 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.fp(i)(j).bits.loadDependency, io.mem.ldCancel) 629 NewPipelineConnect( 630 bypassNetwork.io.toExus.fp(i)(j), fpExuBlock.io.in(i)(j), fpExuBlock.io.in(i)(j).fire, 631 Mux( 632 bypassNetwork.io.toExus.fp(i)(j).fire, 633 bypassNetwork.io.toExus.fp(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 634 fpExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 635 ), 636 Option("bypassNetwork2fpExuBlock") 637 ) 638 } 639 } 640 641 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 642 for (i <- 0 until vfExuBlock.io.in.size) { 643 for (j <- 0 until vfExuBlock.io.in(i).size) { 644 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 645 NewPipelineConnect( 646 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 647 Mux( 648 bypassNetwork.io.toExus.vf(i)(j).fire, 649 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 650 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 651 ), 652 Option("bypassNetwork2vfExuBlock") 653 ) 654 655 } 656 } 657 658 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 659 fpExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 660 fpExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 661 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 662 vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 663 664 wbDataPath.io.flush := ctrlBlock.io.redirect 665 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 666 wbDataPath.io.fromIntExu <> intExuBlock.io.out 667 wbDataPath.io.fromFpExu <> fpExuBlock.io.out 668 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 669 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 670 sink.valid := source.valid 671 source.ready := sink.ready 672 sink.bits.data := VecInit(Seq.fill(sink.bits.params.wbPathNum)(source.bits.data)) 673 sink.bits.pdest := source.bits.uop.pdest 674 sink.bits.robIdx := source.bits.uop.robIdx 675 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 676 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 677 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 678 sink.bits.v0Wen.foreach(_ := source.bits.uop.v0Wen) 679 sink.bits.vlWen.foreach(_ := source.bits.uop.vlWen) 680 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 681 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 682 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 683 sink.bits.debug := source.bits.debug 684 sink.bits.debugInfo := source.bits.uop.debugInfo 685 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 686 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 687 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 688 sink.bits.vls.foreach(x => { 689 x.vdIdx := source.bits.vdIdx.get 690 x.vdIdxInField := source.bits.vdIdxInField.get 691 x.vpu := source.bits.uop.vpu 692 x.oldVdPsrc := source.bits.uop.psrc(2) 693 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 694 x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType) 695 x.isStrided := VlduType.isStrided(source.bits.uop.fuOpType) 696 x.isWhole := VlduType.isWhole(source.bits.uop.fuOpType) 697 x.isVecLoad := VlduType.isVecLd(source.bits.uop.fuOpType) 698 x.isVlm := VlduType.isMasked(source.bits.uop.fuOpType) && VlduType.isVecLd(source.bits.uop.fuOpType) 699 }) 700 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 701 } 702 wbDataPath.io.fromCSR.vstart := csrio.vpu.vstart 703 704 vecExcpMod.i.fromExceptionGen := ctrlBlock.io.toVecExcpMod.excpInfo 705 vecExcpMod.i.fromRab.logicPhyRegMap := ctrlBlock.io.toVecExcpMod.logicPhyRegMap 706 vecExcpMod.i.fromRat := ctrlBlock.io.toVecExcpMod.ratOldPest 707 vecExcpMod.i.fromVprf := dataPath.io.toVecExcpMod 708 709 // to mem 710 private val memIssueParams = params.memSchdParams.get.issueBlockParams 711 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 712 private val memExuBlocksHasVecLoad = memIssueParams.map(_.exuBlockParams.map(x => x.hasVLoadFu)) 713 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 714 println(s"[Backend] memExuBlocksHasVecLoad: $memExuBlocksHasVecLoad") 715 716 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 717 for (i <- toMem.indices) { 718 for (j <- toMem(i).indices) { 719 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 720 val needIssueTimeout = memExuBlocksHasLDU(i)(j) || memExuBlocksHasVecLoad(i)(j) 721 val issueTimeout = 722 if (needIssueTimeout) 723 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 724 else 725 false.B 726 727 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 728 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 729 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 730 memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block 731 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 732 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 733 memScheduler.io.loadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 734 memScheduler.io.loadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 735 } 736 737 if (memScheduler.io.vecLoadFinalIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 738 memScheduler.io.vecLoadFinalIssueResp(i)(j).valid := issueTimeout 739 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 740 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.resp := RespType.block 741 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 742 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 743 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 744 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 745 } 746 747 NewPipelineConnect( 748 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 749 Mux( 750 bypassNetwork.io.toExus.mem(i)(j).fire, 751 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 752 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 753 ), 754 Option("bypassNetwork2toMemExus") 755 ) 756 757 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 758 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 759 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 760 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 761 memScheduler.io.memAddrIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 762 memScheduler.io.memAddrIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 763 memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully 764 } 765 766 if (memScheduler.io.vecLoadIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 767 memScheduler.io.vecLoadIssueResp(i)(j) match { 768 case resp => 769 resp.valid := toMem(i)(j).fire && VlduType.isVecLd(toMem(i)(j).bits.fuOpType) 770 resp.bits.fuType := toMem(i)(j).bits.fuType 771 resp.bits.robIdx := toMem(i)(j).bits.robIdx 772 resp.bits.uopIdx.get := toMem(i)(j).bits.vpu.get.vuopIdx 773 resp.bits.sqIdx.get := toMem(i)(j).bits.sqIdx.get 774 resp.bits.lqIdx.get := toMem(i)(j).bits.lqIdx.get 775 resp.bits.resp := RespType.success 776 } 777 if (backendParams.debugEn){ 778 dontTouch(memScheduler.io.vecLoadIssueResp(i)(j)) 779 } 780 } 781 } 782 } 783 784 io.mem.redirect := ctrlBlock.io.redirect 785 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 786 val enableMdp = Constantin.createRecord("EnableMdp", true) 787 sink.valid := source.valid 788 source.ready := sink.ready 789 sink.bits.iqIdx := source.bits.iqIdx 790 sink.bits.isFirstIssue := source.bits.isFirstIssue 791 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 792 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 793 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 794 sink.bits.uop.fuType := source.bits.fuType 795 sink.bits.uop.fuOpType := source.bits.fuOpType 796 sink.bits.uop.imm := source.bits.imm 797 sink.bits.uop.robIdx := source.bits.robIdx 798 sink.bits.uop.pdest := source.bits.pdest 799 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 800 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 801 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 802 sink.bits.uop.v0Wen := source.bits.v0Wen.getOrElse(false.B) 803 sink.bits.uop.vlWen := source.bits.vlWen.getOrElse(false.B) 804 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 805 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) + (source.bits.ftqOffset.getOrElse(0.U) << instOffsetBits) 806 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 807 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 808 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 809 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 810 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 811 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 812 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 813 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 814 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 815 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 816 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 817 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 818 sink.bits.uop.numLsElem := source.bits.numLsElem.getOrElse(0.U) // Todo: remove this bundle, keep only the one below 819 sink.bits.flowNum.foreach(_ := source.bits.numLsElem.get) 820 } 821 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 822 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 823 io.mem.tlbCsr := csrio.tlb 824 io.mem.csrCtrl := csrio.customCtrl 825 io.mem.sfence := fenceio.sfence 826 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 827 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 828 829 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 830 storePcRead := ctrlBlock.io.memStPcRead(i).data 831 ctrlBlock.io.memStPcRead(i).valid := io.mem.issueSta(i).valid 832 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 833 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 834 } 835 836 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 837 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 838 ctrlBlock.io.memHyPcRead(i).valid := io.mem.issueHylda(i).valid 839 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 840 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 841 }) 842 843 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 844 845 // mem io 846 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 847 io.mem.storeDebugInfo <> ctrlBlock.io.robio.storeDebugInfo 848 849 io.frontendSfence := fenceio.sfence 850 io.frontendTlbCsr := csrio.tlb 851 io.frontendCsrCtrl := csrio.customCtrl 852 853 io.tlb <> csrio.tlb 854 855 io.csrCustomCtrl := csrio.customCtrl 856 857 io.toTop.cpuHalted := ctrlBlock.io.toTop.cpuHalt 858 859 io.traceCoreInterface <> ctrlBlock.io.traceCoreInterface 860 861 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 862 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 863 864 io.debugRolling := ctrlBlock.io.debugRolling 865 866 io.topDownInfo.noUopsIssued := RegNext(dataPath.io.topDownInfo.noUopsIssued) 867 868 private val cg = ClockGate.genTeSrc 869 dontTouch(cg) 870 if(hasMbist) { 871 cg.cgen := io.sramTest.mbist.get.cgen 872 } else { 873 cg.cgen := false.B 874 } 875 876 if(backendParams.debugEn) { 877 dontTouch(memScheduler.io) 878 dontTouch(dataPath.io.toMemExu) 879 dontTouch(wbDataPath.io.fromMemExu) 880 } 881 882 // reset tree 883 if (p(DebugOptionsKey).ResetGen) { 884 val rightResetTree = ResetGenNode(Seq( 885 ModuleNode(dataPath), 886 ModuleNode(intExuBlock), 887 ModuleNode(fpExuBlock), 888 ModuleNode(vfExuBlock), 889 ModuleNode(bypassNetwork), 890 ModuleNode(wbDataPath) 891 )) 892 val leftResetTree = ResetGenNode(Seq( 893 ModuleNode(intScheduler), 894 ModuleNode(fpScheduler), 895 ModuleNode(vfScheduler), 896 ModuleNode(memScheduler), 897 ModuleNode(og2ForVector), 898 ModuleNode(wbFuBusyTable), 899 ResetGenNode(Seq( 900 ModuleNode(ctrlBlock), 901 // ResetGenNode(Seq( 902 CellNode(io.frontendReset) 903 // )) 904 )) 905 )) 906 ResetGen(leftResetTree, reset, sim = false, io.sramTest.mbistReset) 907 ResetGen(rightResetTree, reset, sim = false, io.sramTest.mbistReset) 908 } else { 909 io.frontendReset := DontCare 910 } 911 912 // perf events 913 val pfevent = Module(new PFEvent) 914 pfevent.io.distribute_csr := RegNext(csrio.customCtrl.distribute_csr) 915 val csrevents = pfevent.io.hpmevent.slice(8,16) 916 917 val ctrlBlockPerf = ctrlBlock.getPerfEvents 918 val intSchedulerPerf = intScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 919 val fpSchedulerPerf = fpScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 920 val vecSchedulerPerf = vfScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 921 val memSchedulerPerf = memScheduler.asInstanceOf[SchedulerMemImp].getPerfEvents 922 val dataPathPerf = dataPath.getPerfEvents 923 924 val perfBackend = Seq() 925 // let index = 0 be no event 926 val allPerfEvents = Seq(("noEvent", 0.U)) ++ ctrlBlockPerf ++ dataPathPerf ++ 927 intSchedulerPerf ++ fpSchedulerPerf ++ vecSchedulerPerf ++ memSchedulerPerf ++ perfBackend 928 929 930 if (printEventCoding) { 931 for (((name, inc), i) <- allPerfEvents.zipWithIndex) { 932 println("backend perfEvents Set", name, inc, i) 933 } 934 } 935 936 val allPerfInc = allPerfEvents.map(_._2.asTypeOf(new PerfEvent)) 937 val perfEvents = HPerfMonitor(csrevents, allPerfInc).getPerfEvents 938 csrio.perf.perfEventsBackend := VecInit(perfEvents.map(_._2.asTypeOf(new PerfEvent))) 939 940 val ctrlBlockError = ctrlBlock.getCriticalErrors 941 val intExuBlockError = intExuBlock.getCriticalErrors 942 val criticalErrors = ctrlBlockError ++ intExuBlockError 943 944 if (printCriticalError) { 945 for (((name, error), _) <- criticalErrors.zipWithIndex) { 946 XSError(error, s"critical error: $name \n") 947 } 948 } 949 950 // expand to collect frontend/memblock/L2 critical errors 951 backendCriticalError := criticalErrors.map(_._2).reduce(_ || _) 952 953 io.toTop.cpuCriticalError := csrio.criticalErrorState 954} 955 956class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 957 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 958 val flippedLda = true 959 // params alias 960 private val LoadQueueSize = VirtualLoadQueueSize 961 // In/Out // Todo: split it into one-direction bundle 962 val lsqEnqIO = Flipped(new LsqEnqIO) 963 val robLsqIO = new RobLsqIO 964 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 965 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 966 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 967 val vstuIqFeedback = Flipped(Vec(params.VstuCnt, new MemRSFeedbackIO(isVector = true))) 968 val vlduIqFeedback = Flipped(Vec(params.VlduCnt, new MemRSFeedbackIO(isVector = true))) 969 val ldCancel = Vec(params.LdExuCnt, Input(new LoadCancelIO)) 970 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 971 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 972 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 973 // Input 974 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 975 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 976 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 977 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 978 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 979 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 980 981 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 982 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 983 val memoryViolation = Flipped(ValidIO(new Redirect)) 984 val exceptionAddr = Input(new Bundle { 985 val vaddr = UInt(XLEN.W) 986 val gpaddr = UInt(XLEN.W) 987 val isForVSnonLeafPTE = Bool() 988 }) 989 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 990 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 991 val sqDeqPtr = Input(new SqPtr) 992 val lqDeqPtr = Input(new LqPtr) 993 994 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 995 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 996 997 val lqCanAccept = Input(Bool()) 998 val sqCanAccept = Input(Bool()) 999 1000 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 1001 val stIssuePtr = Input(new SqPtr()) 1002 1003 val debugLS = Flipped(Output(new DebugLSIO)) 1004 1005 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 1006 // Output 1007 val redirect = ValidIO(new Redirect) // rob flush MemBlock 1008 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 1009 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 1010 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 1011 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 1012 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 1013 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 1014 1015 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 1016 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 1017 1018 val tlbCsr = Output(new TlbCsrBundle) 1019 val csrCtrl = Output(new CustomCSRCtrlIO) 1020 val sfence = Output(new SfenceBundle) 1021 val isStoreException = Output(Bool()) 1022 val isVlsException = Output(Bool()) 1023 1024 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 1025 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 1026 issueSta ++ 1027 issueHylda ++ issueHysta ++ 1028 issueLda ++ 1029 issueVldu ++ 1030 issueStd 1031 }.toSeq 1032 1033 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 1034 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 1035 writebackSta ++ 1036 writebackHyuLda ++ writebackHyuSta ++ 1037 writebackLda ++ 1038 writebackVldu ++ 1039 writebackStd 1040 } 1041 1042 // store event difftest information 1043 val storeDebugInfo = Vec(EnsbufferWidth, new Bundle { 1044 val robidx = Input(new RobPtr) 1045 val pc = Output(UInt(VAddrBits.W)) 1046 }) 1047} 1048 1049class TopToBackendBundle(implicit p: Parameters) extends XSBundle { 1050 val hartId = Output(UInt(hartIdLen.W)) 1051 val externalInterrupt = Output(new ExternalInterruptIO) 1052 val msiInfo = Output(ValidIO(new MsiInfoBundle)) 1053 val clintTime = Output(ValidIO(UInt(64.W))) 1054 val l2FlushDone = Output(Bool()) 1055} 1056 1057class BackendToTopBundle extends Bundle { 1058 val cpuHalted = Output(Bool()) 1059 val cpuCriticalError = Output(Bool()) 1060} 1061 1062class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle with HasSoCParameter { 1063 val fromTop = Flipped(new TopToBackendBundle) 1064 1065 val toTop = new BackendToTopBundle 1066 1067 val traceCoreInterface = new TraceCoreInterface(hasOffset = true) 1068 val fenceio = new FenceIO 1069 // Todo: merge these bundles into BackendFrontendIO 1070 val frontend = Flipped(new FrontendToCtrlIO) 1071 val frontendSfence = Output(new SfenceBundle) 1072 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 1073 val frontendTlbCsr = Output(new TlbCsrBundle) 1074 val frontendReset = Output(Reset()) 1075 1076 val mem = new BackendMemIO 1077 1078 val perf = Input(new PerfCounterIO) 1079 1080 val tlb = Output(new TlbCsrBundle) 1081 1082 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 1083 1084 val debugTopDown = new Bundle { 1085 val fromRob = new RobCoreTopDownIO 1086 val fromCore = new CoreDispatchTopDownIO 1087 } 1088 val debugRolling = new RobDebugRollingIO 1089 val topDownInfo = new TopDownInfo 1090 val sramTest = new Bundle() { 1091 val mbist = Option.when(hasMbist)(Input(new SramMbistBundle)) 1092 val mbistReset = Option.when(hasMbist)(Input(new DFTResetSignals())) 1093 } 1094} 1095