xref: /XiangShan/src/main/scala/xiangshan/XSTile.scala (revision ebd53cdba163c9ff5304107837ccd354892c11ad) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import org.chipsalliance.cde.config.{Config, Parameters}
20import chisel3._
21import chisel3.util.{Valid, ValidIO, log2Up}
22import freechips.rocketchip.diplomacy._
23import freechips.rocketchip.interrupts._
24import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors}
25import freechips.rocketchip.tilelink._
26import freechips.rocketchip.amba.axi4._
27import device.MsiInfoBundle
28import system.HasSoCParameter
29import top.{BusPerfMonitor, ArgParser, Generator}
30import utility.{DelayN, ResetGen, TLClientsMerger, TLEdgeBuffer, TLLogger, Constantin, ChiselDB, FileRegisters}
31import coupledL2.EnableCHI
32import coupledL2.tl2chi.PortIO
33import xiangshan.backend.trace.TraceCoreInterface
34
35class XSTile()(implicit p: Parameters) extends LazyModule
36  with HasXSParameter
37  with HasSoCParameter
38{
39  override def shouldBeInlined: Boolean = false
40  val core = LazyModule(new XSCore())
41  val l2top = LazyModule(new L2Top())
42
43  val enableL2 = coreParams.L2CacheParamsOpt.isDefined
44  // =========== Public Ports ============
45  val memBlock = core.memBlock.inner
46  val core_l3_pf_port = memBlock.l3_pf_sender_opt
47  val memory_port = if (enableCHI && enableL2) None else Some(l2top.inner.memory_port.get)
48  val tl_uncache = l2top.inner.mmio_port
49  // val axi4_uncache = if (enableCHI) Some(AXI4UserYanker()) else None
50  val beu_int_source = l2top.inner.beu.intNode
51  val core_reset_sink = BundleBridgeSink(Some(() => Reset()))
52  val clint_int_node = l2top.inner.clint_int_node
53  val plic_int_node = l2top.inner.plic_int_node
54  val debug_int_node = l2top.inner.debug_int_node
55  val nmi_int_node = l2top.inner.nmi_int_node
56  memBlock.clint_int_sink := clint_int_node
57  memBlock.plic_int_sink :*= plic_int_node
58  memBlock.debug_int_sink := debug_int_node
59  memBlock.nmi_int_sink := nmi_int_node
60
61  // =========== Components' Connection ============
62  // L1 to l1_xbar
63  coreParams.dcacheParametersOpt.map { _ =>
64    l2top.inner.misc_l2_pmu := l2top.inner.l1d_logger := memBlock.dcache_port :=
65      memBlock.l1d_to_l2_buffer.node := memBlock.dcache.clientNode
66  }
67
68  l2top.inner.misc_l2_pmu := l2top.inner.l1i_logger := memBlock.frontendBridge.icache_node
69  if (!coreParams.softPTW) {
70    l2top.inner.misc_l2_pmu := l2top.inner.ptw_logger := l2top.inner.ptw_to_l2_buffer.node := memBlock.ptw_to_l2_buffer.node
71  }
72
73  // L2 Prefetch
74  l2top.inner.l2cache match {
75    case Some(l2) =>
76      l2.pf_recv_node.foreach(recv => {
77        println("Connecting L1 prefetcher to L2!")
78        recv := memBlock.l2_pf_sender_opt.get
79      })
80    case None =>
81  }
82
83  val core_l3_tpmeta_source_port = l2top.inner.l2cache match {
84    case Some(l2) => l2.tpmeta_source_node
85    case None => None
86  }
87  val core_l3_tpmeta_sink_port = l2top.inner.l2cache match {
88    case Some(l2) => l2.tpmeta_sink_node
89    case None => None
90  }
91
92  // mmio
93  l2top.inner.i_mmio_port := l2top.inner.i_mmio_buffer.node := memBlock.frontendBridge.instr_uncache_node
94  if (icacheParameters.cacheCtrlAddressOpt.nonEmpty) {
95    memBlock.frontendBridge.icachectrl_node := l2top.inner.icachectrl_port_opt.get
96  }
97  l2top.inner.d_mmio_port := memBlock.uncache_port
98
99  // =========== IO Connection ============
100  class XSTileImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
101    val io = IO(new Bundle {
102      val hartId = Input(UInt(hartIdLen.W))
103      val msiInfo = Input(ValidIO(new MsiInfoBundle))
104      val reset_vector = Input(UInt(PAddrBits.W))
105      val cpu_halt = Output(Bool())
106      val cpu_poff = Output(Bool())
107      val cpu_crtical_error = Output(Bool())
108      val hartIsInReset = Output(Bool())
109      val traceCoreInterface = new TraceCoreInterface
110      val debugTopDown = new Bundle {
111        val robHeadPaddr = Valid(UInt(PAddrBits.W))
112        val l3MissMatch = Input(Bool())
113      }
114      val l3Miss = Input(Bool())
115      val chi = if (enableCHI) Some(new PortIO) else None
116      val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None
117      val clintTime = Input(ValidIO(UInt(64.W)))
118    })
119
120    dontTouch(io.hartId)
121    dontTouch(io.msiInfo)
122    dontTouch(io.cpu_poff)
123    if (!io.chi.isEmpty) { dontTouch(io.chi.get) }
124
125    val core_soft_rst = core_reset_sink.in.head._1 // unused
126
127    l2top.module.io.hartId.fromTile := io.hartId
128    core.module.io.hartId := l2top.module.io.hartId.toCore
129    core.module.io.reset_vector := l2top.module.io.reset_vector.toCore
130    core.module.io.msiInfo := io.msiInfo
131    core.module.io.clintTime := io.clintTime
132    l2top.module.io.reset_vector.fromTile := io.reset_vector
133    l2top.module.io.cpu_halt.fromCore := core.module.io.cpu_halt
134    io.cpu_halt := l2top.module.io.cpu_halt.toTile
135    l2top.module.io.cpu_critical_error.fromCore := core.module.io.cpu_critical_error
136    io.cpu_crtical_error := l2top.module.io.cpu_critical_error.toTile
137
138    l2top.module.io.hartIsInReset.resetInFrontend := core.module.io.resetInFrontend
139    io.hartIsInReset := l2top.module.io.hartIsInReset.toTile
140    l2top.module.io.traceCoreInterface.fromCore <> core.module.io.traceCoreInterface
141    io.traceCoreInterface <> l2top.module.io.traceCoreInterface.toTile
142
143    l2top.module.io.beu_errors.icache <> core.module.io.beu_errors.icache
144    l2top.module.io.beu_errors.dcache <> core.module.io.beu_errors.dcache
145
146    //lower power
147    l2top.module.io.l2_flush_en := core.module.io.l2_flush_en
148    core.module.io.l2_flush_done := l2top.module.io.l2_flush_done
149    io.cpu_poff := core.module.io.power_down_en
150    if (enableL2) {
151      // TODO: add ECC interface of L2
152
153      l2top.module.io.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.io.beu_errors.l2)
154      core.module.io.l2_hint.bits.sourceId := l2top.module.io.l2_hint.bits.sourceId
155      core.module.io.l2_hint.bits.isKeyword := l2top.module.io.l2_hint.bits.isKeyword
156      core.module.io.l2_hint.valid := l2top.module.io.l2_hint.valid
157
158      core.module.io.l2PfqBusy := false.B
159      core.module.io.debugTopDown.l2MissMatch := l2top.module.io.debugTopDown.l2MissMatch
160      l2top.module.io.debugTopDown.robHeadPaddr := core.module.io.debugTopDown.robHeadPaddr
161      l2top.module.io.debugTopDown.robTrueCommit := core.module.io.debugTopDown.robTrueCommit
162      l2top.module.io.l2_pmp_resp := core.module.io.l2_pmp_resp
163      core.module.io.l2_tlb_req <> l2top.module.io.l2_tlb_req
164      core.module.io.topDownInfo.l2Miss := l2top.module.io.l2Miss
165
166      core.module.io.perfEvents <> l2top.module.io.perfEvents
167    } else {
168
169      l2top.module.io.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.io.beu_errors.l2)
170      core.module.io.l2_hint.bits.sourceId := l2top.module.io.l2_hint.bits.sourceId
171      core.module.io.l2_hint.bits.isKeyword := l2top.module.io.l2_hint.bits.isKeyword
172      core.module.io.l2_hint.valid := l2top.module.io.l2_hint.valid
173
174      core.module.io.l2PfqBusy := false.B
175      core.module.io.debugTopDown.l2MissMatch := false.B
176      core.module.io.topDownInfo.l2Miss := false.B
177
178      core.module.io.l2_tlb_req.req.valid := false.B
179      core.module.io.l2_tlb_req.req.bits := DontCare
180      core.module.io.l2_tlb_req.req_kill := DontCare
181      core.module.io.l2_tlb_req.resp.ready := true.B
182
183      core.module.io.perfEvents <> DontCare
184    }
185
186    io.debugTopDown.robHeadPaddr := core.module.io.debugTopDown.robHeadPaddr
187    core.module.io.debugTopDown.l3MissMatch := io.debugTopDown.l3MissMatch
188    l2top.module.io.l3Miss.fromTile := io.l3Miss
189    core.module.io.topDownInfo.l3Miss := l2top.module.io.l3Miss.toCore
190
191    io.chi.foreach(_ <> l2top.module.io.chi.get)
192    l2top.module.io.nodeID.foreach(_ := io.nodeID.get)
193
194    if (debugOpts.ResetGen && enableL2) {
195      core.module.reset := l2top.module.reset_core
196    }
197  }
198
199  lazy val module = new XSTileImp(this)
200}
201