1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Config, Parameters} 20import chisel3._ 21import chisel3.util.{Valid, ValidIO, log2Up} 22import freechips.rocketchip.diplomacy._ 23import freechips.rocketchip.interrupts._ 24import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors} 25import freechips.rocketchip.tilelink._ 26import freechips.rocketchip.amba.axi4._ 27import system.HasSoCParameter 28import top.{ArgParser, BusPerfMonitor, Generator} 29import utility.{ChiselDB, Constantin, DFTResetSignals, DelayN, FileRegisters, IntBuffer, ResetGen, TLClientsMerger, TLEdgeBuffer, TLLogger} 30import utility.sram.SramMbistBundle 31import coupledL2.EnableCHI 32import coupledL2.tl2chi.PortIO 33import xiangshan.backend.trace.TraceCoreInterface 34 35class XSTile()(implicit p: Parameters) extends LazyModule 36 with HasXSParameter 37 with HasSoCParameter 38{ 39 override def shouldBeInlined: Boolean = false 40 val core = LazyModule(new XSCore()) 41 val l2top = LazyModule(new L2Top()) 42 43 val enableL2 = coreParams.L2CacheParamsOpt.isDefined 44 // =========== Public Ports ============ 45 val memBlock = core.memBlock.inner 46 val core_l3_pf_port = memBlock.l3_pf_sender_opt 47 val memory_port = if (enableCHI && enableL2) None else Some(l2top.inner.memory_port.get) 48 val tl_uncache = l2top.inner.mmio_port 49 val sep_tl_opt = l2top.inner.sep_tl_port_opt 50 val beu_int_source = l2top.inner.beu.intNode 51 val core_reset_sink = BundleBridgeSink(Some(() => Reset())) 52 val clint_int_node = l2top.inner.clint_int_node 53 val plic_int_node = l2top.inner.plic_int_node 54 val debug_int_node = l2top.inner.debug_int_node 55 val nmi_int_node = l2top.inner.nmi_int_node 56 memBlock.clint_int_sink := clint_int_node 57 memBlock.plic_int_sink :*= plic_int_node 58 memBlock.debug_int_sink := debug_int_node 59 memBlock.nmi_int_sink := nmi_int_node 60 memBlock.beu_local_int_sink := IntBuffer() := l2top.inner.beu_local_int_source 61 62 // =========== Components' Connection ============ 63 // L1 to l1_xbar 64 coreParams.dcacheParametersOpt.map { _ => 65 l2top.inner.misc_l2_pmu := l2top.inner.l1d_logger := memBlock.dcache_port := 66 memBlock.l1d_to_l2_buffer.node := memBlock.dcache.clientNode 67 } 68 69 l2top.inner.misc_l2_pmu := l2top.inner.l1i_logger := memBlock.frontendBridge.icache_node 70 if (!coreParams.softPTW) { 71 l2top.inner.misc_l2_pmu := l2top.inner.ptw_logger := l2top.inner.ptw_to_l2_buffer.node := memBlock.ptw_to_l2_buffer.node 72 } 73 74 // L2 Prefetch 75 l2top.inner.l2cache match { 76 case Some(l2) => 77 l2.pf_recv_node.foreach(recv => { 78 println("Connecting L1 prefetcher to L2!") 79 recv := memBlock.l2_pf_sender_opt.get 80 }) 81 case None => 82 } 83 84 val core_l3_tpmeta_source_port = l2top.inner.l2cache match { 85 case Some(l2) => l2.tpmeta_source_node 86 case None => None 87 } 88 val core_l3_tpmeta_sink_port = l2top.inner.l2cache match { 89 case Some(l2) => l2.tpmeta_sink_node 90 case None => None 91 } 92 93 // mmio 94 l2top.inner.i_mmio_port := l2top.inner.i_mmio_buffer.node := memBlock.frontendBridge.instr_uncache_node 95 if (icacheParameters.cacheCtrlAddressOpt.nonEmpty) { 96 memBlock.frontendBridge.icachectrl_node := l2top.inner.icachectrl_port_opt.get 97 } 98 l2top.inner.d_mmio_port := memBlock.uncache_port 99 100 // =========== IO Connection ============ 101 class XSTileImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 102 val io = IO(new Bundle { 103 val hartId = Input(UInt(hartIdLen.W)) 104 val msiInfo = Input(ValidIO(UInt(soc.IMSICParams.MSI_INFO_WIDTH.W))) 105 val msiAck = Output(Bool()) 106 val reset_vector = Input(UInt(PAddrBits.W)) 107 val cpu_halt = Output(Bool()) 108 val cpu_crtical_error = Output(Bool()) 109 val hartIsInReset = Output(Bool()) 110 val traceCoreInterface = new TraceCoreInterface 111 val debugTopDown = new Bundle { 112 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 113 val l3MissMatch = Input(Bool()) 114 } 115 val l3Miss = Input(Bool()) 116 val chi = if (enableCHI) Some(new PortIO) else None 117 val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None 118 val clintTime = Input(ValidIO(UInt(64.W))) 119 val sramTest = new Bundle() { 120 val mbist = Option.when(hasMbist)(Input(new SramMbistBundle)) 121 val mbistReset = Option.when(hasMbist)(Input(new DFTResetSignals())) 122 val sramCtl = Option.when(hasSramCtl)(Input(UInt(64.W))) 123 } 124 val l2_flush_en = Option.when(EnablePowerDown) (Output(Bool())) 125 val l2_flush_done = Option.when(EnablePowerDown) (Output(Bool())) 126 }) 127 128 dontTouch(io.hartId) 129 dontTouch(io.msiInfo) 130 if (!io.chi.isEmpty) { dontTouch(io.chi.get) } 131 132 val core_soft_rst = core_reset_sink.in.head._1 // unused 133 134 l2top.module.io.hartId.fromTile := io.hartId 135 core.module.io.hartId := l2top.module.io.hartId.toCore 136 core.module.io.reset_vector := l2top.module.io.reset_vector.toCore 137 core.module.io.msiInfo := l2top.module.io.msiInfo.toCore 138 l2top.module.io.msiInfo.fromTile := io.msiInfo 139 core.module.io.clintTime := l2top.module.io.clintTime.toCore 140 l2top.module.io.clintTime.fromTile := io.clintTime 141 l2top.module.io.reset_vector.fromTile := io.reset_vector 142 l2top.module.io.cpu_halt.fromCore := core.module.io.cpu_halt 143 io.cpu_halt := l2top.module.io.cpu_halt.toTile 144 l2top.module.io.cpu_critical_error.fromCore := core.module.io.cpu_critical_error 145 io.cpu_crtical_error := l2top.module.io.cpu_critical_error.toTile 146 l2top.module.io.msiAck.fromCore := core.module.io.msiAck 147 io.msiAck := l2top.module.io.msiAck.toTile 148 149 l2top.module.io.hartIsInReset.resetInFrontend := core.module.io.resetInFrontend 150 io.hartIsInReset := l2top.module.io.hartIsInReset.toTile 151 l2top.module.io.traceCoreInterface.fromCore <> core.module.io.traceCoreInterface 152 io.traceCoreInterface <> l2top.module.io.traceCoreInterface.toTile 153 154 l2top.module.io.beu_errors.icache <> core.module.io.beu_errors.icache 155 l2top.module.io.beu_errors.dcache <> core.module.io.beu_errors.dcache 156 157 l2top.module.io.l2_flush_en.foreach { _ := core.module.io.l2_flush_en } 158 io.l2_flush_en.foreach { _ := core.module.io.l2_flush_en } 159 core.module.io.l2_flush_done := l2top.module.io.l2_flush_done.getOrElse(false.B) 160 io.l2_flush_done.foreach { _ := l2top.module.io.l2_flush_done.getOrElse(false.B) } 161 162 l2top.module.io.sramTestIn := io.sramTest 163 core.module.io.sramTest := l2top.module.io.sramTestOut 164 165 if (enableL2) { 166 // TODO: add ECC interface of L2 167 l2top.module.io.pfCtrlFromCore := core.module.io.l2PfCtrl 168 169 l2top.module.io.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.io.beu_errors.l2) 170 core.module.io.l2_hint.bits.sourceId := l2top.module.io.l2_hint.bits.sourceId 171 core.module.io.l2_hint.bits.isKeyword := l2top.module.io.l2_hint.bits.isKeyword 172 core.module.io.l2_hint.valid := l2top.module.io.l2_hint.valid 173 174 core.module.io.l2PfqBusy := false.B 175 core.module.io.debugTopDown.l2MissMatch := l2top.module.io.debugTopDown.l2MissMatch 176 l2top.module.io.debugTopDown.robHeadPaddr := core.module.io.debugTopDown.robHeadPaddr 177 l2top.module.io.debugTopDown.robTrueCommit := core.module.io.debugTopDown.robTrueCommit 178 l2top.module.io.l2_pmp_resp := core.module.io.l2_pmp_resp 179 core.module.io.l2_tlb_req <> l2top.module.io.l2_tlb_req 180 core.module.io.topDownInfo.l2Miss := l2top.module.io.l2Miss 181 182 core.module.io.perfEvents <> l2top.module.io.perfEvents 183 } else { 184 185 l2top.module.io.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.io.beu_errors.l2) 186 core.module.io.l2_hint.bits.sourceId := l2top.module.io.l2_hint.bits.sourceId 187 core.module.io.l2_hint.bits.isKeyword := l2top.module.io.l2_hint.bits.isKeyword 188 core.module.io.l2_hint.valid := l2top.module.io.l2_hint.valid 189 190 core.module.io.l2PfqBusy := false.B 191 core.module.io.debugTopDown.l2MissMatch := false.B 192 core.module.io.topDownInfo.l2Miss := false.B 193 194 core.module.io.l2_tlb_req.req.valid := false.B 195 core.module.io.l2_tlb_req.req.bits := DontCare 196 core.module.io.l2_tlb_req.req_kill := DontCare 197 core.module.io.l2_tlb_req.resp.ready := true.B 198 199 core.module.io.perfEvents <> DontCare 200 } 201 202 io.debugTopDown.robHeadPaddr := core.module.io.debugTopDown.robHeadPaddr 203 core.module.io.debugTopDown.l3MissMatch := io.debugTopDown.l3MissMatch 204 l2top.module.io.l3Miss.fromTile := io.l3Miss 205 core.module.io.topDownInfo.l3Miss := l2top.module.io.l3Miss.toCore 206 207 io.chi.foreach(_ <> l2top.module.io.chi.get) 208 l2top.module.io.nodeID.foreach(_ := io.nodeID.get) 209 210 if (debugOpts.ResetGen && enableL2) { 211 core.module.reset := l2top.module.reset_core 212 } 213 } 214 215 lazy val module = new XSTileImp(this) 216} 217