1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Config, Parameters} 20import chisel3._ 21import chisel3.util.{Valid, ValidIO, log2Up} 22import freechips.rocketchip.diplomacy._ 23import freechips.rocketchip.interrupts._ 24import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors} 25import freechips.rocketchip.tilelink._ 26import freechips.rocketchip.amba.axi4._ 27import device.MsiInfoBundle 28import system.HasSoCParameter 29import top.{ArgParser, BusPerfMonitor, Generator} 30import utility.{ChiselDB, Constantin, DFTResetSignals, DelayN, FileRegisters, IntBuffer, ResetGen, TLClientsMerger, TLEdgeBuffer, TLLogger} 31import coupledL2.EnableCHI 32import coupledL2.tl2chi.PortIO 33import utility.sram.SramBroadcastBundle 34import xiangshan.backend.trace.TraceCoreInterface 35 36class XSTile()(implicit p: Parameters) extends LazyModule 37 with HasXSParameter 38 with HasSoCParameter 39{ 40 override def shouldBeInlined: Boolean = false 41 val core = LazyModule(new XSCore()) 42 val l2top = LazyModule(new L2Top()) 43 44 val enableL2 = coreParams.L2CacheParamsOpt.isDefined 45 // =========== Public Ports ============ 46 val memBlock = core.memBlock.inner 47 val core_l3_pf_port = memBlock.l3_pf_sender_opt 48 val memory_port = if (enableCHI && enableL2) None else Some(l2top.inner.memory_port.get) 49 val tl_uncache = l2top.inner.mmio_port 50 val sep_dm_opt = l2top.inner.sep_dm_port_opt 51 val beu_int_source = l2top.inner.beu.intNode 52 val core_reset_sink = BundleBridgeSink(Some(() => Reset())) 53 val clint_int_node = l2top.inner.clint_int_node 54 val plic_int_node = l2top.inner.plic_int_node 55 val debug_int_node = l2top.inner.debug_int_node 56 val nmi_int_node = l2top.inner.nmi_int_node 57 memBlock.clint_int_sink := clint_int_node 58 memBlock.plic_int_sink :*= plic_int_node 59 memBlock.debug_int_sink := debug_int_node 60 memBlock.nmi_int_sink := nmi_int_node 61 memBlock.beu_local_int_sink := IntBuffer() := l2top.inner.beu_local_int_source 62 63 // =========== Components' Connection ============ 64 // L1 to l1_xbar 65 coreParams.dcacheParametersOpt.map { _ => 66 l2top.inner.misc_l2_pmu := l2top.inner.l1d_logger := memBlock.dcache_port := 67 memBlock.l1d_to_l2_buffer.node := memBlock.dcache.clientNode 68 } 69 70 l2top.inner.misc_l2_pmu := l2top.inner.l1i_logger := memBlock.frontendBridge.icache_node 71 if (!coreParams.softPTW) { 72 l2top.inner.misc_l2_pmu := l2top.inner.ptw_logger := l2top.inner.ptw_to_l2_buffer.node := memBlock.ptw_to_l2_buffer.node 73 } 74 75 // L2 Prefetch 76 l2top.inner.l2cache match { 77 case Some(l2) => 78 l2.pf_recv_node.foreach(recv => { 79 println("Connecting L1 prefetcher to L2!") 80 recv := memBlock.l2_pf_sender_opt.get 81 }) 82 case None => 83 } 84 85 val core_l3_tpmeta_source_port = l2top.inner.l2cache match { 86 case Some(l2) => l2.tpmeta_source_node 87 case None => None 88 } 89 val core_l3_tpmeta_sink_port = l2top.inner.l2cache match { 90 case Some(l2) => l2.tpmeta_sink_node 91 case None => None 92 } 93 94 // mmio 95 l2top.inner.i_mmio_port := l2top.inner.i_mmio_buffer.node := memBlock.frontendBridge.instr_uncache_node 96 if (icacheParameters.cacheCtrlAddressOpt.nonEmpty) { 97 memBlock.frontendBridge.icachectrl_node := l2top.inner.icachectrl_port_opt.get 98 } 99 l2top.inner.d_mmio_port := memBlock.uncache_port 100 101 // =========== IO Connection ============ 102 class XSTileImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 103 val io = IO(new Bundle { 104 val hartId = Input(UInt(hartIdLen.W)) 105 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 106 val reset_vector = Input(UInt(PAddrBits.W)) 107 val cpu_halt = Output(Bool()) 108 val cpu_crtical_error = Output(Bool()) 109 val hartIsInReset = Output(Bool()) 110 val traceCoreInterface = new TraceCoreInterface 111 val debugTopDown = new Bundle { 112 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 113 val l3MissMatch = Input(Bool()) 114 } 115 val l3Miss = Input(Bool()) 116 val chi = if (enableCHI) Some(new PortIO) else None 117 val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None 118 val clintTime = Input(ValidIO(UInt(64.W))) 119 val dft = if(hasMbist) Some(Input(new SramBroadcastBundle)) else None 120 val dft_reset = if(hasMbist) Some(Input(new DFTResetSignals())) else None 121 val l2_flush_en = Option.when(EnablePowerDown) (Output(Bool())) 122 val l2_flush_done = Option.when(EnablePowerDown) (Output(Bool())) 123 }) 124 125 dontTouch(io.hartId) 126 dontTouch(io.msiInfo) 127 if (!io.chi.isEmpty) { dontTouch(io.chi.get) } 128 129 val core_soft_rst = core_reset_sink.in.head._1 // unused 130 131 l2top.module.io.hartId.fromTile := io.hartId 132 core.module.io.hartId := l2top.module.io.hartId.toCore 133 core.module.io.reset_vector := l2top.module.io.reset_vector.toCore 134 core.module.io.msiInfo := l2top.module.io.msiInfo.toCore 135 l2top.module.io.msiInfo.fromTile := io.msiInfo 136 core.module.io.clintTime := l2top.module.io.clintTime.toCore 137 l2top.module.io.clintTime.fromTile := io.clintTime 138 l2top.module.io.reset_vector.fromTile := io.reset_vector 139 l2top.module.io.cpu_halt.fromCore := core.module.io.cpu_halt 140 io.cpu_halt := l2top.module.io.cpu_halt.toTile 141 l2top.module.io.cpu_critical_error.fromCore := core.module.io.cpu_critical_error 142 io.cpu_crtical_error := l2top.module.io.cpu_critical_error.toTile 143 144 l2top.module.io.hartIsInReset.resetInFrontend := core.module.io.resetInFrontend 145 io.hartIsInReset := l2top.module.io.hartIsInReset.toTile 146 l2top.module.io.traceCoreInterface.fromCore <> core.module.io.traceCoreInterface 147 io.traceCoreInterface <> l2top.module.io.traceCoreInterface.toTile 148 149 l2top.module.io.beu_errors.icache <> core.module.io.beu_errors.icache 150 l2top.module.io.beu_errors.dcache <> core.module.io.beu_errors.dcache 151 152 l2top.module.io.l2_flush_en.foreach { _ := core.module.io.l2_flush_en } 153 io.l2_flush_en.foreach { _ := core.module.io.l2_flush_en } 154 core.module.io.l2_flush_done := l2top.module.io.l2_flush_done.getOrElse(false.B) 155 io.l2_flush_done.foreach { _ := l2top.module.io.l2_flush_done.getOrElse(false.B) } 156 157 l2top.module.io.dft.zip(io.dft).foreach({case(a, b) => a := b}) 158 l2top.module.io.dft_reset.zip(io.dft_reset).foreach({case(a, b) => a := b}) 159 core.module.io.dft.zip(l2top.module.io.dft_out).foreach({case(a, b) => a := b}) 160 core.module.io.dft_reset.zip(l2top.module.io.dft_reset_out).foreach({case(a, b) => a := b}) 161 162 if (enableL2) { 163 // TODO: add ECC interface of L2 164 l2top.module.io.pfCtrlFromCore := core.module.io.l2PfCtrl 165 166 l2top.module.io.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.io.beu_errors.l2) 167 core.module.io.l2_hint.bits.sourceId := l2top.module.io.l2_hint.bits.sourceId 168 core.module.io.l2_hint.bits.isKeyword := l2top.module.io.l2_hint.bits.isKeyword 169 core.module.io.l2_hint.valid := l2top.module.io.l2_hint.valid 170 171 core.module.io.l2PfqBusy := false.B 172 core.module.io.debugTopDown.l2MissMatch := l2top.module.io.debugTopDown.l2MissMatch 173 l2top.module.io.debugTopDown.robHeadPaddr := core.module.io.debugTopDown.robHeadPaddr 174 l2top.module.io.debugTopDown.robTrueCommit := core.module.io.debugTopDown.robTrueCommit 175 l2top.module.io.l2_pmp_resp := core.module.io.l2_pmp_resp 176 core.module.io.l2_tlb_req <> l2top.module.io.l2_tlb_req 177 core.module.io.topDownInfo.l2Miss := l2top.module.io.l2Miss 178 179 core.module.io.perfEvents <> l2top.module.io.perfEvents 180 } else { 181 182 l2top.module.io.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.io.beu_errors.l2) 183 core.module.io.l2_hint.bits.sourceId := l2top.module.io.l2_hint.bits.sourceId 184 core.module.io.l2_hint.bits.isKeyword := l2top.module.io.l2_hint.bits.isKeyword 185 core.module.io.l2_hint.valid := l2top.module.io.l2_hint.valid 186 187 core.module.io.l2PfqBusy := false.B 188 core.module.io.debugTopDown.l2MissMatch := false.B 189 core.module.io.topDownInfo.l2Miss := false.B 190 191 core.module.io.l2_tlb_req.req.valid := false.B 192 core.module.io.l2_tlb_req.req.bits := DontCare 193 core.module.io.l2_tlb_req.req_kill := DontCare 194 core.module.io.l2_tlb_req.resp.ready := true.B 195 196 core.module.io.perfEvents <> DontCare 197 } 198 199 io.debugTopDown.robHeadPaddr := core.module.io.debugTopDown.robHeadPaddr 200 core.module.io.debugTopDown.l3MissMatch := io.debugTopDown.l3MissMatch 201 l2top.module.io.l3Miss.fromTile := io.l3Miss 202 core.module.io.topDownInfo.l3Miss := l2top.module.io.l3Miss.toCore 203 204 io.chi.foreach(_ <> l2top.module.io.chi.get) 205 l2top.module.io.nodeID.foreach(_ := io.nodeID.get) 206 207 if (debugOpts.ResetGen && enableL2) { 208 core.module.reset := l2top.module.reset_core 209 } 210 } 211 212 lazy val module = new XSTileImp(this) 213} 214