1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Config, Parameters} 20import chisel3._ 21import chisel3.util.{Valid, ValidIO, log2Up} 22import freechips.rocketchip.diplomacy._ 23import freechips.rocketchip.interrupts._ 24import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors} 25import freechips.rocketchip.tilelink._ 26import freechips.rocketchip.amba.axi4._ 27import device.MsiInfoBundle 28import system.HasSoCParameter 29import top.{BusPerfMonitor, ArgParser, Generator} 30import utility.{DelayN, ResetGen, TLClientsMerger, TLEdgeBuffer, TLLogger, Constantin, ChiselDB, FileRegisters} 31import coupledL2.EnableCHI 32import coupledL2.tl2chi.PortIO 33 34class XSTile()(implicit p: Parameters) extends LazyModule 35 with HasXSParameter 36 with HasSoCParameter 37{ 38 override def shouldBeInlined: Boolean = false 39 val core = LazyModule(new XSCore()) 40 val l2top = LazyModule(new L2Top()) 41 42 val enableL2 = coreParams.L2CacheParamsOpt.isDefined 43 // =========== Public Ports ============ 44 val memBlock = core.memBlock.inner 45 val core_l3_pf_port = memBlock.l3_pf_sender_opt 46 val memory_port = if (enableCHI && enableL2) None else Some(l2top.inner.memory_port.get) 47 val tl_uncache = l2top.inner.mmio_port 48 // val axi4_uncache = if (enableCHI) Some(AXI4UserYanker()) else None 49 val beu_int_source = l2top.inner.beu.intNode 50 val core_reset_sink = BundleBridgeSink(Some(() => Reset())) 51 val clint_int_node = l2top.inner.clint_int_node 52 val plic_int_node = l2top.inner.plic_int_node 53 val debug_int_node = l2top.inner.debug_int_node 54 memBlock.clint_int_sink := clint_int_node 55 memBlock.plic_int_sink :*= plic_int_node 56 memBlock.debug_int_sink := debug_int_node 57 58 // =========== Components' Connection ============ 59 // L1 to l1_xbar 60 coreParams.dcacheParametersOpt.map { _ => 61 l2top.inner.misc_l2_pmu := l2top.inner.l1d_logger := memBlock.dcache_port := 62 memBlock.l1d_to_l2_buffer.node := memBlock.dcache.clientNode 63 } 64 65 l2top.inner.misc_l2_pmu := l2top.inner.l1i_logger := memBlock.frontendBridge.icache_node 66 if (!coreParams.softPTW) { 67 l2top.inner.misc_l2_pmu := l2top.inner.ptw_logger := l2top.inner.ptw_to_l2_buffer.node := memBlock.ptw_to_l2_buffer.node 68 } 69 70 // L2 Prefetch 71 l2top.inner.l2cache match { 72 case Some(l2) => 73 l2.pf_recv_node.foreach(recv => { 74 println("Connecting L1 prefetcher to L2!") 75 recv := memBlock.l2_pf_sender_opt.get 76 }) 77 case None => 78 } 79 80 // CMO 81 l2top.inner.l2cache match { 82 case Some(l2) => 83 l2.cmo_sink_node.foreach(recv => { 84 recv := memBlock.cmo_sender.get 85 }) 86 l2.cmo_source_node.foreach(resp => { 87 memBlock.cmo_reciver.get := resp 88 }) 89 case None => 90 } 91 92 val core_l3_tpmeta_source_port = l2top.inner.l2cache match { 93 case Some(l2) => l2.tpmeta_source_node 94 case None => None 95 } 96 val core_l3_tpmeta_sink_port = l2top.inner.l2cache match { 97 case Some(l2) => l2.tpmeta_sink_node 98 case None => None 99 } 100 101 // mmio 102 l2top.inner.i_mmio_port := l2top.inner.i_mmio_buffer.node := memBlock.frontendBridge.instr_uncache_node 103 l2top.inner.d_mmio_port := memBlock.uncache.clientNode 104 105 // =========== IO Connection ============ 106 class XSTileImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 107 val io = IO(new Bundle { 108 val hartId = Input(UInt(hartIdLen.W)) 109 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 110 val reset_vector = Input(UInt(PAddrBits.W)) 111 val cpu_halt = Output(Bool()) 112 val hartIsInReset = Output(Bool()) 113 val debugTopDown = new Bundle { 114 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 115 val l3MissMatch = Input(Bool()) 116 } 117 val chi = if (enableCHI) Some(new PortIO) else None 118 val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None 119 val clintTime = Input(ValidIO(UInt(64.W))) 120 }) 121 122 dontTouch(io.hartId) 123 dontTouch(io.msiInfo) 124 if (!io.chi.isEmpty) { dontTouch(io.chi.get) } 125 126 val core_soft_rst = core_reset_sink.in.head._1 // unused 127 128 l2top.module.io.hartId.fromTile := io.hartId 129 core.module.io.hartId := l2top.module.io.hartId.toCore 130 core.module.io.reset_vector := l2top.module.io.reset_vector.toCore 131 core.module.io.msiInfo := io.msiInfo 132 core.module.io.clintTime := io.clintTime 133 l2top.module.io.reset_vector.fromTile := io.reset_vector 134 l2top.module.io.cpu_halt.fromCore := core.module.io.cpu_halt 135 io.cpu_halt := l2top.module.io.cpu_halt.toTile 136 137 l2top.module.io.hartIsInReset.resetInFrontend := core.module.io.resetInFrontend 138 io.hartIsInReset := l2top.module.io.hartIsInReset.toTile 139 140 core.module.io.perfEvents <> DontCare 141 142 l2top.module.io.beu_errors.icache <> core.module.io.beu_errors.icache 143 l2top.module.io.beu_errors.dcache <> core.module.io.beu_errors.dcache 144 if (enableL2) { 145 // TODO: add ECC interface of L2 146 147 l2top.module.io.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.io.beu_errors.l2) 148 core.module.io.l2_hint.bits.sourceId := l2top.module.io.l2_hint.bits.sourceId 149 core.module.io.l2_hint.bits.isKeyword := l2top.module.io.l2_hint.bits.isKeyword 150 core.module.io.l2_hint.valid := l2top.module.io.l2_hint.valid 151 152 core.module.io.l2PfqBusy := false.B 153 core.module.io.debugTopDown.l2MissMatch := l2top.module.io.debugTopDown.l2MissMatch 154 l2top.module.io.debugTopDown.robHeadPaddr := core.module.io.debugTopDown.robHeadPaddr 155 l2top.module.io.debugTopDown.robTrueCommit := core.module.io.debugTopDown.robTrueCommit 156 l2top.module.io.l2_pmp_resp := core.module.io.l2_pmp_resp 157 core.module.io.l2_tlb_req <> l2top.module.io.l2_tlb_req 158 } else { 159 160 l2top.module.io.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.io.beu_errors.l2) 161 core.module.io.l2_hint.bits.sourceId := l2top.module.io.l2_hint.bits.sourceId 162 core.module.io.l2_hint.bits.isKeyword := l2top.module.io.l2_hint.bits.isKeyword 163 core.module.io.l2_hint.valid := l2top.module.io.l2_hint.valid 164 165 core.module.io.l2PfqBusy := false.B 166 core.module.io.debugTopDown.l2MissMatch := false.B 167 168 core.module.io.l2_tlb_req.req.valid := false.B 169 core.module.io.l2_tlb_req.req.bits := DontCare 170 core.module.io.l2_tlb_req.req_kill := DontCare 171 core.module.io.l2_tlb_req.resp.ready := true.B 172 } 173 174 io.debugTopDown.robHeadPaddr := core.module.io.debugTopDown.robHeadPaddr 175 core.module.io.debugTopDown.l3MissMatch := io.debugTopDown.l3MissMatch 176 177 io.chi.foreach(_ <> l2top.module.io.chi.get) 178 l2top.module.io.nodeID.foreach(_ := io.nodeID.get) 179 180 if (debugOpts.ResetGen && enableL2) { 181 core.module.reset := l2top.module.reset_core 182 } 183 } 184 185 lazy val module = new XSTileImp(this) 186} 187