1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chisel3._ 20import org.chipsalliance.cde.config.{Config, Parameters} 21import chisel3.util.{Valid, ValidIO} 22import freechips.rocketchip.diplomacy._ 23import freechips.rocketchip.interrupts._ 24import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors} 25import freechips.rocketchip.tilelink._ 26import coupledL2.{L2ParamKey, CoupledL2} 27import system.HasSoCParameter 28import top.BusPerfMonitor 29import utility.{DelayN, ResetGen, TLClientsMerger, TLEdgeBuffer, TLLogger} 30 31class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter { 32 val ecc_error = Valid(UInt(soc.PAddrBits.W)) 33} 34 35class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors { 36 val icache = new L1BusErrorUnitInfo 37 val dcache = new L1BusErrorUnitInfo 38 val l2 = new L1BusErrorUnitInfo 39 40 override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] = 41 List( 42 Some(icache.ecc_error, "I_ECC", "Icache ecc error"), 43 Some(dcache.ecc_error, "D_ECC", "Dcache ecc error"), 44 Some(l2.ecc_error, "L2_ECC", "L2Cache ecc error") 45 ) 46} 47 48/** 49 * XSTileMisc contains every module except Core and L2 Cache 50 */ 51class XSTileMisc()(implicit p: Parameters) extends LazyModule 52 with HasXSParameter 53 with HasSoCParameter 54{ 55 override def shouldBeInlined: Boolean = false 56 val l1_xbar = TLXbar() 57 val mmio_xbar = TLXbar() 58 val mmio_port = TLIdentityNode() // to L3 59 val memory_port = TLIdentityNode() 60 val beu = LazyModule(new BusErrorUnit( 61 new XSL1BusErrors(), BusErrorUnitParams(0x38010000) 62 )) 63 val misc_l2_pmu = BusPerfMonitor(name = "Misc_L2", enable = !debugOpts.FPGAPlatform) 64 val l2_l3_pmu = BusPerfMonitor(name = "L2_L3", enable = !debugOpts.FPGAPlatform, stat_latency = true) 65 val l1d_logger = TLLogger(s"L2_L1D_${coreParams.HartId}", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) 66 val l2_binder = coreParams.L2CacheParamsOpt.map(_ => BankBinder(coreParams.L2NBanks, 64)) 67 68 val i_mmio_port = TLTempNode() 69 val d_mmio_port = TLTempNode() 70 71 misc_l2_pmu := l1d_logger 72 l1_xbar :=* misc_l2_pmu 73 74 l2_binder match { 75 case Some(binder) => 76 memory_port := l2_l3_pmu := TLClientsMerger() := TLXbar() :=* binder 77 case None => 78 memory_port := l1_xbar 79 } 80 81 mmio_xbar := TLBuffer.chainNode(2) := i_mmio_port 82 mmio_xbar := TLBuffer.chainNode(2) := d_mmio_port 83 beu.node := TLBuffer.chainNode(1) := mmio_xbar 84 mmio_port := TLBuffer() := mmio_xbar 85 86 class XSTileMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 87 val beu_errors = IO(Input(chiselTypeOf(beu.module.io.errors))) 88 beu.module.io.errors <> beu_errors 89 } 90 91 lazy val module = new XSTileMiscImp(this) 92} 93 94class XSTile()(implicit p: Parameters) extends LazyModule 95 with HasXSParameter 96 with HasSoCParameter 97{ 98 override def shouldBeInlined: Boolean = false 99 private val core = LazyModule(new XSCore()) 100 private val misc = LazyModule(new XSTileMisc()) 101 private val l2cache = coreParams.L2CacheParamsOpt.map(l2param => 102 LazyModule(new CoupledL2()(new Config((_, _, _) => { 103 case L2ParamKey => l2param.copy( 104 hartIds = Seq(p(XSCoreParamsKey).HartId), 105 FPGAPlatform = debugOpts.FPGAPlatform 106 ) 107 }))) 108 ) 109 110 // public ports 111 val core_l3_pf_port = core.memBlock.l3_pf_sender_opt 112 val memory_port = misc.memory_port 113 val uncache = misc.mmio_port 114 val clint_int_sink = core.clint_int_sink 115 val plic_int_sink = core.plic_int_sink 116 val debug_int_sink = core.debug_int_sink 117 val beu_int_source = misc.beu.intNode 118 val core_reset_sink = BundleBridgeSink(Some(() => Reset())) 119 val l1d_l2_pmu = BusPerfMonitor(name = "L1d_L2", enable = !debugOpts.FPGAPlatform, stat_latency = true) 120 121 val l1d_to_l2_bufferOpt = coreParams.dcacheParametersOpt.map { _ => 122 val buffer = LazyModule(new TLBuffer) 123 misc.l1d_logger := buffer.node := l1d_l2_pmu := core.memBlock.dcache.clientNode 124 buffer 125 } 126 127 def chainBuffer(depth: Int, n: String): (Seq[LazyModule], TLNode) = { 128 val buffers = Seq.fill(depth){ LazyModule(new TLBuffer()) } 129 buffers.zipWithIndex.foreach{ case (b, i) => { 130 b.suggestName(s"${n}_${i}") 131 }} 132 val node = buffers.map(_.node.asInstanceOf[TLNode]).reduce(_ :*=* _) 133 (buffers, node) 134 } 135 136 misc.misc_l2_pmu := TLLogger(s"L2_L1I_${coreParams.HartId}", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) := core.frontend.icache.clientNode 137 if (!coreParams.softPTW) { 138 misc.misc_l2_pmu := TLLogger(s"L2_PTW_${coreParams.HartId}", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) := core.memBlock.ptw_to_l2_buffer.node 139 } 140 141 l2cache match { 142 case Some(l2) => 143 misc.l2_binder.get :*= l2.node :*= misc.l1_xbar 144 l2.pf_recv_node.map(recv => { 145 println("Connecting L1 prefetcher to L2!") 146 recv := core.memBlock.l2_pf_sender_opt.get 147 }) 148 case None => 149 } 150 151 misc.i_mmio_port := core.frontend.instrUncache.clientNode 152 misc.d_mmio_port := core.memBlock.uncache.clientNode 153 154 class XSTileImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 155 val io = IO(new Bundle { 156 val hartId = Input(UInt(64.W)) 157 val reset_vector = Input(UInt(PAddrBits.W)) 158 val cpu_halt = Output(Bool()) 159 val debugTopDown = new Bundle { 160 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 161 val l3MissMatch = Input(Bool()) 162 } 163 }) 164 165 dontTouch(io.hartId) 166 167 val core_soft_rst = core_reset_sink.in.head._1 168 169 core.module.io.hartId := io.hartId 170 core.module.io.reset_vector := DelayN(io.reset_vector, 5) 171 io.cpu_halt := core.module.io.cpu_halt 172 if (l2cache.isDefined) { 173 // TODO: add perfEvents of L2 174 // core.module.io.perfEvents.zip(l2cache.get.module.io.perfEvents.flatten).foreach(x => x._1.value := x._2) 175 core.module.io.perfEvents <> DontCare 176 } 177 else { 178 core.module.io.perfEvents <> DontCare 179 } 180 181 misc.module.beu_errors.icache <> core.module.io.beu_errors.icache 182 misc.module.beu_errors.dcache <> core.module.io.beu_errors.dcache 183 if (l2cache.isDefined) { 184 // TODO: add ECC interface of L2 185 // misc.module.beu_errors.l2.ecc_error.valid := l2cache.get.module.io.ecc_error.valid 186 // misc.module.beu_errors.l2.ecc_error.bits := l2cache.get.module.io.ecc_error.bits 187 misc.module.beu_errors.l2 <> 0.U.asTypeOf(misc.module.beu_errors.l2) 188 core.module.io.l2_hint.bits.sourceId := l2cache.get.module.io.l2_hint.bits 189 core.module.io.l2_hint.valid := l2cache.get.module.io.l2_hint.valid 190 core.module.io.l2PfqBusy := false.B 191 core.module.io.debugTopDown.l2MissMatch := l2cache.get.module.io.debugTopDown.l2MissMatch.head 192 l2cache.get.module.io.debugTopDown.robHeadPaddr.head := core.module.io.debugTopDown.robHeadPaddr 193 } else { 194 misc.module.beu_errors.l2 <> 0.U.asTypeOf(misc.module.beu_errors.l2) 195 core.module.io.l2_hint.bits.sourceId := DontCare 196 core.module.io.l2_hint.valid := false.B 197 core.module.io.l2PfqBusy := false.B 198 core.module.io.debugTopDown.l2MissMatch := false.B 199 } 200 201 io.debugTopDown.robHeadPaddr := core.module.io.debugTopDown.robHeadPaddr 202 core.module.io.debugTopDown.l3MissMatch := io.debugTopDown.l3MissMatch 203 204 // Modules are reset one by one 205 // io_reset ---- 206 // | 207 // v 208 // reset ----> OR_SYNC --> {Misc, L2 Cache, Cores} 209 val resetChain = Seq( 210 Seq(misc.module, core.module) ++ 211 l1d_to_l2_bufferOpt.map(_.module) ++ 212 l2cache.map(_.module) 213 ) 214 ResetGen(resetChain, reset, !debugOpts.FPGAPlatform) 215 } 216 217 lazy val module = new XSTileImp(this) 218} 219