1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Config, Parameters} 20import chisel3._ 21import chisel3.util.{Valid, ValidIO, log2Up} 22import freechips.rocketchip.diplomacy._ 23import freechips.rocketchip.interrupts._ 24import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors} 25import freechips.rocketchip.tilelink._ 26import freechips.rocketchip.amba.axi4._ 27import device.MsiInfoBundle 28import system.HasSoCParameter 29import top.{BusPerfMonitor, ArgParser, Generator} 30import utility.{DelayN, ResetGen, TLClientsMerger, TLEdgeBuffer, TLLogger, Constantin, ChiselDB, FileRegisters} 31import coupledL2.EnableCHI 32import coupledL2.tl2chi.PortIO 33 34class XSTile()(implicit p: Parameters) extends LazyModule 35 with HasXSParameter 36 with HasSoCParameter 37{ 38 override def shouldBeInlined: Boolean = false 39 val core = LazyModule(new XSCore()) 40 val l2top = LazyModule(new L2Top()) 41 42 val enableL2 = coreParams.L2CacheParamsOpt.isDefined 43 // =========== Public Ports ============ 44 val core_l3_pf_port = core.memBlock.l3_pf_sender_opt 45 val memory_port = if (enableCHI && enableL2) None else Some(l2top.memory_port.get) 46 val tl_uncache = l2top.mmio_port 47 // val axi4_uncache = if (enableCHI) Some(AXI4UserYanker()) else None 48 val beu_int_source = l2top.beu.intNode 49 val core_reset_sink = BundleBridgeSink(Some(() => Reset())) 50 val clint_int_node = l2top.clint_int_node 51 val plic_int_node = l2top.plic_int_node 52 val debug_int_node = l2top.debug_int_node 53 core.memBlock.clint_int_sink := clint_int_node 54 core.memBlock.plic_int_sink :*= plic_int_node 55 core.memBlock.debug_int_sink := debug_int_node 56 57 // =========== Components' Connection ============ 58 // L1 to l1_xbar 59 coreParams.dcacheParametersOpt.map { _ => 60 l2top.misc_l2_pmu := l2top.l1d_logger := core.memBlock.dcache_port := 61 core.memBlock.l1d_to_l2_buffer.node := core.memBlock.dcache.clientNode 62 } 63 64 l2top.misc_l2_pmu := l2top.l1i_logger := core.memBlock.frontendBridge.icache_node 65 if (!coreParams.softPTW) { 66 l2top.misc_l2_pmu := l2top.ptw_logger := l2top.ptw_to_l2_buffer.node := core.memBlock.ptw_to_l2_buffer.node 67 } 68 69 // L2 Prefetch 70 l2top.l2cache match { 71 case Some(l2) => 72 l2.pf_recv_node.foreach(recv => { 73 println("Connecting L1 prefetcher to L2!") 74 recv := core.memBlock.l2_pf_sender_opt.get 75 }) 76 case None => 77 } 78 79 // CMO 80 l2top.l2cache match { 81 case Some(l2) => 82 l2.cmo_sink_node.foreach(recv => { 83 recv := core.memBlock.cmo_sender.get 84 }) 85 l2.cmo_source_node.foreach(resp => { 86 core.memBlock.cmo_reciver.get := resp 87 }) 88 case None => 89 } 90 91 val core_l3_tpmeta_source_port = l2top.l2cache match { 92 case Some(l2) => l2.tpmeta_source_node 93 case None => None 94 } 95 val core_l3_tpmeta_sink_port = l2top.l2cache match { 96 case Some(l2) => l2.tpmeta_sink_node 97 case None => None 98 } 99 100 // mmio 101 l2top.i_mmio_port := l2top.i_mmio_buffer.node := core.memBlock.frontendBridge.instr_uncache_node 102 l2top.d_mmio_port := core.memBlock.uncache.clientNode 103 104 // =========== IO Connection ============ 105 class XSTileImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 106 val io = IO(new Bundle { 107 val hartId = Input(UInt(hartIdLen.W)) 108 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 109 val reset_vector = Input(UInt(PAddrBits.W)) 110 val cpu_halt = Output(Bool()) 111 val debugTopDown = new Bundle { 112 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 113 val l3MissMatch = Input(Bool()) 114 } 115 val chi = if (enableCHI) Some(new PortIO) else None 116 val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None 117 val clintTime = Input(ValidIO(UInt(64.W))) 118 }) 119 120 dontTouch(io.hartId) 121 dontTouch(io.msiInfo) 122 if (!io.chi.isEmpty) { dontTouch(io.chi.get) } 123 124 val core_soft_rst = core_reset_sink.in.head._1 // unused 125 126 l2top.module.hartId.fromTile := io.hartId 127 core.module.io.hartId := l2top.module.hartId.toCore 128 core.module.io.reset_vector := l2top.module.reset_vector.toCore 129 core.module.io.msiInfo := io.msiInfo 130 core.module.io.clintTime := io.clintTime 131 l2top.module.reset_vector.fromTile := io.reset_vector 132 l2top.module.cpu_halt.fromCore := core.module.io.cpu_halt 133 io.cpu_halt := l2top.module.cpu_halt.toTile 134 135 core.module.io.perfEvents <> DontCare 136 137 l2top.module.beu_errors.icache <> core.module.io.beu_errors.icache 138 l2top.module.beu_errors.dcache <> core.module.io.beu_errors.dcache 139 if (enableL2) { 140 // TODO: add ECC interface of L2 141 142 l2top.module.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.beu_errors.l2) 143 core.module.io.l2_hint.bits.sourceId := l2top.module.l2_hint.bits.sourceId 144 core.module.io.l2_hint.bits.isKeyword := l2top.module.l2_hint.bits.isKeyword 145 core.module.io.l2_hint.valid := l2top.module.l2_hint.valid 146 147 core.module.io.l2PfqBusy := false.B 148 core.module.io.debugTopDown.l2MissMatch := l2top.module.debugTopDown.l2MissMatch 149 l2top.module.debugTopDown.robHeadPaddr := core.module.io.debugTopDown.robHeadPaddr 150 l2top.module.debugTopDown.robTrueCommit := core.module.io.debugTopDown.robTrueCommit 151 l2top.module.l2_pmp_resp := core.module.io.l2_pmp_resp 152 core.module.io.l2_tlb_req <> l2top.module.l2_tlb_req 153 } else { 154 155 l2top.module.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.beu_errors.l2) 156 core.module.io.l2_hint.bits.sourceId := l2top.module.l2_hint.bits.sourceId 157 core.module.io.l2_hint.bits.isKeyword := l2top.module.l2_hint.bits.isKeyword 158 core.module.io.l2_hint.valid := l2top.module.l2_hint.valid 159 160 core.module.io.l2PfqBusy := false.B 161 core.module.io.debugTopDown.l2MissMatch := false.B 162 163 core.module.io.l2_tlb_req.req.valid := false.B 164 core.module.io.l2_tlb_req.req.bits := DontCare 165 core.module.io.l2_tlb_req.req_kill := DontCare 166 core.module.io.l2_tlb_req.resp.ready := true.B 167 } 168 169 io.debugTopDown.robHeadPaddr := core.module.io.debugTopDown.robHeadPaddr 170 core.module.io.debugTopDown.l3MissMatch := io.debugTopDown.l3MissMatch 171 172 io.chi.foreach(_ <> l2top.module.chi.get) 173 l2top.module.nodeID.foreach(_ := io.nodeID.get) 174 175 if (debugOpts.ResetGen && enableL2) { 176 core.module.reset := l2top.module.reset_core 177 } 178 } 179 180 lazy val module = new XSTileImp(this) 181} 182