xref: /XiangShan/src/main/scala/xiangshan/XSTile.scala (revision 453674e016566fa721fbe46c1cb35f5db2e7eff8) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import org.chipsalliance.cde.config.{Config, Parameters}
20import chisel3._
21import chisel3.util.{Valid, ValidIO}
22import freechips.rocketchip.diplomacy._
23import freechips.rocketchip.interrupts._
24import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors}
25import freechips.rocketchip.tilelink._
26import freechips.rocketchip.amba.axi4._
27import system.HasSoCParameter
28import top.{BusPerfMonitor, ArgParser, Generator}
29import utility.{DelayN, ResetGen, TLClientsMerger, TLEdgeBuffer, TLLogger, Constantin, ChiselDB, FileRegisters}
30import coupledL2.EnableCHI
31import coupledL2.tl2chi.PortIO
32
33class XSTile()(implicit p: Parameters) extends LazyModule
34  with HasXSParameter
35  with HasSoCParameter
36{
37  override def shouldBeInlined: Boolean = false
38  val core = LazyModule(new XSCore())
39  val l2top = LazyModule(new L2Top())
40
41  val enableCHI = p(EnableCHI)
42  val enableL2 = coreParams.L2CacheParamsOpt.isDefined
43  // =========== Public Ports ============
44  val core_l3_pf_port = core.memBlock.l3_pf_sender_opt
45  val memory_port = if (enableCHI && enableL2) None else Some(l2top.memory_port.get)
46  val tl_uncache = l2top.mmio_port
47  // val axi4_uncache = if (enableCHI) Some(AXI4UserYanker()) else None
48  val beu_int_source = l2top.beu.intNode
49  val core_reset_sink = BundleBridgeSink(Some(() => Reset()))
50  val clint_int_node = l2top.clint_int_node
51  val plic_int_node = l2top.plic_int_node
52  val debug_int_node = l2top.debug_int_node
53  core.memBlock.clint_int_sink := clint_int_node
54  core.memBlock.plic_int_sink :*= plic_int_node
55  core.memBlock.debug_int_sink := debug_int_node
56
57  // =========== Components' Connection ============
58  // L1 to l1_xbar
59  coreParams.dcacheParametersOpt.map { _ =>
60    l2top.misc_l2_pmu := l2top.l1d_logger := core.memBlock.dcache_port :=
61      core.memBlock.l1d_to_l2_buffer.node := core.memBlock.dcache.clientNode
62  }
63
64  l2top.misc_l2_pmu := l2top.l1i_logger := core.memBlock.frontendBridge.icache_node
65  if (!coreParams.softPTW) {
66    l2top.misc_l2_pmu := l2top.ptw_logger := l2top.ptw_to_l2_buffer.node := core.memBlock.ptw_to_l2_buffer.node
67  }
68  l2top.l1_xbar :=* l2top.misc_l2_pmu
69
70  // TL2TL L2 Cache
71  val tl2tl_l2cache = l2top.tl2tl_l2cache
72  // l1_xbar to l2
73  tl2tl_l2cache match {
74    case Some(l2) =>
75      l2.node :*= l2top.xbar_l2_buffer :*= l2top.l1_xbar
76      l2.pf_recv_node.map(recv => {
77        println("Connecting L1 prefetcher to L2!")
78        recv := core.memBlock.l2_pf_sender_opt.get
79      })
80    case None =>
81  }
82
83  val core_l3_tpmeta_source_port = tl2tl_l2cache match {
84    case Some(l2) => l2.tpmeta_source_node
85    case None => None
86  }
87  val core_l3_tpmeta_sink_port = tl2tl_l2cache match {
88    case Some(l2) => l2.tpmeta_sink_node
89    case None => None
90  }
91
92  // TL2CHI L2 Cache
93  val tl2chi_l2cache = l2top.tl2chi_l2cache
94  tl2chi_l2cache match {
95    case Some(l2) =>
96      l2.pf_recv_node.map(recv => {
97        println("Connecting L1 prefetcher to L2!")
98        recv := core.memBlock.l2_pf_sender_opt.get
99      })
100    case None =>
101  }
102
103  // mmio
104  l2top.i_mmio_port := l2top.i_mmio_buffer.node := core.memBlock.frontendBridge.instr_uncache_node
105  l2top.d_mmio_port := core.memBlock.uncache.clientNode
106
107  // =========== IO Connection ============
108  class XSTileImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
109    val io = IO(new Bundle {
110      val hartId = Input(UInt(hartIdLen.W))
111      val reset_vector = Input(UInt(PAddrBits.W))
112      val cpu_halt = Output(Bool())
113      val debugTopDown = new Bundle {
114        val robHeadPaddr = Valid(UInt(PAddrBits.W))
115        val l3MissMatch = Input(Bool())
116      }
117      val chi = if (enableCHI) Some(new PortIO) else None
118      val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None
119    })
120
121    dontTouch(io.hartId)
122
123    val core_soft_rst = core_reset_sink.in.head._1 // unused
124
125    l2top.module.hartId.fromTile := io.hartId
126    core.module.io.hartId := l2top.module.hartId.toCore
127    core.module.io.reset_vector := l2top.module.reset_vector.toCore
128    l2top.module.reset_vector.fromTile := io.reset_vector
129    l2top.module.cpu_halt.fromCore := core.module.io.cpu_halt
130    io.cpu_halt := l2top.module.cpu_halt.toTile
131
132    core.module.io.perfEvents <> DontCare
133
134    l2top.module.beu_errors.icache <> core.module.io.beu_errors.icache
135    l2top.module.beu_errors.dcache <> core.module.io.beu_errors.dcache
136    if (enableL2) {
137      // TODO: add ECC interface of L2
138
139      l2top.module.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.beu_errors.l2)
140      core.module.io.l2_hint.bits.sourceId := l2top.module.l2_hint.bits.sourceId
141      core.module.io.l2_hint.bits.isKeyword := l2top.module.l2_hint.bits.isKeyword
142      core.module.io.l2_hint.valid := l2top.module.l2_hint.valid
143
144      core.module.io.l2PfqBusy := false.B
145      core.module.io.debugTopDown.l2MissMatch := l2top.module.debugTopDown.l2MissMatch
146      l2top.module.debugTopDown.robHeadPaddr := core.module.io.debugTopDown.robHeadPaddr
147      l2top.module.debugTopDown.robTrueCommit := core.module.io.debugTopDown.robTrueCommit
148      core.module.io.l2_tlb_req <> l2top.module.l2_tlb_req
149    } else {
150
151      l2top.module.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.beu_errors.l2)
152      core.module.io.l2_hint.bits.sourceId := l2top.module.l2_hint.bits.sourceId
153      core.module.io.l2_hint.bits.isKeyword := l2top.module.l2_hint.bits.isKeyword
154      core.module.io.l2_hint.valid := l2top.module.l2_hint.valid
155
156      core.module.io.l2PfqBusy := false.B
157      core.module.io.debugTopDown.l2MissMatch := false.B
158
159      core.module.io.l2_tlb_req.req.valid := false.B
160      core.module.io.l2_tlb_req.req.bits := DontCare
161      core.module.io.l2_tlb_req.req_kill := DontCare
162      core.module.io.l2_tlb_req.resp.ready := true.B
163    }
164
165    io.debugTopDown.robHeadPaddr := core.module.io.debugTopDown.robHeadPaddr
166    core.module.io.debugTopDown.l3MissMatch := io.debugTopDown.l3MissMatch
167
168    io.chi.foreach(_ <> l2top.module.chi.get)
169    l2top.module.nodeID.foreach(_ := io.nodeID.get)
170
171    // Modules are reset one by one
172    // io_reset ----
173    //             |
174    //             v
175    // reset ----> OR_SYNC --> {Misc, L2 Cache, Cores}
176    // val resetChain = Seq(
177    //   Seq(l2top.module, core.module)
178    // )
179    // ResetGen(resetChain, reset, !debugOpts.FPGAPlatform)
180  }
181
182  lazy val module = new XSTileImp(this)
183}
184