1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.backend.exu.Exu._ 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.backend.fu.HasExceptionNO 13import xiangshan.cache.{DCache, DCacheParameters, ICache, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, Uncache} 14import xiangshan.cache.prefetch._ 15import chipsalliance.rocketchip.config 16import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp} 17import freechips.rocketchip.tilelink.{TLBuffer, TLBundleParameters, TLCacheCork, TLClientNode, TLFilter, TLIdentityNode, TLToAXI4, TLWidthWidget, TLXbar} 18import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError} 19import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 20import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4IdentityNode, AXI4ToTL, AXI4UserYanker} 21import freechips.rocketchip.tile.HasFPUParameters 22import utils._ 23 24case class XSCoreParameters 25( 26 XLEN: Int = 64, 27 HasMExtension: Boolean = true, 28 HasCExtension: Boolean = true, 29 HasDiv: Boolean = true, 30 HasICache: Boolean = true, 31 HasDCache: Boolean = true, 32 EnableStoreQueue: Boolean = true, 33 AddrBits: Int = 64, 34 VAddrBits: Int = 39, 35 PAddrBits: Int = 40, 36 HasFPU: Boolean = true, 37 FectchWidth: Int = 8, 38 EnableBPU: Boolean = true, 39 EnableBPD: Boolean = true, 40 EnableRAS: Boolean = true, 41 EnableLB: Boolean = false, 42 EnableLoop: Boolean = true, 43 EnableSC: Boolean = false, 44 HistoryLength: Int = 64, 45 BtbSize: Int = 2048, 46 JbtacSize: Int = 1024, 47 JbtacBanks: Int = 8, 48 RasSize: Int = 16, 49 CacheLineSize: Int = 512, 50 UBtbWays: Int = 16, 51 BtbWays: Int = 2, 52 53 EnableL1plusPrefetcher: Boolean = true, 54 IBufSize: Int = 32, 55 DecodeWidth: Int = 6, 56 RenameWidth: Int = 6, 57 CommitWidth: Int = 6, 58 BrqSize: Int = 32, 59 IssQueSize: Int = 12, 60 NRPhyRegs: Int = 160, 61 NRIntReadPorts: Int = 14, 62 NRIntWritePorts: Int = 8, 63 NRFpReadPorts: Int = 14, 64 NRFpWritePorts: Int = 8, 65 LoadQueueSize: Int = 64, 66 StoreQueueSize: Int = 48, 67 RoqSize: Int = 192, 68 dpParams: DispatchParameters = DispatchParameters( 69 IntDqSize = 32, 70 FpDqSize = 32, 71 LsDqSize = 32, 72 IntDqDeqWidth = 4, 73 FpDqDeqWidth = 4, 74 LsDqDeqWidth = 4 75 ), 76 exuParameters: ExuParameters = ExuParameters( 77 JmpCnt = 1, 78 AluCnt = 4, 79 MulCnt = 0, 80 MduCnt = 2, 81 FmacCnt = 4, 82 FmiscCnt = 2, 83 FmiscDivSqrtCnt = 0, 84 LduCnt = 2, 85 StuCnt = 2 86 ), 87 LoadPipelineWidth: Int = 2, 88 StorePipelineWidth: Int = 2, 89 StoreBufferSize: Int = 16, 90 RefillSize: Int = 512, 91 TlbEntrySize: Int = 32, 92 TlbSPEntrySize: Int = 4, 93 TlbL2EntrySize: Int = 256, // or 512 94 TlbL2SPEntrySize: Int = 16, 95 PtwL1EntrySize: Int = 16, 96 PtwL2EntrySize: Int = 256, 97 NumPerfCounters: Int = 16, 98 NrExtIntr: Int = 1 99) 100 101trait HasXSParameter { 102 103 val core = Parameters.get.coreParameters 104 val env = Parameters.get.envParameters 105 106 val XLEN = 64 107 val minFLen = 32 108 val fLen = 64 109 def xLen = 64 110 val HasMExtension = core.HasMExtension 111 val HasCExtension = core.HasCExtension 112 val HasDiv = core.HasDiv 113 val HasIcache = core.HasICache 114 val HasDcache = core.HasDCache 115 val EnableStoreQueue = core.EnableStoreQueue 116 val AddrBits = core.AddrBits // AddrBits is used in some cases 117 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 118 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 119 val AddrBytes = AddrBits / 8 // unused 120 val DataBits = XLEN 121 val DataBytes = DataBits / 8 122 val HasFPU = core.HasFPU 123 val FetchWidth = core.FectchWidth 124 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 125 val EnableBPU = core.EnableBPU 126 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 127 val EnableRAS = core.EnableRAS 128 val EnableLB = core.EnableLB 129 val EnableLoop = core.EnableLoop 130 val EnableSC = core.EnableSC 131 val HistoryLength = core.HistoryLength 132 val BtbSize = core.BtbSize 133 // val BtbWays = 4 134 val BtbBanks = PredictWidth 135 // val BtbSets = BtbSize / BtbWays 136 val JbtacSize = core.JbtacSize 137 val JbtacBanks = core.JbtacBanks 138 val RasSize = core.RasSize 139 val CacheLineSize = core.CacheLineSize 140 val CacheLineHalfWord = CacheLineSize / 16 141 val ExtHistoryLength = HistoryLength + 64 142 val UBtbWays = core.UBtbWays 143 val BtbWays = core.BtbWays 144 val EnableL1plusPrefetcher = core.EnableL1plusPrefetcher 145 val IBufSize = core.IBufSize 146 val DecodeWidth = core.DecodeWidth 147 val RenameWidth = core.RenameWidth 148 val CommitWidth = core.CommitWidth 149 val BrqSize = core.BrqSize 150 val IssQueSize = core.IssQueSize 151 val BrTagWidth = log2Up(BrqSize) 152 val NRPhyRegs = core.NRPhyRegs 153 val PhyRegIdxWidth = log2Up(NRPhyRegs) 154 val RoqSize = core.RoqSize 155 val LoadQueueSize = core.LoadQueueSize 156 val StoreQueueSize = core.StoreQueueSize 157 val dpParams = core.dpParams 158 val exuParameters = core.exuParameters 159 val NRIntReadPorts = core.NRIntReadPorts 160 val NRIntWritePorts = core.NRIntWritePorts 161 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 162 val NRFpReadPorts = core.NRFpReadPorts 163 val NRFpWritePorts = core.NRFpWritePorts 164 val LoadPipelineWidth = core.LoadPipelineWidth 165 val StorePipelineWidth = core.StorePipelineWidth 166 val StoreBufferSize = core.StoreBufferSize 167 val RefillSize = core.RefillSize 168 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 169 val TlbEntrySize = core.TlbEntrySize 170 val TlbSPEntrySize = core.TlbSPEntrySize 171 val TlbL2EntrySize = core.TlbL2EntrySize 172 val TlbL2SPEntrySize = core.TlbL2SPEntrySize 173 val PtwL1EntrySize = core.PtwL1EntrySize 174 val PtwL2EntrySize = core.PtwL2EntrySize 175 val NumPerfCounters = core.NumPerfCounters 176 val NrExtIntr = core.NrExtIntr 177 178 val icacheParameters = ICacheParameters( 179 tagECC = Some("parity"), 180 dataECC = Some("parity"), 181 nMissEntries = 2 182 ) 183 184 val l1plusCacheParameters = L1plusCacheParameters( 185 tagECC = Some("secded"), 186 dataECC = Some("secded"), 187 nMissEntries = 8 188 ) 189 190 val dcacheParameters = DCacheParameters( 191 tagECC = Some("secded"), 192 dataECC = Some("secded"), 193 nMissEntries = 16, 194 nLoadMissEntries = 8, 195 nStoreMissEntries = 8 196 ) 197 198 val LRSCCycles = 100 199 200 201 // cache hierarchy configurations 202 val l1BusDataWidth = 256 203 204 // L2 configurations 205 val L1BusWidth = 256 206 val L2Size = 512 * 1024 // 512KB 207 val L2BlockSize = 64 208 val L2NWays = 8 209 val L2NSets = L2Size / L2BlockSize / L2NWays 210 211 // L3 configurations 212 val L2BusWidth = 256 213 val L3Size = 4 * 1024 * 1024 // 4MB 214 val L3BlockSize = 64 215 val L3NBanks = 4 216 val L3NWays = 8 217 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 218 219 // on chip network configurations 220 val L3BusWidth = 256 221 222 // icache prefetcher 223 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 224 enable = true, 225 _type = "stream", 226 streamParams = StreamPrefetchParameters( 227 streamCnt = 2, 228 streamSize = 4, 229 ageWidth = 4, 230 blockBytes = l1plusCacheParameters.blockBytes, 231 reallocStreamOnMissInstantly = true, 232 cacheName = "icache" 233 ) 234 ) 235 236 // dcache prefetcher 237 val l2PrefetcherParameters = L2PrefetcherParameters( 238 enable = true, 239 _type = "stream", 240 streamParams = StreamPrefetchParameters( 241 streamCnt = 4, 242 streamSize = 4, 243 ageWidth = 4, 244 blockBytes = L2BlockSize, 245 reallocStreamOnMissInstantly = true, 246 cacheName = "dcache" 247 ) 248 ) 249} 250 251trait HasXSLog { this: RawModule => 252 implicit val moduleName: String = this.name 253} 254 255abstract class XSModule extends MultiIOModule 256 with HasXSParameter 257 with HasExceptionNO 258 with HasXSLog 259 with HasFPUParameters 260{ 261 def io: Record 262} 263 264//remove this trait after impl module logic 265trait NeedImpl { this: RawModule => 266 override protected def IO[T <: Data](iodef: T): T = { 267 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 268 val io = chisel3.experimental.IO(iodef) 269 io <> DontCare 270 io 271 } 272} 273 274abstract class XSBundle extends Bundle 275 with HasXSParameter 276 277case class EnviromentParameters 278( 279 FPGAPlatform: Boolean = true, 280 EnableDebug: Boolean = false 281) 282 283// object AddressSpace extends HasXSParameter { 284// // (start, size) 285// // address out of MMIO will be considered as DRAM 286// def mmio = List( 287// (0x00000000L, 0x40000000L), // internal devices, such as CLINT and PLIC 288// (0x40000000L, 0x40000000L) // external devices 289// ) 290 291// def isMMIO(addr: UInt): Bool = mmio.map(range => { 292// require(isPow2(range._2)) 293// val bits = log2Up(range._2) 294// (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 295// }).reduce(_ || _) 296// } 297 298 299 300class XSCore()(implicit p: config.Parameters) extends LazyModule 301 with HasXSParameter 302 with HasExeBlockHelper 303{ 304 305 // to fast wake up fp, mem rs 306 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 307 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 308 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 309 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 310 311 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 312 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 313 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 314 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 315 316 // outer facing nodes 317 val l1pluscache = LazyModule(new L1plusCache()) 318 val ptw = LazyModule(new PTW()) 319 val l2Prefetcher = LazyModule(new L2Prefetcher()) 320 val memBlock = LazyModule(new MemBlock( 321 fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp, 322 slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp, 323 fastFpOut = Seq(), 324 slowFpOut = loadExuConfigs, 325 fastIntOut = Seq(), 326 slowIntOut = loadExuConfigs 327 )) 328 329 lazy val module = new XSCoreImp(this) 330} 331 332class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 333 with HasXSParameter 334 with HasExeBlockHelper 335{ 336 val io = IO(new Bundle { 337 val externalInterrupt = new ExternalInterruptIO 338 }) 339 340 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 341 AddressSpace.printMemmap() 342 343 // to fast wake up fp, mem rs 344 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 345 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 346 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 347 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 348 349 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 350 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 351 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 352 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 353 354 val frontend = Module(new Frontend) 355 val ctrlBlock = Module(new CtrlBlock) 356 val integerBlock = Module(new IntegerBlock( 357 fastWakeUpIn = fpBlockFastWakeUpInt, 358 slowWakeUpIn = fpBlockSlowWakeUpInt ++ loadExuConfigs, 359 fastFpOut = intBlockFastWakeUpFp, 360 slowFpOut = intBlockSlowWakeUpFp, 361 fastIntOut = intBlockFastWakeUpInt, 362 slowIntOut = intBlockSlowWakeUpInt 363 )) 364 val floatBlock = Module(new FloatBlock( 365 fastWakeUpIn = intBlockFastWakeUpFp, 366 slowWakeUpIn = intBlockSlowWakeUpFp ++ loadExuConfigs, 367 fastFpOut = fpBlockFastWakeUpFp, 368 slowFpOut = fpBlockSlowWakeUpFp, 369 fastIntOut = fpBlockFastWakeUpInt, 370 slowIntOut = fpBlockSlowWakeUpInt 371 )) 372 373 val memBlock = outer.memBlock.module 374 val l1pluscache = outer.l1pluscache.module 375 val ptw = outer.ptw.module 376 val l2Prefetcher = outer.l2Prefetcher.module 377 378 frontend.io.backend <> ctrlBlock.io.frontend 379 frontend.io.sfence <> integerBlock.io.fenceio.sfence 380 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 381 382 frontend.io.icacheMemAcq <> l1pluscache.io.req 383 l1pluscache.io.resp <> frontend.io.icacheMemGrant 384 l1pluscache.io.flush := frontend.io.l1plusFlush 385 frontend.io.fencei := integerBlock.io.fenceio.fencei 386 387 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 388 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 389 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 390 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 391 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 392 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 393 394 integerBlock.io.wakeUpIn.fastUops <> floatBlock.io.wakeUpIntOut.fastUops 395 integerBlock.io.wakeUpIn.fast <> floatBlock.io.wakeUpIntOut.fast 396 integerBlock.io.wakeUpIn.slow <> floatBlock.io.wakeUpIntOut.slow ++ memBlock.io.wakeUpIntOut.slow 397 integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock 398 399 floatBlock.io.wakeUpIn.fastUops <> integerBlock.io.wakeUpFpOut.fastUops 400 floatBlock.io.wakeUpIn.fast <> integerBlock.io.wakeUpFpOut.fast 401 floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlock.io.wakeUpFpOut.slow 402 floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock 403 404 405 integerBlock.io.wakeUpIntOut.fast.map(_.ready := true.B) 406 integerBlock.io.wakeUpIntOut.slow.map(_.ready := true.B) 407 floatBlock.io.wakeUpFpOut.fast.map(_.ready := true.B) 408 floatBlock.io.wakeUpFpOut.slow.map(_.ready := true.B) 409 410 val wakeUpMem = Seq( 411 integerBlock.io.wakeUpIntOut, 412 integerBlock.io.wakeUpFpOut, 413 floatBlock.io.wakeUpIntOut, 414 floatBlock.io.wakeUpFpOut 415 ) 416 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 417 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(w => w.fast.map(f => { 418 val raw = WireInit(f) 419 raw 420 })) 421 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(w => w.slow.map(s => { 422 val raw = WireInit(s) 423 raw 424 })) 425 426 integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags 427 integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 428 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 429 integerBlock.io.csrio.isInterrupt <> ctrlBlock.io.roqio.isInterrupt 430 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 431 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 432 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 433 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 434 integerBlock.io.csrio.tlb <> memBlock.io.tlbCsr 435 integerBlock.io.csrio.perfinfo <> ctrlBlock.io.roqio.toCSR.perfinfo 436 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 437 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 438 439 floatBlock.io.frm <> integerBlock.io.csrio.frm 440 441 memBlock.io.lsqio.commits <> ctrlBlock.io.roqio.commits 442 memBlock.io.lsqio.roqDeqPtr <> ctrlBlock.io.roqio.roqDeqPtr 443 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.lqIdx 444 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.sqIdx 445 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.ctrl.commitType) 446 447 ptw.io.tlb(0) <> memBlock.io.ptw 448 ptw.io.tlb(1) <> frontend.io.ptw 449 ptw.io.sfence <> integerBlock.io.fenceio.sfence 450 ptw.io.csr <> integerBlock.io.csrio.tlb 451 452 l2Prefetcher.io.in <> memBlock.io.toDCachePrefetch 453 454 if (!env.FPGAPlatform) { 455 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 456 ExcitingUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG", ExcitingUtils.Debug) 457 ExcitingUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG", ExcitingUtils.Debug) 458 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 459 ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug) 460 } 461 462} 463