1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import device.MsiInfoBundle 24import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp} 25import freechips.rocketchip.tile.HasFPUParameters 26import system.HasSoCParameter 27import utils._ 28import utility._ 29import xiangshan.backend._ 30import xiangshan.backend.fu.PMPRespBundle 31import xiangshan.backend.trace.TraceCoreInterface 32import xiangshan.cache.mmu._ 33import xiangshan.frontend._ 34import scala.collection.mutable.ListBuffer 35import xiangshan.cache.mmu.TlbRequestIO 36 37abstract class XSModule(implicit val p: Parameters) extends Module 38 with HasXSParameter 39 with HasFPUParameters 40 41//remove this trait after impl module logic 42trait NeedImpl { 43 this: RawModule => 44 protected def IO[T <: Data](iodef: T): T = { 45 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 46 val io = chisel3.IO(iodef) 47 io <> DontCare 48 io 49 } 50} 51 52abstract class XSBundle(implicit val p: Parameters) extends Bundle 53 with HasXSParameter 54 55abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 56 with HasXSParameter 57{ 58 override def shouldBeInlined: Boolean = false 59 // outer facing nodes 60 val frontend = LazyModule(new Frontend()) 61 val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO())) 62 val backend = LazyModule(new Backend(backendParams)) 63 64 val memBlock = LazyModule(new MemBlock) 65 66 memBlock.inner.frontendBridge.icache_node := frontend.inner.icache.clientNode 67 memBlock.inner.frontendBridge.instr_uncache_node := frontend.inner.instrUncache.clientNode 68 if (icacheParameters.cacheCtrlAddressOpt.nonEmpty) { 69 frontend.inner.icache.ctrlUnitOpt.get.node := memBlock.inner.frontendBridge.icachectrl_node 70 } 71} 72 73class XSCore()(implicit p: config.Parameters) extends XSCoreBase 74 with HasXSDts 75{ 76 lazy val module = new XSCoreImp(this) 77} 78 79class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 80 with HasXSParameter 81 with HasSoCParameter { 82 val io = IO(new Bundle { 83 val hartId = Input(UInt(hartIdLen.W)) 84 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 85 val clintTime = Input(ValidIO(UInt(64.W))) 86 val reset_vector = Input(UInt(PAddrBits.W)) 87 val cpu_halt = Output(Bool()) 88 val l2_flush_done = Input(Bool()) 89 val l2_flush_en = Output(Bool()) 90 val power_down_en = Output(Bool()) 91 val cpu_critical_error = Output(Bool()) 92 val resetInFrontend = Output(Bool()) 93 val traceCoreInterface = new TraceCoreInterface 94 val l2_pf_enable = Output(Bool()) 95 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent)) 96 val beu_errors = Output(new XSL1BusErrors()) 97 val l2_hint = Input(Valid(new L2ToL1Hint())) 98 val l2_tlb_req = Flipped(new TlbRequestIO(nRespDups = 2)) 99 val l2_pmp_resp = new PMPRespBundle 100 val l2PfqBusy = Input(Bool()) 101 val debugTopDown = new Bundle { 102 val robTrueCommit = Output(UInt(64.W)) 103 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 104 val l2MissMatch = Input(Bool()) 105 val l3MissMatch = Input(Bool()) 106 } 107 val topDownInfo = Input(new Bundle { 108 val l2Miss = Bool() 109 val l3Miss = Bool() 110 }) 111 }) 112 113 dontTouch(io.l2_flush_done) 114 dontTouch(io.l2_flush_en) 115 dontTouch(io.power_down_en) 116 117 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 118 119 val frontend = outer.frontend.module 120 val backend = outer.backend.module 121 val memBlock = outer.memBlock.module 122 123 frontend.io.hartId := memBlock.io.inner_hartId 124 frontend.io.reset_vector := memBlock.io.inner_reset_vector 125 frontend.io.softPrefetch <> memBlock.io.ifetchPrefetch 126 frontend.io.backend <> backend.io.frontend 127 frontend.io.sfence <> backend.io.frontendSfence 128 frontend.io.tlbCsr <> backend.io.frontendTlbCsr 129 frontend.io.csrCtrl <> backend.io.frontendCsrCtrl 130 frontend.io.fencei <> backend.io.fenceio.fencei 131 132 backend.io.fromTop := memBlock.io.mem_to_ooo.topToBackendBypass 133 134 require(backend.io.mem.stIn.length == memBlock.io.mem_to_ooo.stIn.length) 135 backend.io.mem.stIn.zip(memBlock.io.mem_to_ooo.stIn).foreach { case (sink, source) => 136 sink.valid := source.valid 137 sink.bits := 0.U.asTypeOf(sink.bits) 138 sink.bits.robIdx := source.bits.uop.robIdx 139 sink.bits.ssid := source.bits.uop.ssid 140 sink.bits.storeSetHit := source.bits.uop.storeSetHit 141 // The other signals have not been used 142 } 143 backend.io.mem.memoryViolation := memBlock.io.mem_to_ooo.memoryViolation 144 backend.io.mem.lsqEnqIO <> memBlock.io.ooo_to_mem.enqLsq 145 backend.io.mem.sqDeq := memBlock.io.mem_to_ooo.sqDeq 146 backend.io.mem.lqDeq := memBlock.io.mem_to_ooo.lqDeq 147 backend.io.mem.sqDeqPtr := memBlock.io.mem_to_ooo.sqDeqPtr 148 backend.io.mem.lqDeqPtr := memBlock.io.mem_to_ooo.lqDeqPtr 149 backend.io.mem.lqCancelCnt := memBlock.io.mem_to_ooo.lqCancelCnt 150 backend.io.mem.sqCancelCnt := memBlock.io.mem_to_ooo.sqCancelCnt 151 backend.io.mem.otherFastWakeup := memBlock.io.mem_to_ooo.otherFastWakeup 152 backend.io.mem.stIssuePtr := memBlock.io.mem_to_ooo.stIssuePtr 153 backend.io.mem.ldaIqFeedback := memBlock.io.mem_to_ooo.ldaIqFeedback 154 backend.io.mem.staIqFeedback := memBlock.io.mem_to_ooo.staIqFeedback 155 backend.io.mem.hyuIqFeedback := memBlock.io.mem_to_ooo.hyuIqFeedback 156 backend.io.mem.vstuIqFeedback := memBlock.io.mem_to_ooo.vstuIqFeedback 157 backend.io.mem.vlduIqFeedback := memBlock.io.mem_to_ooo.vlduIqFeedback 158 backend.io.mem.ldCancel := memBlock.io.mem_to_ooo.ldCancel 159 backend.io.mem.wakeup := memBlock.io.mem_to_ooo.wakeup 160 backend.io.mem.writebackLda <> memBlock.io.mem_to_ooo.writebackLda 161 backend.io.mem.writebackSta <> memBlock.io.mem_to_ooo.writebackSta 162 backend.io.mem.writebackHyuLda <> memBlock.io.mem_to_ooo.writebackHyuLda 163 backend.io.mem.writebackHyuSta <> memBlock.io.mem_to_ooo.writebackHyuSta 164 backend.io.mem.writebackStd <> memBlock.io.mem_to_ooo.writebackStd 165 backend.io.mem.writebackVldu <> memBlock.io.mem_to_ooo.writebackVldu 166 backend.io.mem.robLsqIO.mmio := memBlock.io.mem_to_ooo.lsqio.mmio 167 backend.io.mem.robLsqIO.uop := memBlock.io.mem_to_ooo.lsqio.uop 168 169 // memblock error exception writeback, 1 cycle after normal writeback 170 backend.io.mem.s3_delayed_load_error := memBlock.io.mem_to_ooo.s3_delayed_load_error 171 172 backend.io.mem.exceptionAddr.vaddr := memBlock.io.mem_to_ooo.lsqio.vaddr 173 backend.io.mem.exceptionAddr.gpaddr := memBlock.io.mem_to_ooo.lsqio.gpaddr 174 backend.io.mem.exceptionAddr.isForVSnonLeafPTE := memBlock.io.mem_to_ooo.lsqio.isForVSnonLeafPTE 175 backend.io.mem.debugLS := memBlock.io.debug_ls 176 backend.io.mem.lsTopdownInfo := memBlock.io.mem_to_ooo.lsTopdownInfo 177 backend.io.mem.lqCanAccept := memBlock.io.mem_to_ooo.lsqio.lqCanAccept 178 backend.io.mem.sqCanAccept := memBlock.io.mem_to_ooo.lsqio.sqCanAccept 179 backend.io.fenceio.sbuffer.sbIsEmpty := memBlock.io.mem_to_ooo.sbIsEmpty 180 181 backend.io.perf.frontendInfo := frontend.io.frontendInfo 182 backend.io.perf.memInfo := memBlock.io.memInfo 183 backend.io.perf.perfEventsFrontend := frontend.io_perf 184 backend.io.perf.perfEventsLsu := memBlock.io_perf 185 backend.io.perf.perfEventsHc := memBlock.io.inner_hc_perfEvents 186 backend.io.perf.perfEventsBackend := DontCare 187 backend.io.perf.retiredInstr := DontCare 188 backend.io.perf.ctrlInfo := DontCare 189 190 backend.io.mem.storeDebugInfo <> memBlock.io.mem_to_ooo.storeDebugInfo 191 192 // top -> memBlock 193 memBlock.io.fromTopToBackend.clintTime := io.clintTime 194 memBlock.io.fromTopToBackend.msiInfo := io.msiInfo 195 memBlock.io.hartId := io.hartId 196 memBlock.io.l2_flush_done := io.l2_flush_done 197 memBlock.io.outer_reset_vector := io.reset_vector 198 memBlock.io.outer_hc_perfEvents := io.perfEvents 199 // frontend -> memBlock 200 memBlock.io.inner_beu_errors_icache <> frontend.io.error.bits.toL1BusErrorUnitInfo(frontend.io.error.valid) 201 memBlock.io.inner_l2_pf_enable := backend.io.csrCustomCtrl.l2_pf_enable 202 memBlock.io.ooo_to_mem.backendToTopBypass := backend.io.toTop 203 memBlock.io.ooo_to_mem.issueLda <> backend.io.mem.issueLda 204 memBlock.io.ooo_to_mem.issueSta <> backend.io.mem.issueSta 205 memBlock.io.ooo_to_mem.issueStd <> backend.io.mem.issueStd 206 memBlock.io.ooo_to_mem.issueHya <> backend.io.mem.issueHylda 207 backend.io.mem.issueHysta.foreach(_.ready := false.B) // this fake port should not be used 208 memBlock.io.ooo_to_mem.issueVldu <> backend.io.mem.issueVldu 209 210 // By default, instructions do not have exceptions when they enter the function units. 211 memBlock.io.ooo_to_mem.issueUops.map(_.bits.uop.clearExceptions()) 212 memBlock.io.ooo_to_mem.storePc := backend.io.mem.storePcRead 213 memBlock.io.ooo_to_mem.hybridPc := backend.io.mem.hyuPcRead 214 memBlock.io.ooo_to_mem.flushSb := backend.io.fenceio.sbuffer.flushSb 215 memBlock.io.ooo_to_mem.loadFastMatch := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastMatch) 216 memBlock.io.ooo_to_mem.loadFastImm := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastImm) 217 memBlock.io.ooo_to_mem.loadFastFuOpType := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastFuOpType) 218 219 memBlock.io.ooo_to_mem.sfence <> backend.io.mem.sfence 220 221 memBlock.io.redirect := backend.io.mem.redirect 222 memBlock.io.ooo_to_mem.csrCtrl := backend.io.mem.csrCtrl 223 memBlock.io.ooo_to_mem.tlbCsr := backend.io.mem.tlbCsr 224 memBlock.io.ooo_to_mem.lsqio.lcommit := backend.io.mem.robLsqIO.lcommit 225 memBlock.io.ooo_to_mem.lsqio.scommit := backend.io.mem.robLsqIO.scommit 226 memBlock.io.ooo_to_mem.lsqio.pendingMMIOld := backend.io.mem.robLsqIO.pendingMMIOld 227 memBlock.io.ooo_to_mem.lsqio.pendingld := backend.io.mem.robLsqIO.pendingld 228 memBlock.io.ooo_to_mem.lsqio.pendingst := backend.io.mem.robLsqIO.pendingst 229 memBlock.io.ooo_to_mem.lsqio.pendingVst := backend.io.mem.robLsqIO.pendingVst 230 memBlock.io.ooo_to_mem.lsqio.commit := backend.io.mem.robLsqIO.commit 231 memBlock.io.ooo_to_mem.lsqio.pendingPtr := backend.io.mem.robLsqIO.pendingPtr 232 memBlock.io.ooo_to_mem.lsqio.pendingPtrNext := backend.io.mem.robLsqIO.pendingPtrNext 233 memBlock.io.ooo_to_mem.isStoreException := backend.io.mem.isStoreException 234 memBlock.io.ooo_to_mem.isVlsException := backend.io.mem.isVlsException 235 236 memBlock.io.fetch_to_mem.itlb <> frontend.io.ptw 237 memBlock.io.l2_hint.valid := io.l2_hint.valid 238 memBlock.io.l2_hint.bits.sourceId := io.l2_hint.bits.sourceId 239 memBlock.io.l2_tlb_req <> io.l2_tlb_req 240 memBlock.io.l2_pmp_resp <> io.l2_pmp_resp 241 memBlock.io.l2_hint.bits.isKeyword := io.l2_hint.bits.isKeyword 242 memBlock.io.l2PfqBusy := io.l2PfqBusy 243 244 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 245 246 // top-down info 247 memBlock.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 248 frontend.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 249 io.debugTopDown.robHeadPaddr := backend.io.debugTopDown.fromRob.robHeadPaddr 250 io.debugTopDown.robTrueCommit := backend.io.debugRolling.robTrueCommit 251 backend.io.debugTopDown.fromCore.l2MissMatch := io.debugTopDown.l2MissMatch 252 backend.io.debugTopDown.fromCore.l3MissMatch := io.debugTopDown.l3MissMatch 253 backend.io.debugTopDown.fromCore.fromMem := memBlock.io.debugTopDown.toCore 254 memBlock.io.debugRolling := backend.io.debugRolling 255 256 io.cpu_halt := memBlock.io.outer_cpu_halt 257 io.l2_flush_en := memBlock.io.outer_l2_flush_en 258 io.power_down_en := memBlock.io.outer_power_down_en 259 io.cpu_critical_error := memBlock.io.outer_cpu_critical_error 260 io.beu_errors.icache <> memBlock.io.outer_beu_errors_icache 261 io.beu_errors.dcache <> memBlock.io.error.bits.toL1BusErrorUnitInfo(memBlock.io.error.valid) 262 io.beu_errors.l2 <> DontCare 263 io.l2_pf_enable := memBlock.io.outer_l2_pf_enable 264 265 memBlock.io.resetInFrontendBypass.fromFrontend := frontend.io.resetInFrontend 266 io.resetInFrontend := memBlock.io.resetInFrontendBypass.toL2Top 267 memBlock.io.traceCoreInterfaceBypass.fromBackend <> backend.io.traceCoreInterface 268 io.traceCoreInterface <> memBlock.io.traceCoreInterfaceBypass.toL2Top 269 memBlock.io.topDownInfo.fromL2Top.l2Miss := io.topDownInfo.l2Miss 270 memBlock.io.topDownInfo.fromL2Top.l3Miss := io.topDownInfo.l3Miss 271 memBlock.io.topDownInfo.toBackend.noUopsIssued := backend.io.topDownInfo.noUopsIssued 272 backend.io.topDownInfo.lqEmpty := memBlock.io.topDownInfo.toBackend.lqEmpty 273 backend.io.topDownInfo.sqEmpty := memBlock.io.topDownInfo.toBackend.sqEmpty 274 backend.io.topDownInfo.l1Miss := memBlock.io.topDownInfo.toBackend.l1Miss 275 backend.io.topDownInfo.l2TopMiss.l2Miss := memBlock.io.topDownInfo.toBackend.l2TopMiss.l2Miss 276 backend.io.topDownInfo.l2TopMiss.l3Miss := memBlock.io.topDownInfo.toBackend.l2TopMiss.l3Miss 277 278 279 if (debugOpts.ResetGen) { 280 backend.reset := memBlock.io.reset_backend 281 frontend.reset := backend.io.frontendReset 282 } 283} 284