1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.backend.exu.Exu._ 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.backend.fu.HasExceptionNO 13import xiangshan.cache.{ICache, DCache, L1plusCache, DCacheParameters, ICacheParameters, L1plusCacheParameters, PTW, Uncache} 14import chipsalliance.rocketchip.config 15import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, AddressSet} 16import freechips.rocketchip.tilelink.{TLBundleParameters, TLCacheCork, TLBuffer, TLClientNode, TLIdentityNode, TLXbar, TLWidthWidget, TLFilter, TLToAXI4} 17import freechips.rocketchip.devices.tilelink.{TLError, DevNullParams} 18import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 19import freechips.rocketchip.amba.axi4.{AXI4ToTL, AXI4IdentityNode, AXI4UserYanker, AXI4Fragmenter, AXI4IdIndexer, AXI4Deinterleaver} 20import utils._ 21 22case class XSCoreParameters 23( 24 XLEN: Int = 64, 25 HasMExtension: Boolean = true, 26 HasCExtension: Boolean = true, 27 HasDiv: Boolean = true, 28 HasICache: Boolean = true, 29 HasDCache: Boolean = true, 30 EnableStoreQueue: Boolean = true, 31 AddrBits: Int = 64, 32 VAddrBits: Int = 39, 33 PAddrBits: Int = 40, 34 HasFPU: Boolean = true, 35 FectchWidth: Int = 8, 36 EnableBPU: Boolean = true, 37 EnableBPD: Boolean = true, 38 EnableRAS: Boolean = true, 39 EnableLB: Boolean = false, 40 EnableLoop: Boolean = false, 41 EnableSC: Boolean = false, 42 HistoryLength: Int = 64, 43 BtbSize: Int = 2048, 44 JbtacSize: Int = 1024, 45 JbtacBanks: Int = 8, 46 RasSize: Int = 16, 47 CacheLineSize: Int = 512, 48 UBtbWays: Int = 16, 49 BtbWays: Int = 2, 50 IBufSize: Int = 64, 51 DecodeWidth: Int = 6, 52 RenameWidth: Int = 6, 53 CommitWidth: Int = 6, 54 BrqSize: Int = 32, 55 IssQueSize: Int = 12, 56 NRPhyRegs: Int = 160, 57 NRIntReadPorts: Int = 14, 58 NRIntWritePorts: Int = 8, 59 NRFpReadPorts: Int = 14, 60 NRFpWritePorts: Int = 8, 61 LoadQueueSize: Int = 64, 62 StoreQueueSize: Int = 48, 63 RoqSize: Int = 192, 64 dpParams: DispatchParameters = DispatchParameters( 65 IntDqSize = 24, 66 FpDqSize = 24, 67 LsDqSize = 24, 68 IntDqDeqWidth = 4, 69 FpDqDeqWidth = 4, 70 LsDqDeqWidth = 4 71 ), 72 exuParameters: ExuParameters = ExuParameters( 73 JmpCnt = 1, 74 AluCnt = 4, 75 MulCnt = 0, 76 MduCnt = 2, 77 FmacCnt = 4, 78 FmiscCnt = 2, 79 FmiscDivSqrtCnt = 0, 80 LduCnt = 2, 81 StuCnt = 2 82 ), 83 LoadPipelineWidth: Int = 2, 84 StorePipelineWidth: Int = 2, 85 StoreBufferSize: Int = 16, 86 RefillSize: Int = 512, 87 TlbEntrySize: Int = 32, 88 TlbL2EntrySize: Int = 256, // or 512 89 PtwL1EntrySize: Int = 16, 90 PtwL2EntrySize: Int = 256, 91 NumPerfCounters: Int = 16 92) 93 94trait HasXSParameter { 95 96 val core = Parameters.get.coreParameters 97 val env = Parameters.get.envParameters 98 99 val XLEN = core.XLEN 100 val HasMExtension = core.HasMExtension 101 val HasCExtension = core.HasCExtension 102 val HasDiv = core.HasDiv 103 val HasIcache = core.HasICache 104 val HasDcache = core.HasDCache 105 val EnableStoreQueue = core.EnableStoreQueue 106 val AddrBits = core.AddrBits // AddrBits is used in some cases 107 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 108 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 109 val AddrBytes = AddrBits / 8 // unused 110 val DataBits = XLEN 111 val DataBytes = DataBits / 8 112 val HasFPU = core.HasFPU 113 val FetchWidth = core.FectchWidth 114 val PredictWidth = FetchWidth * 2 115 val EnableBPU = core.EnableBPU 116 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 117 val EnableRAS = core.EnableRAS 118 val EnableLB = core.EnableLB 119 val EnableLoop = core.EnableLoop 120 val EnableSC = core.EnableSC 121 val HistoryLength = core.HistoryLength 122 val BtbSize = core.BtbSize 123 // val BtbWays = 4 124 val BtbBanks = PredictWidth 125 // val BtbSets = BtbSize / BtbWays 126 val JbtacSize = core.JbtacSize 127 val JbtacBanks = core.JbtacBanks 128 val RasSize = core.RasSize 129 val CacheLineSize = core.CacheLineSize 130 val CacheLineHalfWord = CacheLineSize / 16 131 val ExtHistoryLength = HistoryLength + 64 132 val UBtbWays = core.UBtbWays 133 val BtbWays = core.BtbWays 134 val IBufSize = core.IBufSize 135 val DecodeWidth = core.DecodeWidth 136 val RenameWidth = core.RenameWidth 137 val CommitWidth = core.CommitWidth 138 val BrqSize = core.BrqSize 139 val IssQueSize = core.IssQueSize 140 val BrTagWidth = log2Up(BrqSize) 141 val NRPhyRegs = core.NRPhyRegs 142 val PhyRegIdxWidth = log2Up(NRPhyRegs) 143 val RoqSize = core.RoqSize 144 val LoadQueueSize = core.LoadQueueSize 145 val StoreQueueSize = core.StoreQueueSize 146 val dpParams = core.dpParams 147 val exuParameters = core.exuParameters 148 val NRIntReadPorts = core.NRIntReadPorts 149 val NRIntWritePorts = core.NRIntWritePorts 150 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 151 val NRFpReadPorts = core.NRFpReadPorts 152 val NRFpWritePorts = core.NRFpWritePorts 153 val LoadPipelineWidth = core.LoadPipelineWidth 154 val StorePipelineWidth = core.StorePipelineWidth 155 val StoreBufferSize = core.StoreBufferSize 156 val RefillSize = core.RefillSize 157 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 158 val TlbEntrySize = core.TlbEntrySize 159 val TlbL2EntrySize = core.TlbL2EntrySize 160 val PtwL1EntrySize = core.PtwL1EntrySize 161 val PtwL2EntrySize = core.PtwL2EntrySize 162 val NumPerfCounters = core.NumPerfCounters 163 164 val icacheParameters = ICacheParameters( 165 nMissEntries = 2 166 ) 167 168 val l1plusCacheParameters = L1plusCacheParameters( 169 tagECC = Some("secded"), 170 dataECC = Some("secded"), 171 nMissEntries = 8 172 ) 173 174 val dcacheParameters = DCacheParameters( 175 tagECC = Some("secded"), 176 dataECC = Some("secded"), 177 nMissEntries = 16, 178 nLoadMissEntries = 8, 179 nStoreMissEntries = 8 180 ) 181 182 val LRSCCycles = 100 183 184 185 // cache hierarchy configurations 186 val l1BusDataWidth = 256 187 188 // L2 configurations 189 val L1BusWidth = 256 190 val L2Size = 512 * 1024 // 512KB 191 val L2BlockSize = 64 192 val L2NWays = 8 193 val L2NSets = L2Size / L2BlockSize / L2NWays 194 195 // L3 configurations 196 val L2BusWidth = 256 197 val L3Size = 4 * 1024 * 1024 // 4MB 198 val L3BlockSize = 64 199 val L3NBanks = 4 200 val L3NWays = 8 201 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 202 203 // on chip network configurations 204 val L3BusWidth = 256 205} 206 207trait HasXSLog { this: RawModule => 208 implicit val moduleName: String = this.name 209} 210 211abstract class XSModule extends MultiIOModule 212 with HasXSParameter 213 with HasExceptionNO 214 with HasXSLog 215{ 216 def io: Record 217} 218 219//remove this trait after impl module logic 220trait NeedImpl { this: RawModule => 221 override protected def IO[T <: Data](iodef: T): T = { 222 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 223 val io = chisel3.experimental.IO(iodef) 224 io <> DontCare 225 io 226 } 227} 228 229abstract class XSBundle extends Bundle 230 with HasXSParameter 231 232case class EnviromentParameters 233( 234 FPGAPlatform: Boolean = true, 235 EnableDebug: Boolean = false 236) 237 238object AddressSpace extends HasXSParameter { 239 // (start, size) 240 // address out of MMIO will be considered as DRAM 241 def mmio = List( 242 (0x00000000L, 0x40000000L), // internal devices, such as CLINT and PLIC 243 (0x40000000L, 0x40000000L) // external devices 244 ) 245 246 def isMMIO(addr: UInt): Bool = mmio.map(range => { 247 require(isPow2(range._2)) 248 val bits = log2Up(range._2) 249 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 250 }).reduce(_ || _) 251} 252 253 254 255class XSCore()(implicit p: config.Parameters) extends LazyModule with HasXSParameter { 256 257 // outer facing nodes 258 val dcache = LazyModule(new DCache()) 259 val uncache = LazyModule(new Uncache()) 260 val l1pluscache = LazyModule(new L1plusCache()) 261 val ptw = LazyModule(new PTW()) 262 263 lazy val module = new XSCoreImp(this) 264} 265 266class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 267 with HasXSParameter 268 with HasExeBlockHelper 269{ 270 val io = IO(new Bundle { 271 val externalInterrupt = new ExternalInterruptIO 272 }) 273 274 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 275 276 // to fast wake up fp, mem rs 277 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 278 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 279 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 280 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 281 282 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 283 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 284 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 285 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 286 287 val frontend = Module(new Frontend) 288 val ctrlBlock = Module(new CtrlBlock) 289 val integerBlock = Module(new IntegerBlock( 290 fastWakeUpIn = fpBlockFastWakeUpInt, 291 slowWakeUpIn = fpBlockSlowWakeUpInt ++ loadExuConfigs, 292 fastFpOut = intBlockFastWakeUpFp, 293 slowFpOut = intBlockSlowWakeUpFp, 294 fastIntOut = intBlockFastWakeUpInt, 295 slowIntOut = intBlockSlowWakeUpInt 296 )) 297 val floatBlock = Module(new FloatBlock( 298 fastWakeUpIn = intBlockFastWakeUpFp, 299 slowWakeUpIn = intBlockSlowWakeUpFp ++ loadExuConfigs, 300 fastFpOut = fpBlockFastWakeUpFp, 301 slowFpOut = fpBlockSlowWakeUpFp, 302 fastIntOut = fpBlockFastWakeUpInt, 303 slowIntOut = fpBlockSlowWakeUpInt 304 )) 305 val memBlock = Module(new MemBlock( 306 fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp, 307 slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp, 308 fastFpOut = Seq(), 309 slowFpOut = loadExuConfigs, 310 fastIntOut = Seq(), 311 slowIntOut = loadExuConfigs 312 )) 313 314 val dcache = outer.dcache.module 315 val uncache = outer.uncache.module 316 val l1pluscache = outer.l1pluscache.module 317 val ptw = outer.ptw.module 318 319 320 frontend.io.backend <> ctrlBlock.io.frontend 321 frontend.io.sfence <> integerBlock.io.fenceio.sfence 322 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 323 324 frontend.io.icacheMemAcq <> l1pluscache.io.req 325 l1pluscache.io.resp <> frontend.io.icacheMemGrant 326 l1pluscache.io.flush := frontend.io.l1plusFlush 327 frontend.io.fencei := integerBlock.io.fenceio.fencei 328 329 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 330 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 331 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 332 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 333 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 334 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 335 336 integerBlock.io.wakeUpIn.fastUops <> floatBlock.io.wakeUpIntOut.fastUops 337 integerBlock.io.wakeUpIn.fast <> floatBlock.io.wakeUpIntOut.fast 338 integerBlock.io.wakeUpIn.slow <> floatBlock.io.wakeUpIntOut.slow ++ memBlock.io.wakeUpIntOut.slow 339 340 floatBlock.io.wakeUpIn.fastUops <> integerBlock.io.wakeUpFpOut.fastUops 341 floatBlock.io.wakeUpIn.fast <> integerBlock.io.wakeUpFpOut.fast 342 floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlock.io.wakeUpFpOut.slow 343 344 345 integerBlock.io.wakeUpIntOut.fast.map(_.ready := true.B) 346 integerBlock.io.wakeUpIntOut.slow.map(_.ready := true.B) 347 floatBlock.io.wakeUpFpOut.fast.map(_.ready := true.B) 348 floatBlock.io.wakeUpFpOut.slow.map(_.ready := true.B) 349 350 val wakeUpMem = Seq( 351 integerBlock.io.wakeUpIntOut, 352 integerBlock.io.wakeUpFpOut, 353 floatBlock.io.wakeUpIntOut, 354 floatBlock.io.wakeUpFpOut 355 ) 356 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 357 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(w => w.fast.map(f => { 358 val raw = WireInit(f) 359 raw 360 })) 361 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(w => w.slow.map(s => { 362 val raw = WireInit(s) 363 raw 364 })) 365 366 integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags 367 integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 368 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 369 integerBlock.io.csrio.isInterrupt <> ctrlBlock.io.roqio.isInterrupt 370 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 371 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 372 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 373 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 374 integerBlock.io.csrio.tlb <> memBlock.io.tlbCsr 375 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 376 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 377 378 floatBlock.io.frm <> integerBlock.io.csrio.frm 379 380 memBlock.io.lsqio.commits <> ctrlBlock.io.roqio.commits 381 memBlock.io.lsqio.roqDeqPtr <> ctrlBlock.io.roqio.roqDeqPtr 382 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.lqIdx 383 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.sqIdx 384 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.ctrl.commitType) 385 386 ptw.io.tlb(0) <> memBlock.io.ptw 387 ptw.io.tlb(1) <> frontend.io.ptw 388 ptw.io.sfence <> integerBlock.io.fenceio.sfence 389 ptw.io.csr <> integerBlock.io.csrio.tlb 390 391 dcache.io.lsu.load <> memBlock.io.dcache.loadUnitToDcacheVec 392 dcache.io.lsu.lsq <> memBlock.io.dcache.loadMiss 393 dcache.io.lsu.atomics <> memBlock.io.dcache.atomics 394 dcache.io.lsu.store <> memBlock.io.dcache.sbufferToDcache 395 uncache.io.lsq <> memBlock.io.dcache.uncache 396 397 if (!env.FPGAPlatform) { 398 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 399 ExcitingUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG", ExcitingUtils.Debug) 400 ExcitingUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG", ExcitingUtils.Debug) 401 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 402 ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug) 403 } 404 405} 406