1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.backend.exu.Exu._ 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.backend.fu.HasExceptionNO 13import xiangshan.cache.{DCache, DCacheParameters, ICache, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, Uncache} 14import chipsalliance.rocketchip.config 15import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp} 16import freechips.rocketchip.tilelink.{TLBuffer, TLBundleParameters, TLCacheCork, TLClientNode, TLFilter, TLIdentityNode, TLToAXI4, TLWidthWidget, TLXbar} 17import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError} 18import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 19import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4IdentityNode, AXI4ToTL, AXI4UserYanker} 20import freechips.rocketchip.tile.HasFPUParameters 21import utils._ 22 23case class XSCoreParameters 24( 25 XLEN: Int = 64, 26 HasMExtension: Boolean = true, 27 HasCExtension: Boolean = true, 28 HasDiv: Boolean = true, 29 HasICache: Boolean = true, 30 HasDCache: Boolean = true, 31 EnableStoreQueue: Boolean = true, 32 AddrBits: Int = 64, 33 VAddrBits: Int = 39, 34 PAddrBits: Int = 40, 35 HasFPU: Boolean = true, 36 FectchWidth: Int = 8, 37 EnableBPU: Boolean = true, 38 EnableBPD: Boolean = true, 39 EnableRAS: Boolean = true, 40 EnableLB: Boolean = false, 41 EnableLoop: Boolean = false, 42 EnableSC: Boolean = false, 43 HistoryLength: Int = 64, 44 BtbSize: Int = 2048, 45 JbtacSize: Int = 1024, 46 JbtacBanks: Int = 8, 47 RasSize: Int = 16, 48 CacheLineSize: Int = 512, 49 UBtbWays: Int = 16, 50 BtbWays: Int = 2, 51 IBufSize: Int = 64, 52 DecodeWidth: Int = 6, 53 RenameWidth: Int = 6, 54 CommitWidth: Int = 6, 55 BrqSize: Int = 32, 56 IssQueSize: Int = 12, 57 NRPhyRegs: Int = 160, 58 NRIntReadPorts: Int = 14, 59 NRIntWritePorts: Int = 8, 60 NRFpReadPorts: Int = 14, 61 NRFpWritePorts: Int = 8, 62 LoadQueueSize: Int = 64, 63 StoreQueueSize: Int = 48, 64 RoqSize: Int = 192, 65 dpParams: DispatchParameters = DispatchParameters( 66 IntDqSize = 32, 67 FpDqSize = 32, 68 LsDqSize = 32, 69 IntDqDeqWidth = 4, 70 FpDqDeqWidth = 4, 71 LsDqDeqWidth = 4 72 ), 73 exuParameters: ExuParameters = ExuParameters( 74 JmpCnt = 1, 75 AluCnt = 4, 76 MulCnt = 0, 77 MduCnt = 2, 78 FmacCnt = 4, 79 FmiscCnt = 2, 80 FmiscDivSqrtCnt = 0, 81 LduCnt = 2, 82 StuCnt = 2 83 ), 84 LoadPipelineWidth: Int = 2, 85 StorePipelineWidth: Int = 2, 86 StoreBufferSize: Int = 16, 87 RefillSize: Int = 512, 88 TlbEntrySize: Int = 32, 89 TlbL2EntrySize: Int = 256, // or 512 90 PtwL1EntrySize: Int = 16, 91 PtwL2EntrySize: Int = 256, 92 NumPerfCounters: Int = 16, 93 NrExtIntr: Int = 1 94) 95 96trait HasXSParameter { 97 98 val core = Parameters.get.coreParameters 99 val env = Parameters.get.envParameters 100 101 val XLEN = 64 102 val minFLen = 32 103 val fLen = 64 104 def xLen = 64 105 val HasMExtension = core.HasMExtension 106 val HasCExtension = core.HasCExtension 107 val HasDiv = core.HasDiv 108 val HasIcache = core.HasICache 109 val HasDcache = core.HasDCache 110 val EnableStoreQueue = core.EnableStoreQueue 111 val AddrBits = core.AddrBits // AddrBits is used in some cases 112 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 113 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 114 val AddrBytes = AddrBits / 8 // unused 115 val DataBits = XLEN 116 val DataBytes = DataBits / 8 117 val HasFPU = core.HasFPU 118 val FetchWidth = core.FectchWidth 119 val PredictWidth = FetchWidth * 2 120 val EnableBPU = core.EnableBPU 121 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 122 val EnableRAS = core.EnableRAS 123 val EnableLB = core.EnableLB 124 val EnableLoop = core.EnableLoop 125 val EnableSC = core.EnableSC 126 val HistoryLength = core.HistoryLength 127 val BtbSize = core.BtbSize 128 // val BtbWays = 4 129 val BtbBanks = PredictWidth 130 // val BtbSets = BtbSize / BtbWays 131 val JbtacSize = core.JbtacSize 132 val JbtacBanks = core.JbtacBanks 133 val RasSize = core.RasSize 134 val CacheLineSize = core.CacheLineSize 135 val CacheLineHalfWord = CacheLineSize / 16 136 val ExtHistoryLength = HistoryLength + 64 137 val UBtbWays = core.UBtbWays 138 val BtbWays = core.BtbWays 139 val IBufSize = core.IBufSize 140 val DecodeWidth = core.DecodeWidth 141 val RenameWidth = core.RenameWidth 142 val CommitWidth = core.CommitWidth 143 val BrqSize = core.BrqSize 144 val IssQueSize = core.IssQueSize 145 val BrTagWidth = log2Up(BrqSize) 146 val NRPhyRegs = core.NRPhyRegs 147 val PhyRegIdxWidth = log2Up(NRPhyRegs) 148 val RoqSize = core.RoqSize 149 val LoadQueueSize = core.LoadQueueSize 150 val StoreQueueSize = core.StoreQueueSize 151 val dpParams = core.dpParams 152 val exuParameters = core.exuParameters 153 val NRIntReadPorts = core.NRIntReadPorts 154 val NRIntWritePorts = core.NRIntWritePorts 155 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 156 val NRFpReadPorts = core.NRFpReadPorts 157 val NRFpWritePorts = core.NRFpWritePorts 158 val LoadPipelineWidth = core.LoadPipelineWidth 159 val StorePipelineWidth = core.StorePipelineWidth 160 val StoreBufferSize = core.StoreBufferSize 161 val RefillSize = core.RefillSize 162 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 163 val TlbEntrySize = core.TlbEntrySize 164 val TlbL2EntrySize = core.TlbL2EntrySize 165 val PtwL1EntrySize = core.PtwL1EntrySize 166 val PtwL2EntrySize = core.PtwL2EntrySize 167 val NumPerfCounters = core.NumPerfCounters 168 val NrExtIntr = core.NrExtIntr 169 170 val icacheParameters = ICacheParameters( 171 tagECC = Some("secded"), 172 dataECC = Some("secded"), 173 nMissEntries = 2 174 ) 175 176 val l1plusCacheParameters = L1plusCacheParameters( 177 tagECC = Some("secded"), 178 dataECC = Some("secded"), 179 nMissEntries = 8 180 ) 181 182 val dcacheParameters = DCacheParameters( 183 tagECC = Some("secded"), 184 dataECC = Some("secded"), 185 nMissEntries = 16, 186 nLoadMissEntries = 8, 187 nStoreMissEntries = 8 188 ) 189 190 val LRSCCycles = 100 191 192 193 // cache hierarchy configurations 194 val l1BusDataWidth = 256 195 196 // L2 configurations 197 val L1BusWidth = 256 198 val L2Size = 512 * 1024 // 512KB 199 val L2BlockSize = 64 200 val L2NWays = 8 201 val L2NSets = L2Size / L2BlockSize / L2NWays 202 203 // L3 configurations 204 val L2BusWidth = 256 205 val L3Size = 4 * 1024 * 1024 // 4MB 206 val L3BlockSize = 64 207 val L3NBanks = 4 208 val L3NWays = 8 209 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 210 211 // on chip network configurations 212 val L3BusWidth = 256 213} 214 215trait HasXSLog { this: RawModule => 216 implicit val moduleName: String = this.name 217} 218 219abstract class XSModule extends MultiIOModule 220 with HasXSParameter 221 with HasExceptionNO 222 with HasXSLog 223 with HasFPUParameters 224{ 225 def io: Record 226} 227 228//remove this trait after impl module logic 229trait NeedImpl { this: RawModule => 230 override protected def IO[T <: Data](iodef: T): T = { 231 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 232 val io = chisel3.experimental.IO(iodef) 233 io <> DontCare 234 io 235 } 236} 237 238abstract class XSBundle extends Bundle 239 with HasXSParameter 240 241case class EnviromentParameters 242( 243 FPGAPlatform: Boolean = true, 244 EnableDebug: Boolean = false 245) 246 247object AddressSpace extends HasXSParameter { 248 // (start, size) 249 // address out of MMIO will be considered as DRAM 250 def mmio = List( 251 (0x00000000L, 0x40000000L), // internal devices, such as CLINT and PLIC 252 (0x40000000L, 0x40000000L) // external devices 253 ) 254 255 def isMMIO(addr: UInt): Bool = mmio.map(range => { 256 require(isPow2(range._2)) 257 val bits = log2Up(range._2) 258 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 259 }).reduce(_ || _) 260} 261 262 263 264class XSCore()(implicit p: config.Parameters) extends LazyModule 265 with HasXSParameter 266 with HasExeBlockHelper 267{ 268 269 // to fast wake up fp, mem rs 270 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 271 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 272 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 273 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 274 275 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 276 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 277 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 278 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 279 280 // outer facing nodes 281 val l1pluscache = LazyModule(new L1plusCache()) 282 val ptw = LazyModule(new PTW()) 283 val memBlock = LazyModule(new MemBlock( 284 fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp, 285 slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp, 286 fastFpOut = Seq(), 287 slowFpOut = loadExuConfigs, 288 fastIntOut = Seq(), 289 slowIntOut = loadExuConfigs 290 )) 291 292 lazy val module = new XSCoreImp(this) 293} 294 295class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 296 with HasXSParameter 297 with HasExeBlockHelper 298{ 299 val io = IO(new Bundle { 300 val externalInterrupt = new ExternalInterruptIO 301 }) 302 303 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 304 305 // to fast wake up fp, mem rs 306 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 307 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 308 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 309 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 310 311 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 312 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 313 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 314 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 315 316 val frontend = Module(new Frontend) 317 val ctrlBlock = Module(new CtrlBlock) 318 val integerBlock = Module(new IntegerBlock( 319 fastWakeUpIn = fpBlockFastWakeUpInt, 320 slowWakeUpIn = fpBlockSlowWakeUpInt ++ loadExuConfigs, 321 fastFpOut = intBlockFastWakeUpFp, 322 slowFpOut = intBlockSlowWakeUpFp, 323 fastIntOut = intBlockFastWakeUpInt, 324 slowIntOut = intBlockSlowWakeUpInt 325 )) 326 val floatBlock = Module(new FloatBlock( 327 fastWakeUpIn = intBlockFastWakeUpFp, 328 slowWakeUpIn = intBlockSlowWakeUpFp ++ loadExuConfigs, 329 fastFpOut = fpBlockFastWakeUpFp, 330 slowFpOut = fpBlockSlowWakeUpFp, 331 fastIntOut = fpBlockFastWakeUpInt, 332 slowIntOut = fpBlockSlowWakeUpInt 333 )) 334 335 val memBlock = outer.memBlock.module 336 val l1pluscache = outer.l1pluscache.module 337 val ptw = outer.ptw.module 338 339 frontend.io.backend <> ctrlBlock.io.frontend 340 frontend.io.sfence <> integerBlock.io.fenceio.sfence 341 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 342 343 frontend.io.icacheMemAcq <> l1pluscache.io.req 344 l1pluscache.io.resp <> frontend.io.icacheMemGrant 345 l1pluscache.io.flush := frontend.io.l1plusFlush 346 frontend.io.fencei := integerBlock.io.fenceio.fencei 347 348 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 349 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 350 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 351 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 352 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 353 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 354 355 integerBlock.io.wakeUpIn.fastUops <> floatBlock.io.wakeUpIntOut.fastUops 356 integerBlock.io.wakeUpIn.fast <> floatBlock.io.wakeUpIntOut.fast 357 integerBlock.io.wakeUpIn.slow <> floatBlock.io.wakeUpIntOut.slow ++ memBlock.io.wakeUpIntOut.slow 358 integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock 359 360 floatBlock.io.wakeUpIn.fastUops <> integerBlock.io.wakeUpFpOut.fastUops 361 floatBlock.io.wakeUpIn.fast <> integerBlock.io.wakeUpFpOut.fast 362 floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlock.io.wakeUpFpOut.slow 363 floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock 364 365 366 integerBlock.io.wakeUpIntOut.fast.map(_.ready := true.B) 367 integerBlock.io.wakeUpIntOut.slow.map(_.ready := true.B) 368 floatBlock.io.wakeUpFpOut.fast.map(_.ready := true.B) 369 floatBlock.io.wakeUpFpOut.slow.map(_.ready := true.B) 370 371 val wakeUpMem = Seq( 372 integerBlock.io.wakeUpIntOut, 373 integerBlock.io.wakeUpFpOut, 374 floatBlock.io.wakeUpIntOut, 375 floatBlock.io.wakeUpFpOut 376 ) 377 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 378 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(w => w.fast.map(f => { 379 val raw = WireInit(f) 380 raw 381 })) 382 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(w => w.slow.map(s => { 383 val raw = WireInit(s) 384 raw 385 })) 386 387 integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags 388 integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 389 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 390 integerBlock.io.csrio.isInterrupt <> ctrlBlock.io.roqio.isInterrupt 391 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 392 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 393 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 394 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 395 integerBlock.io.csrio.tlb <> memBlock.io.tlbCsr 396 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 397 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 398 399 floatBlock.io.frm <> integerBlock.io.csrio.frm 400 401 memBlock.io.lsqio.commits <> ctrlBlock.io.roqio.commits 402 memBlock.io.lsqio.roqDeqPtr <> ctrlBlock.io.roqio.roqDeqPtr 403 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.lqIdx 404 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.sqIdx 405 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.ctrl.commitType) 406 407 ptw.io.tlb(0) <> memBlock.io.ptw 408 ptw.io.tlb(1) <> frontend.io.ptw 409 ptw.io.sfence <> integerBlock.io.fenceio.sfence 410 ptw.io.csr <> integerBlock.io.csrio.tlb 411 412 if (!env.FPGAPlatform) { 413 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 414 ExcitingUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG", ExcitingUtils.Debug) 415 ExcitingUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG", ExcitingUtils.Debug) 416 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 417 ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug) 418 } 419 420} 421