1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.frontend._ 10import xiangshan.mem._ 11import xiangshan.backend.fu.HasExceptionNO 12import xiangshan.cache.{ICache, DCache, L1plusCache, DCacheParameters, ICacheParameters, L1plusCacheParameters, PTW, Uncache} 13import chipsalliance.rocketchip.config 14import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, AddressSet} 15import freechips.rocketchip.tilelink.{TLBundleParameters, TLCacheCork, TLBuffer, TLClientNode, TLIdentityNode, TLXbar, TLWidthWidget, TLFilter, TLToAXI4} 16import freechips.rocketchip.devices.tilelink.{TLError, DevNullParams} 17import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 18import freechips.rocketchip.amba.axi4.{AXI4ToTL, AXI4IdentityNode, AXI4UserYanker, AXI4Fragmenter, AXI4IdIndexer, AXI4Deinterleaver} 19import utils._ 20 21case class XSCoreParameters 22( 23 XLEN: Int = 64, 24 HasMExtension: Boolean = true, 25 HasCExtension: Boolean = true, 26 HasDiv: Boolean = true, 27 HasICache: Boolean = true, 28 HasDCache: Boolean = true, 29 EnableStoreQueue: Boolean = true, 30 AddrBits: Int = 64, 31 VAddrBits: Int = 39, 32 PAddrBits: Int = 40, 33 HasFPU: Boolean = true, 34 FectchWidth: Int = 8, 35 EnableBPU: Boolean = true, 36 EnableBPD: Boolean = true, 37 EnableRAS: Boolean = true, 38 EnableLB: Boolean = true, 39 EnableLoop: Boolean = true, 40 EnableSC: Boolean = false, 41 HistoryLength: Int = 64, 42 BtbSize: Int = 2048, 43 JbtacSize: Int = 1024, 44 JbtacBanks: Int = 8, 45 RasSize: Int = 16, 46 CacheLineSize: Int = 512, 47 UBtbWays: Int = 16, 48 BtbWays: Int = 2, 49 IBufSize: Int = 64, 50 DecodeWidth: Int = 6, 51 RenameWidth: Int = 6, 52 CommitWidth: Int = 6, 53 BrqSize: Int = 12, 54 IssQueSize: Int = 8, 55 NRPhyRegs: Int = 128, 56 NRIntReadPorts: Int = 14, 57 NRIntWritePorts: Int = 8, 58 NRFpReadPorts: Int = 14, 59 NRFpWritePorts: Int = 8, 60 EnableUnifiedLSQ: Boolean = false, 61 LsroqSize: Int = 16, 62 LoadQueueSize: Int = 12, 63 StoreQueueSize: Int = 10, 64 RoqSize: Int = 32, 65 dpParams: DispatchParameters = DispatchParameters( 66 DqEnqWidth = 4, 67 IntDqSize = 24, 68 FpDqSize = 16, 69 LsDqSize = 16, 70 IntDqDeqWidth = 4, 71 FpDqDeqWidth = 4, 72 LsDqDeqWidth = 4, 73 IntDqReplayWidth = 4, 74 FpDqReplayWidth = 4, 75 LsDqReplayWidth = 4 76 ), 77 exuParameters: ExuParameters = ExuParameters( 78 JmpCnt = 1, 79 AluCnt = 4, 80 MulCnt = 0, 81 MduCnt = 2, 82 FmacCnt = 4, 83 FmiscCnt = 2, 84 FmiscDivSqrtCnt = 0, 85 LduCnt = 2, 86 StuCnt = 2 87 ), 88 LoadPipelineWidth: Int = 2, 89 StorePipelineWidth: Int = 2, 90 StoreBufferSize: Int = 16, 91 RefillSize: Int = 512, 92 TlbEntrySize: Int = 32, 93 TlbL2EntrySize: Int = 256, // or 512 94 PtwL1EntrySize: Int = 16, 95 PtwL2EntrySize: Int = 256, 96 NumPerfCounters: Int = 16 97) 98 99trait HasXSParameter { 100 101 val core = Parameters.get.coreParameters 102 val env = Parameters.get.envParameters 103 104 val XLEN = core.XLEN 105 val HasMExtension = core.HasMExtension 106 val HasCExtension = core.HasCExtension 107 val HasDiv = core.HasDiv 108 val HasIcache = core.HasICache 109 val HasDcache = core.HasDCache 110 val EnableStoreQueue = core.EnableStoreQueue 111 val AddrBits = core.AddrBits // AddrBits is used in some cases 112 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 113 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 114 val AddrBytes = AddrBits / 8 // unused 115 val DataBits = XLEN 116 val DataBytes = DataBits / 8 117 val HasFPU = core.HasFPU 118 val FetchWidth = core.FectchWidth 119 val PredictWidth = FetchWidth * 2 120 val EnableBPU = core.EnableBPU 121 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 122 val EnableRAS = core.EnableRAS 123 val EnableLB = core.EnableLB 124 val EnableLoop = core.EnableLoop 125 val EnableSC = core.EnableSC 126 val HistoryLength = core.HistoryLength 127 val BtbSize = core.BtbSize 128 // val BtbWays = 4 129 val BtbBanks = PredictWidth 130 // val BtbSets = BtbSize / BtbWays 131 val JbtacSize = core.JbtacSize 132 val JbtacBanks = core.JbtacBanks 133 val RasSize = core.RasSize 134 val CacheLineSize = core.CacheLineSize 135 val CacheLineHalfWord = CacheLineSize / 16 136 val ExtHistoryLength = HistoryLength + 64 137 val UBtbWays = core.UBtbWays 138 val BtbWays = core.BtbWays 139 val IBufSize = core.IBufSize 140 val DecodeWidth = core.DecodeWidth 141 val RenameWidth = core.RenameWidth 142 val CommitWidth = core.CommitWidth 143 val BrqSize = core.BrqSize 144 val IssQueSize = core.IssQueSize 145 val BrTagWidth = log2Up(BrqSize) 146 val NRPhyRegs = core.NRPhyRegs 147 val PhyRegIdxWidth = log2Up(NRPhyRegs) 148 val RoqSize = core.RoqSize 149 val EnableUnifiedLSQ = core.EnableUnifiedLSQ 150 val LsroqSize = core.LsroqSize // 64 151 val InnerLsroqIdxWidth = log2Up(LsroqSize) 152 val LsroqIdxWidth = InnerLsroqIdxWidth + 1 153 val LoadQueueSize = core.LoadQueueSize 154 val StoreQueueSize = core.StoreQueueSize 155 val dpParams = core.dpParams 156 val ReplayWidth = dpParams.IntDqReplayWidth + dpParams.FpDqReplayWidth + dpParams.LsDqReplayWidth 157 val exuParameters = core.exuParameters 158 val NRIntReadPorts = core.NRIntReadPorts 159 val NRIntWritePorts = core.NRIntWritePorts 160 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 161 val NRFpReadPorts = core.NRFpReadPorts 162 val NRFpWritePorts = core.NRFpWritePorts 163 val LoadPipelineWidth = core.LoadPipelineWidth 164 val StorePipelineWidth = core.StorePipelineWidth 165 val StoreBufferSize = core.StoreBufferSize 166 val RefillSize = core.RefillSize 167 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 168 val TlbEntrySize = core.TlbEntrySize 169 val TlbL2EntrySize = core.TlbL2EntrySize 170 val PtwL1EntrySize = core.PtwL1EntrySize 171 val PtwL2EntrySize = core.PtwL2EntrySize 172 val NumPerfCounters = core.NumPerfCounters 173 174 val icacheParameters = ICacheParameters( 175 nMissEntries = 2 176 ) 177 178 val l1plusCacheParameters = L1plusCacheParameters( 179 tagECC = Some("secded"), 180 dataECC = Some("secded"), 181 nMissEntries = 8 182 ) 183 184 val dcacheParameters = DCacheParameters( 185 tagECC = Some("secded"), 186 dataECC = Some("secded"), 187 nMissEntries = 16, 188 nLoadMissEntries = 8, 189 nStoreMissEntries = 8 190 ) 191 192 val LRSCCycles = 100 193 194 195 // cache hierarchy configurations 196 val l1BusDataWidth = 256 197 198 // L2 configurations 199 val L1BusWidth = 256 200 val L2Size = 512 * 1024 // 512KB 201 val L2BlockSize = 64 202 val L2NWays = 8 203 val L2NSets = L2Size / L2BlockSize / L2NWays 204 205 // L3 configurations 206 val L2BusWidth = 256 207 val L3Size = 4 * 1024 * 1024 // 4MB 208 val L3BlockSize = 64 209 val L3NBanks = 4 210 val L3NWays = 8 211 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 212 213 // on chip network configurations 214 val L3BusWidth = 256 215} 216 217trait HasXSLog { this: RawModule => 218 implicit val moduleName: String = this.name 219} 220 221abstract class XSModule extends MultiIOModule 222 with HasXSParameter 223 with HasExceptionNO 224 with HasXSLog 225{ 226 def io: Record 227} 228 229//remove this trait after impl module logic 230trait NeedImpl { this: RawModule => 231 override protected def IO[T <: Data](iodef: T): T = { 232 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 233 val io = chisel3.experimental.IO(iodef) 234 io <> DontCare 235 io 236 } 237} 238 239abstract class XSBundle extends Bundle 240 with HasXSParameter 241 242case class EnviromentParameters 243( 244 FPGAPlatform: Boolean = true, 245 EnableDebug: Boolean = false 246) 247 248object AddressSpace extends HasXSParameter { 249 // (start, size) 250 // address out of MMIO will be considered as DRAM 251 def mmio = List( 252 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 253 (0x40000000L, 0x40000000L) // external devices 254 ) 255 256 def isMMIO(addr: UInt): Bool = mmio.map(range => { 257 require(isPow2(range._2)) 258 val bits = log2Up(range._2) 259 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 260 }).reduce(_ || _) 261} 262 263 264 265class XSCore()(implicit p: config.Parameters) extends LazyModule with HasXSParameter { 266 267 // inner nodes 268 val dcache = LazyModule(new DCache()) 269 val uncache = LazyModule(new Uncache()) 270 val l1pluscache = LazyModule(new L1plusCache()) 271 val ptw = LazyModule(new PTW()) 272 273 // out facing nodes 274 val mem = TLIdentityNode() 275 val mmio = uncache.clientNode 276 277 // L1 to L2 network 278 // ------------------------------------------------- 279 private val l2_xbar = TLXbar() 280 281 private val l2 = LazyModule(new InclusiveCache( 282 CacheParameters( 283 level = 2, 284 ways = L2NWays, 285 sets = L2NSets, 286 blockBytes = L2BlockSize, 287 beatBytes = L1BusWidth / 8, // beatBytes = l1BusDataWidth / 8 288 cacheName = s"L2" 289 ), 290 InclusiveCacheMicroParameters( 291 writeBytes = 8 292 ) 293 )) 294 295 l2_xbar := TLBuffer() := DebugIdentityNode() := dcache.clientNode 296 l2_xbar := TLBuffer() := DebugIdentityNode() := l1pluscache.clientNode 297 l2_xbar := TLBuffer() := DebugIdentityNode() := ptw.node 298 l2.node := TLBuffer() := DebugIdentityNode() := l2_xbar 299 300 mem := l2.node 301 302 lazy val module = new XSCoreImp(this) 303} 304 305class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) with HasXSParameter { 306 val io = IO(new Bundle { 307 val externalInterrupt = new ExternalInterruptIO 308 }) 309 310 val front = Module(new Frontend) 311 val backend = Module(new Backend) 312 val mem = Module(new Memend) 313 314 val dcache = outer.dcache.module 315 val uncache = outer.uncache.module 316 val l1pluscache = outer.l1pluscache.module 317 val ptw = outer.ptw.module 318 val icache = Module(new ICache) 319 320 front.io.backend <> backend.io.frontend 321 front.io.icacheResp <> icache.io.resp 322 front.io.icacheToTlb <> icache.io.tlb 323 icache.io.req <> front.io.icacheReq 324 icache.io.flush <> front.io.icacheFlush 325 326 icache.io.mem_acquire <> l1pluscache.io.req 327 l1pluscache.io.resp <> icache.io.mem_grant 328 l1pluscache.io.flush := icache.io.l1plusflush 329 icache.io.fencei := backend.io.fencei 330 331 mem.io.backend <> backend.io.mem 332 io.externalInterrupt <> backend.io.externalInterrupt 333 334 ptw.io.tlb(0) <> mem.io.ptw 335 ptw.io.tlb(1) <> front.io.ptw 336 ptw.io.sfence <> backend.io.mem.sfence//sfence 337 ptw.io.csr <> backend.io.tlbCsrIO 338 339 dcache.io.lsu.load <> mem.io.loadUnitToDcacheVec 340 dcache.io.lsu.lsroq <> mem.io.loadMiss 341 dcache.io.lsu.atomics <> mem.io.atomics 342 dcache.io.lsu.store <> mem.io.sbufferToDcache 343 uncache.io.lsroq <> mem.io.uncache 344 345} 346