1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.frontend._ 10import xiangshan.mem._ 11import xiangshan.backend.fu.HasExceptionNO 12import xiangshan.cache.{ICache, DCache, L1plusCache, DCacheParameters, ICacheParameters, L1plusCacheParameters, PTW, Uncache} 13import chipsalliance.rocketchip.config 14import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 15import freechips.rocketchip.tilelink.{TLBundleParameters, TLCacheCork, TLBuffer, TLClientNode, TLIdentityNode, TLXbar} 16import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 17import utils._ 18 19case class XSCoreParameters 20( 21 XLEN: Int = 64, 22 HasMExtension: Boolean = true, 23 HasCExtension: Boolean = true, 24 HasDiv: Boolean = true, 25 HasICache: Boolean = true, 26 HasDCache: Boolean = true, 27 EnableStoreQueue: Boolean = true, 28 AddrBits: Int = 64, 29 VAddrBits: Int = 39, 30 PAddrBits: Int = 40, 31 HasFPU: Boolean = true, 32 FectchWidth: Int = 8, 33 EnableBPU: Boolean = true, 34 EnableBPD: Boolean = true, 35 EnableRAS: Boolean = true, 36 EnableLB: Boolean = false, 37 EnableLoop: Boolean = false, 38 HistoryLength: Int = 64, 39 BtbSize: Int = 2048, 40 JbtacSize: Int = 1024, 41 JbtacBanks: Int = 8, 42 RasSize: Int = 16, 43 CacheLineSize: Int = 512, 44 UBtbWays: Int = 16, 45 BtbWays: Int = 2, 46 IBufSize: Int = 64, 47 DecodeWidth: Int = 6, 48 RenameWidth: Int = 6, 49 CommitWidth: Int = 6, 50 BrqSize: Int = 12, 51 IssQueSize: Int = 8, 52 NRPhyRegs: Int = 128, 53 NRIntReadPorts: Int = 14, 54 NRIntWritePorts: Int = 8, 55 NRFpReadPorts: Int = 14, 56 NRFpWritePorts: Int = 8, 57 EnableUnifiedLSQ: Boolean = false, 58 LsroqSize: Int = 16, 59 LoadQueueSize: Int = 12, 60 StoreQueueSize: Int = 10, 61 RoqSize: Int = 32, 62 dpParams: DispatchParameters = DispatchParameters( 63 DqEnqWidth = 4, 64 IntDqSize = 24, 65 FpDqSize = 16, 66 LsDqSize = 16, 67 IntDqDeqWidth = 4, 68 FpDqDeqWidth = 4, 69 LsDqDeqWidth = 4, 70 IntDqReplayWidth = 4, 71 FpDqReplayWidth = 4, 72 LsDqReplayWidth = 4 73 ), 74 exuParameters: ExuParameters = ExuParameters( 75 JmpCnt = 1, 76 AluCnt = 4, 77 MulCnt = 0, 78 MduCnt = 2, 79 FmacCnt = 4, 80 FmiscCnt = 2, 81 FmiscDivSqrtCnt = 0, 82 LduCnt = 2, 83 StuCnt = 2 84 ), 85 LoadPipelineWidth: Int = 2, 86 StorePipelineWidth: Int = 2, 87 StoreBufferSize: Int = 16, 88 RefillSize: Int = 512, 89 TlbEntrySize: Int = 32, 90 TlbL2EntrySize: Int = 256, // or 512 91 PtwL1EntrySize: Int = 16, 92 PtwL2EntrySize: Int = 256, 93 NumPerfCounters: Int = 16 94) 95 96trait HasXSParameter { 97 98 val core = Parameters.get.coreParameters 99 val env = Parameters.get.envParameters 100 101 val XLEN = core.XLEN 102 val HasMExtension = core.HasMExtension 103 val HasCExtension = core.HasCExtension 104 val HasDiv = core.HasDiv 105 val HasIcache = core.HasICache 106 val HasDcache = core.HasDCache 107 val EnableStoreQueue = core.EnableStoreQueue 108 val AddrBits = core.AddrBits // AddrBits is used in some cases 109 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 110 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 111 val AddrBytes = AddrBits / 8 // unused 112 val DataBits = XLEN 113 val DataBytes = DataBits / 8 114 val HasFPU = core.HasFPU 115 val FetchWidth = core.FectchWidth 116 val PredictWidth = FetchWidth * 2 117 val EnableBPU = core.EnableBPU 118 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 119 val EnableRAS = core.EnableRAS 120 val EnableLB = core.EnableLB 121 val EnableLoop = core.EnableLoop 122 val HistoryLength = core.HistoryLength 123 val BtbSize = core.BtbSize 124 // val BtbWays = 4 125 val BtbBanks = PredictWidth 126 // val BtbSets = BtbSize / BtbWays 127 val JbtacSize = core.JbtacSize 128 val JbtacBanks = core.JbtacBanks 129 val RasSize = core.RasSize 130 val CacheLineSize = core.CacheLineSize 131 val CacheLineHalfWord = CacheLineSize / 16 132 val ExtHistoryLength = HistoryLength + 64 133 val UBtbWays = core.UBtbWays 134 val BtbWays = core.BtbWays 135 val IBufSize = core.IBufSize 136 val DecodeWidth = core.DecodeWidth 137 val RenameWidth = core.RenameWidth 138 val CommitWidth = core.CommitWidth 139 val BrqSize = core.BrqSize 140 val IssQueSize = core.IssQueSize 141 val BrTagWidth = log2Up(BrqSize) 142 val NRPhyRegs = core.NRPhyRegs 143 val PhyRegIdxWidth = log2Up(NRPhyRegs) 144 val RoqSize = core.RoqSize 145 val EnableUnifiedLSQ = core.EnableUnifiedLSQ 146 val LsroqSize = core.LsroqSize // 64 147 val InnerLsroqIdxWidth = log2Up(LsroqSize) 148 val LsroqIdxWidth = InnerLsroqIdxWidth + 1 149 val LoadQueueSize = core.LoadQueueSize 150 val StoreQueueSize = core.StoreQueueSize 151 val dpParams = core.dpParams 152 val ReplayWidth = dpParams.IntDqReplayWidth + dpParams.FpDqReplayWidth + dpParams.LsDqReplayWidth 153 val exuParameters = core.exuParameters 154 val NRIntReadPorts = core.NRIntReadPorts 155 val NRIntWritePorts = core.NRIntWritePorts 156 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 157 val NRFpReadPorts = core.NRFpReadPorts 158 val NRFpWritePorts = core.NRFpWritePorts 159 val LoadPipelineWidth = core.LoadPipelineWidth 160 val StorePipelineWidth = core.StorePipelineWidth 161 val StoreBufferSize = core.StoreBufferSize 162 val RefillSize = core.RefillSize 163 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 164 val TlbEntrySize = core.TlbEntrySize 165 val TlbL2EntrySize = core.TlbL2EntrySize 166 val PtwL1EntrySize = core.PtwL1EntrySize 167 val PtwL2EntrySize = core.PtwL2EntrySize 168 val NumPerfCounters = core.NumPerfCounters 169 170 val l1BusDataWidth = 256 171 172 val icacheParameters = ICacheParameters( 173 nMissEntries = 2 174 ) 175 176 val l1plusCacheParameters = L1plusCacheParameters( 177 tagECC = Some("secded"), 178 dataECC = Some("secded"), 179 nMissEntries = 8 180 ) 181 182 val dcacheParameters = DCacheParameters( 183 tagECC = Some("secded"), 184 dataECC = Some("secded"), 185 nMissEntries = 16, 186 nLoadMissEntries = 8, 187 nStoreMissEntries = 8 188 ) 189 190 val LRSCCycles = 100 191} 192 193trait HasXSLog { this: RawModule => 194 implicit val moduleName: String = this.name 195} 196 197abstract class XSModule extends MultiIOModule 198 with HasXSParameter 199 with HasExceptionNO 200 with HasXSLog 201{ 202 def io: Record 203} 204 205//remove this trait after impl module logic 206trait NeedImpl { this: RawModule => 207 override protected def IO[T <: Data](iodef: T): T = { 208 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 209 val io = chisel3.experimental.IO(iodef) 210 io <> DontCare 211 io 212 } 213} 214 215abstract class XSBundle extends Bundle 216 with HasXSParameter 217 218case class EnviromentParameters 219( 220 FPGAPlatform: Boolean = true, 221 EnableDebug: Boolean = false 222) 223 224object AddressSpace extends HasXSParameter { 225 // (start, size) 226 // address out of MMIO will be considered as DRAM 227 def mmio = List( 228 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 229 (0x40000000L, 0x40000000L) // external devices 230 ) 231 232 def isMMIO(addr: UInt): Bool = mmio.map(range => { 233 require(isPow2(range._2)) 234 val bits = log2Up(range._2) 235 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 236 }).reduce(_ || _) 237} 238 239 240 241class XSCore()(implicit p: config.Parameters) extends LazyModule { 242 243 val dcache = LazyModule(new DCache()) 244 val uncache = LazyModule(new Uncache()) 245 val l1pluscache = LazyModule(new L1plusCache()) 246 val ptw = LazyModule(new PTW()) 247 248 val mem = TLIdentityNode() 249 val mmio = uncache.clientNode 250 251 // TODO: refactor these params 252 private val l2 = LazyModule(new InclusiveCache( 253 CacheParameters( 254 level = 2, 255 ways = 4, 256 sets = 512 * 1024 / (64 * 4), 257 blockBytes = 64, 258 beatBytes = 32 // beatBytes = l1BusDataWidth / 8 259 ), 260 InclusiveCacheMicroParameters( 261 writeBytes = 8 262 ) 263 )) 264 265 private val xbar = TLXbar() 266 267 xbar := TLBuffer() := DebugIdentityNode() := dcache.clientNode 268 xbar := TLBuffer() := DebugIdentityNode() := l1pluscache.clientNode 269 xbar := TLBuffer() := DebugIdentityNode() := ptw.node 270 271 l2.node := xbar 272 273 mem := TLBuffer() := TLCacheCork() := TLBuffer() := l2.node 274 275 lazy val module = new XSCoreImp(this) 276} 277 278class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) with HasXSParameter { 279 val io = IO(new Bundle { 280 val externalInterrupt = new ExternalInterruptIO 281 }) 282 283 val front = Module(new Frontend) 284 val backend = Module(new Backend) 285 val mem = Module(new Memend) 286 287 val dcache = outer.dcache.module 288 val uncache = outer.uncache.module 289 val l1pluscache = outer.l1pluscache.module 290 val ptw = outer.ptw.module 291 val icache = Module(new ICache) 292 293 front.io.backend <> backend.io.frontend 294 front.io.icacheResp <> icache.io.resp 295 front.io.icacheToTlb <> icache.io.tlb 296 icache.io.req <> front.io.icacheReq 297 icache.io.flush <> front.io.icacheFlush 298 299 icache.io.mem_acquire <> l1pluscache.io.req 300 l1pluscache.io.resp <> icache.io.mem_grant 301 l1pluscache.io.flush := icache.io.l1plusflush 302 icache.io.fencei := backend.io.fencei 303 304 mem.io.backend <> backend.io.mem 305 io.externalInterrupt <> backend.io.externalInterrupt 306 307 ptw.io.tlb(0) <> mem.io.ptw 308 ptw.io.tlb(1) <> front.io.ptw 309 ptw.io.sfence <> backend.io.sfence 310 ptw.io.csr <> backend.io.tlbCsrIO 311 312 dcache.io.lsu.load <> mem.io.loadUnitToDcacheVec 313 dcache.io.lsu.lsroq <> mem.io.loadMiss 314 dcache.io.lsu.atomics <> mem.io.atomics 315 dcache.io.lsu.store <> mem.io.sbufferToDcache 316 uncache.io.lsroq <> mem.io.uncache 317 318} 319