1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 7import xiangshan.backend._ 8import xiangshan.backend.dispatch.DP1Parameters 9import xiangshan.backend.exu.ExuParameters 10import xiangshan.frontend.Frontend 11import xiangshan.mem._ 12import xiangshan.utils._ 13 14trait HasXSParameter { 15 val XLEN = 64 16 val HasMExtension = true 17 val HasCExtension = true 18 val HasDiv = true 19 val HasIcache = true 20 val HasDcache = true 21 val EnableStoreQueue = false 22 val AddrBits = 64 // AddrBits is used in some cases 23 val VAddrBits = 39 // VAddrBits is Virtual Memory addr bits 24 val PAddrBits = 32 // PAddrBits is Phyical Memory addr bits 25 val L1CacheLineSize = 512 26 val AddrBytes = AddrBits / 8 // unused 27 val DataBits = XLEN 28 val DataBytes = DataBits / 8 29 val HasFPU = true 30 val FetchWidth = 8 31 val IBufSize = 64 32 val DecodeWidth = 6 33 val RenameWidth = 6 34 val CommitWidth = 6 35 val BrqSize = 16 36 val IssQueSize = 8 37 val BrTagWidth = log2Up(BrqSize) 38 val NRPhyRegs = 128 39 val PhyRegIdxWidth = log2Up(NRPhyRegs) 40 val NRReadPorts = 14 41 val NRWritePorts = 8 42 val RoqSize = 32 43 val InnerRoqIdxWidth = log2Up(RoqSize) 44 val RoqIdxWidth = InnerRoqIdxWidth + 1 45 val IntDqDeqWidth = 4 46 val FpDqDeqWidth = 4 47 val LsDqDeqWidth = 4 48 val dp1Paremeters = DP1Parameters( 49 IntDqSize = 16, 50 FpDqSize = 16, 51 LsDqSize = 16 52 ) 53 val exuParameters = ExuParameters( 54 JmpCnt = 1, 55 AluCnt = 4, 56 MulCnt = 1, 57 MduCnt = 1, 58 FmacCnt = 0, 59 FmiscCnt = 0, 60 FmiscDivSqrtCnt = 0, 61 LduCnt = 0, 62 StuCnt = 1 63 ) 64} 65 66trait HasXSLog { this: Module => 67 implicit val moduleName: String = this.name 68} 69 70abstract class XSModule extends Module 71 with HasXSParameter 72 with HasExceptionNO 73 with HasXSLog 74 75//remove this trait after impl module logic 76trait NeedImpl { this: Module => 77 override protected def IO[T <: Data](iodef: T): T = { 78 val io = chisel3.experimental.IO(iodef) 79 io <> DontCare 80 io 81 } 82} 83 84abstract class XSBundle extends Bundle 85 with HasXSParameter 86 87case class XSConfig 88( 89 FPGAPlatform: Boolean = true, 90 EnableDebug: Boolean = true 91) 92 93object AddressSpace extends HasXSParameter { 94 // (start, size) 95 // address out of MMIO will be considered as DRAM 96 def mmio = List( 97 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 98 (0x40000000L, 0x40000000L) // external devices 99 ) 100 101 def isMMIO(addr: UInt): Bool = mmio.map(range => { 102 require(isPow2(range._2)) 103 val bits = log2Up(range._2) 104 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 105 }).reduce(_ || _) 106} 107 108 109class XSCore(implicit val p: XSConfig) extends XSModule { 110 val io = IO(new Bundle { 111 val imem = new SimpleBusC 112 val dmem = new SimpleBusC 113 val mmio = new SimpleBusUC 114 val frontend = Flipped(new SimpleBusUC()) 115 }) 116 117 io.imem <> DontCare 118 119 val dmemXbar = Module(new SimpleBusCrossbarNto1(3)) 120 121 val front = Module(new Frontend) 122 val backend = Module(new Backend) 123 val mem = Module(new MemPipeline) 124 125 mem.io := DontCare // FIXME 126 127 front.io.backend <> backend.io.frontend 128 129 backend.io.memMMU.imem <> DontCare 130 131 val dtlb = TLB( 132 in = backend.io.dmem, 133 mem = dmemXbar.io.in(1), 134 flush = false.B, 135 csrMMU = backend.io.memMMU.dmem 136 )(TLBConfig(name = "dtlb", totalEntry = 64)) 137 dmemXbar.io.in(0) <> dtlb.io.out 138 dmemXbar.io.in(2) <> io.frontend 139 140 io.dmem <> Cache( 141 in = dmemXbar.io.out, 142 mmio = Seq(io.mmio), 143 flush = "b00".U, 144 empty = dtlb.io.cacheEmpty, 145 enable = HasDcache 146 )(CacheConfig(name = "dcache")) 147 148 XSDebug("(req valid, ready | resp valid, ready) \n") 149 XSDebug("c-mem(%x %x %x| %x %x) c-coh(%x %x %x| %x %x) cache (%x %x %x| %x %x) tlb (%x %x %x| %x %x)\n", 150 io.dmem.mem.req.valid, 151 io.dmem.mem.req.ready, 152 io.dmem.mem.req.bits.addr, 153 io.dmem.mem.resp.valid, 154 io.dmem.mem.resp.ready, 155 io.dmem.coh.req.valid, 156 io.dmem.coh.req.ready, 157 io.dmem.coh.req.bits.addr, 158 io.dmem.coh.resp.valid, 159 io.dmem.coh.resp.ready, 160 dmemXbar.io.out.req.valid, 161 dmemXbar.io.out.req.ready, 162 dmemXbar.io.out.req.bits.addr, 163 dmemXbar.io.out.resp.valid, 164 dmemXbar.io.out.resp.ready, 165 backend.io.dmem.req.valid, 166 backend.io.dmem.req.ready, 167 backend.io.dmem.req.bits.addr, 168 backend.io.dmem.resp.valid, 169 backend.io.dmem.resp.ready 170 ) 171} 172