1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import device.MsiInfoBundle 24import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp} 25import freechips.rocketchip.tile.HasFPUParameters 26import system.HasSoCParameter 27import utils._ 28import utility._ 29import xiangshan.backend._ 30import xiangshan.backend.fu.PMPRespBundle 31import xiangshan.backend.trace.TraceCoreInterface 32import xiangshan.cache.mmu._ 33import xiangshan.frontend._ 34import xiangshan.mem.L1PrefetchFuzzer 35import scala.collection.mutable.ListBuffer 36import xiangshan.cache.mmu.TlbRequestIO 37 38abstract class XSModule(implicit val p: Parameters) extends Module 39 with HasXSParameter 40 with HasFPUParameters 41 42//remove this trait after impl module logic 43trait NeedImpl { 44 this: RawModule => 45 protected def IO[T <: Data](iodef: T): T = { 46 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 47 val io = chisel3.IO(iodef) 48 io <> DontCare 49 io 50 } 51} 52 53abstract class XSBundle(implicit val p: Parameters) extends Bundle 54 with HasXSParameter 55 56abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 57 with HasXSParameter 58{ 59 override def shouldBeInlined: Boolean = false 60 // outer facing nodes 61 val frontend = LazyModule(new Frontend()) 62 val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO())) 63 val backend = LazyModule(new Backend(backendParams)) 64 65 val memBlock = LazyModule(new MemBlock) 66 67 memBlock.inner.frontendBridge.icache_node := frontend.inner.icache.clientNode 68 memBlock.inner.frontendBridge.instr_uncache_node := frontend.inner.instrUncache.clientNode 69} 70 71class XSCore()(implicit p: config.Parameters) extends XSCoreBase 72 with HasXSDts 73{ 74 lazy val module = new XSCoreImp(this) 75} 76 77class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 78 with HasXSParameter 79 with HasSoCParameter { 80 val io = IO(new Bundle { 81 val hartId = Input(UInt(hartIdLen.W)) 82 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 83 val clintTime = Input(ValidIO(UInt(64.W))) 84 val reset_vector = Input(UInt(PAddrBits.W)) 85 val cpu_halt = Output(Bool()) 86 val cpu_critical_error = Output(Bool()) 87 val resetInFrontend = Output(Bool()) 88 val traceCoreInterface = new TraceCoreInterface 89 val l2_pf_enable = Output(Bool()) 90 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent)) 91 val beu_errors = Output(new XSL1BusErrors()) 92 val l2_hint = Input(Valid(new L2ToL1Hint())) 93 val l2_tlb_req = Flipped(new TlbRequestIO(nRespDups = 2)) 94 val l2_pmp_resp = new PMPRespBundle 95 val l2PfqBusy = Input(Bool()) 96 val debugTopDown = new Bundle { 97 val robTrueCommit = Output(UInt(64.W)) 98 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 99 val l2MissMatch = Input(Bool()) 100 val l3MissMatch = Input(Bool()) 101 } 102 }) 103 104 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 105 106 val frontend = outer.frontend.module 107 val backend = outer.backend.module 108 val memBlock = outer.memBlock.module 109 110 frontend.io.hartId := memBlock.io.inner_hartId 111 frontend.io.reset_vector := memBlock.io.inner_reset_vector 112 frontend.io.softPrefetch <> memBlock.io.ifetchPrefetch 113 frontend.io.backend <> backend.io.frontend 114 frontend.io.sfence <> backend.io.frontendSfence 115 frontend.io.tlbCsr <> backend.io.frontendTlbCsr 116 frontend.io.csrCtrl <> backend.io.frontendCsrCtrl 117 frontend.io.fencei <> backend.io.fenceio.fencei 118 119 backend.io.fromTop := memBlock.io.mem_to_ooo.topToBackendBypass 120 121 require(backend.io.mem.stIn.length == memBlock.io.mem_to_ooo.stIn.length) 122 backend.io.mem.stIn.zip(memBlock.io.mem_to_ooo.stIn).foreach { case (sink, source) => 123 sink.valid := source.valid 124 sink.bits := 0.U.asTypeOf(sink.bits) 125 sink.bits.robIdx := source.bits.uop.robIdx 126 sink.bits.ssid := source.bits.uop.ssid 127 sink.bits.storeSetHit := source.bits.uop.storeSetHit 128 // The other signals have not been used 129 } 130 backend.io.mem.memoryViolation := memBlock.io.mem_to_ooo.memoryViolation 131 backend.io.mem.lsqEnqIO <> memBlock.io.ooo_to_mem.enqLsq 132 backend.io.mem.sqDeq := memBlock.io.mem_to_ooo.sqDeq 133 backend.io.mem.lqDeq := memBlock.io.mem_to_ooo.lqDeq 134 backend.io.mem.sqDeqPtr := memBlock.io.mem_to_ooo.sqDeqPtr 135 backend.io.mem.lqDeqPtr := memBlock.io.mem_to_ooo.lqDeqPtr 136 backend.io.mem.lqCancelCnt := memBlock.io.mem_to_ooo.lqCancelCnt 137 backend.io.mem.sqCancelCnt := memBlock.io.mem_to_ooo.sqCancelCnt 138 backend.io.mem.otherFastWakeup := memBlock.io.mem_to_ooo.otherFastWakeup 139 backend.io.mem.stIssuePtr := memBlock.io.mem_to_ooo.stIssuePtr 140 backend.io.mem.ldaIqFeedback := memBlock.io.mem_to_ooo.ldaIqFeedback 141 backend.io.mem.staIqFeedback := memBlock.io.mem_to_ooo.staIqFeedback 142 backend.io.mem.hyuIqFeedback := memBlock.io.mem_to_ooo.hyuIqFeedback 143 backend.io.mem.vstuIqFeedback := memBlock.io.mem_to_ooo.vstuIqFeedback 144 backend.io.mem.vlduIqFeedback := memBlock.io.mem_to_ooo.vlduIqFeedback 145 backend.io.mem.ldCancel := memBlock.io.mem_to_ooo.ldCancel 146 backend.io.mem.wakeup := memBlock.io.mem_to_ooo.wakeup 147 backend.io.mem.writebackLda <> memBlock.io.mem_to_ooo.writebackLda 148 backend.io.mem.writebackSta <> memBlock.io.mem_to_ooo.writebackSta 149 backend.io.mem.writebackHyuLda <> memBlock.io.mem_to_ooo.writebackHyuLda 150 backend.io.mem.writebackHyuSta <> memBlock.io.mem_to_ooo.writebackHyuSta 151 backend.io.mem.writebackStd <> memBlock.io.mem_to_ooo.writebackStd 152 backend.io.mem.writebackVldu <> memBlock.io.mem_to_ooo.writebackVldu 153 backend.io.mem.robLsqIO.mmio := memBlock.io.mem_to_ooo.lsqio.mmio 154 backend.io.mem.robLsqIO.uop := memBlock.io.mem_to_ooo.lsqio.uop 155 156 // memblock error exception writeback, 1 cycle after normal writeback 157 backend.io.mem.s3_delayed_load_error := memBlock.io.mem_to_ooo.s3_delayed_load_error 158 159 backend.io.mem.exceptionAddr.vaddr := memBlock.io.mem_to_ooo.lsqio.vaddr 160 backend.io.mem.exceptionAddr.gpaddr := memBlock.io.mem_to_ooo.lsqio.gpaddr 161 backend.io.mem.exceptionAddr.isForVSnonLeafPTE := memBlock.io.mem_to_ooo.lsqio.isForVSnonLeafPTE 162 backend.io.mem.debugLS := memBlock.io.debug_ls 163 backend.io.mem.lsTopdownInfo := memBlock.io.mem_to_ooo.lsTopdownInfo 164 backend.io.mem.lqCanAccept := memBlock.io.mem_to_ooo.lsqio.lqCanAccept 165 backend.io.mem.sqCanAccept := memBlock.io.mem_to_ooo.lsqio.sqCanAccept 166 backend.io.fenceio.sbuffer.sbIsEmpty := memBlock.io.mem_to_ooo.sbIsEmpty 167 168 backend.io.perf.frontendInfo := frontend.io.frontendInfo 169 backend.io.perf.memInfo := memBlock.io.memInfo 170 backend.io.perf.perfEventsFrontend := frontend.io_perf 171 backend.io.perf.perfEventsLsu := memBlock.io_perf 172 backend.io.perf.perfEventsHc := memBlock.io.inner_hc_perfEvents 173 backend.io.perf.perfEventsBackend := DontCare 174 backend.io.perf.retiredInstr := DontCare 175 backend.io.perf.ctrlInfo := DontCare 176 177 backend.io.mem.storeDebugInfo <> memBlock.io.mem_to_ooo.storeDebugInfo 178 179 // top -> memBlock 180 memBlock.io.fromTopToBackend.clintTime := io.clintTime 181 memBlock.io.fromTopToBackend.msiInfo := io.msiInfo 182 memBlock.io.hartId := io.hartId 183 memBlock.io.outer_reset_vector := io.reset_vector 184 memBlock.io.outer_hc_perfEvents := io.perfEvents 185 // frontend -> memBlock 186 memBlock.io.inner_beu_errors_icache <> frontend.io.error.bits.toL1BusErrorUnitInfo(frontend.io.error.valid) 187 memBlock.io.inner_l2_pf_enable := backend.io.csrCustomCtrl.l2_pf_enable 188 memBlock.io.ooo_to_mem.backendToTopBypass := backend.io.toTop 189 memBlock.io.ooo_to_mem.issueLda <> backend.io.mem.issueLda 190 memBlock.io.ooo_to_mem.issueSta <> backend.io.mem.issueSta 191 memBlock.io.ooo_to_mem.issueStd <> backend.io.mem.issueStd 192 memBlock.io.ooo_to_mem.issueHya <> backend.io.mem.issueHylda 193 backend.io.mem.issueHysta.foreach(_.ready := false.B) // this fake port should not be used 194 memBlock.io.ooo_to_mem.issueVldu <> backend.io.mem.issueVldu 195 196 // By default, instructions do not have exceptions when they enter the function units. 197 memBlock.io.ooo_to_mem.issueUops.map(_.bits.uop.clearExceptions()) 198 memBlock.io.ooo_to_mem.storePc := backend.io.mem.storePcRead 199 memBlock.io.ooo_to_mem.hybridPc := backend.io.mem.hyuPcRead 200 memBlock.io.ooo_to_mem.flushSb := backend.io.fenceio.sbuffer.flushSb 201 memBlock.io.ooo_to_mem.loadFastMatch := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastMatch) 202 memBlock.io.ooo_to_mem.loadFastImm := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastImm) 203 memBlock.io.ooo_to_mem.loadFastFuOpType := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastFuOpType) 204 205 memBlock.io.ooo_to_mem.sfence <> backend.io.mem.sfence 206 207 memBlock.io.redirect := backend.io.mem.redirect 208 memBlock.io.ooo_to_mem.csrCtrl := backend.io.mem.csrCtrl 209 memBlock.io.ooo_to_mem.tlbCsr := backend.io.mem.tlbCsr 210 memBlock.io.ooo_to_mem.lsqio.lcommit := backend.io.mem.robLsqIO.lcommit 211 memBlock.io.ooo_to_mem.lsqio.scommit := backend.io.mem.robLsqIO.scommit 212 memBlock.io.ooo_to_mem.lsqio.pendingMMIOld := backend.io.mem.robLsqIO.pendingMMIOld 213 memBlock.io.ooo_to_mem.lsqio.pendingld := backend.io.mem.robLsqIO.pendingld 214 memBlock.io.ooo_to_mem.lsqio.pendingst := backend.io.mem.robLsqIO.pendingst 215 memBlock.io.ooo_to_mem.lsqio.pendingVst := backend.io.mem.robLsqIO.pendingVst 216 memBlock.io.ooo_to_mem.lsqio.commit := backend.io.mem.robLsqIO.commit 217 memBlock.io.ooo_to_mem.lsqio.pendingPtr := backend.io.mem.robLsqIO.pendingPtr 218 memBlock.io.ooo_to_mem.lsqio.pendingPtrNext := backend.io.mem.robLsqIO.pendingPtrNext 219 memBlock.io.ooo_to_mem.isStoreException := backend.io.mem.isStoreException 220 memBlock.io.ooo_to_mem.isVlsException := backend.io.mem.isVlsException 221 222 memBlock.io.fetch_to_mem.itlb <> frontend.io.ptw 223 memBlock.io.l2_hint.valid := io.l2_hint.valid 224 memBlock.io.l2_hint.bits.sourceId := io.l2_hint.bits.sourceId 225 memBlock.io.l2_tlb_req <> io.l2_tlb_req 226 memBlock.io.l2_pmp_resp <> io.l2_pmp_resp 227 memBlock.io.l2_hint.bits.isKeyword := io.l2_hint.bits.isKeyword 228 memBlock.io.l2PfqBusy := io.l2PfqBusy 229 230 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 231 232 // top-down info 233 memBlock.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 234 frontend.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 235 io.debugTopDown.robHeadPaddr := backend.io.debugTopDown.fromRob.robHeadPaddr 236 io.debugTopDown.robTrueCommit := backend.io.debugRolling.robTrueCommit 237 backend.io.debugTopDown.fromCore.l2MissMatch := io.debugTopDown.l2MissMatch 238 backend.io.debugTopDown.fromCore.l3MissMatch := io.debugTopDown.l3MissMatch 239 backend.io.debugTopDown.fromCore.fromMem := memBlock.io.debugTopDown.toCore 240 memBlock.io.debugRolling := backend.io.debugRolling 241 242 io.cpu_halt := memBlock.io.outer_cpu_halt 243 io.cpu_critical_error := memBlock.io.outer_cpu_critical_error 244 io.beu_errors.icache <> memBlock.io.outer_beu_errors_icache 245 io.beu_errors.dcache <> memBlock.io.error.bits.toL1BusErrorUnitInfo(memBlock.io.error.valid) 246 io.beu_errors.l2 <> DontCare 247 io.l2_pf_enable := memBlock.io.outer_l2_pf_enable 248 249 memBlock.io.resetInFrontendBypass.fromFrontend := frontend.io.resetInFrontend 250 io.resetInFrontend := memBlock.io.resetInFrontendBypass.toL2Top 251 memBlock.io.traceCoreInterfaceBypass.fromBackend <> backend.io.traceCoreInterface 252 io.traceCoreInterface <> memBlock.io.traceCoreInterfaceBypass.toL2Top 253 254 255 if (debugOpts.ResetGen) { 256 backend.reset := memBlock.io.reset_backend 257 frontend.reset := backend.io.frontendReset 258 } 259} 260