1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config 20import chipsalliance.rocketchip.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp} 24import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple} 25import freechips.rocketchip.tile.HasFPUParameters 26import freechips.rocketchip.tilelink.TLBuffer 27import system.HasSoCParameter 28import utils._ 29import utility._ 30import xiangshan.backend._ 31import xiangshan.backend.exu.{ExuConfig, Wb2Ctrl, WbArbiterWrapper} 32import xiangshan.cache.mmu._ 33import xiangshan.frontend._ 34 35import scala.collection.mutable.ListBuffer 36 37abstract class XSModule(implicit val p: Parameters) extends Module 38 with HasXSParameter 39 with HasFPUParameters 40 41//remove this trait after impl module logic 42trait NeedImpl { 43 this: RawModule => 44 override protected def IO[T <: Data](iodef: T): T = { 45 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 46 val io = chisel3.experimental.IO(iodef) 47 io <> DontCare 48 io 49 } 50} 51 52class WritebackSourceParams( 53 var exuConfigs: Seq[Seq[ExuConfig]] = Seq() 54 ) { 55 def length: Int = exuConfigs.length 56 def ++(that: WritebackSourceParams): WritebackSourceParams = { 57 new WritebackSourceParams(exuConfigs ++ that.exuConfigs) 58 } 59} 60 61trait HasWritebackSource { 62 val writebackSourceParams: Seq[WritebackSourceParams] 63 final def writebackSource(sourceMod: HasWritebackSourceImp): Seq[Seq[Valid[ExuOutput]]] = { 64 require(sourceMod.writebackSource.isDefined, "should not use Valid[ExuOutput]") 65 val source = sourceMod.writebackSource.get 66 require(source.length == writebackSourceParams.length, "length mismatch between sources") 67 for ((s, p) <- source.zip(writebackSourceParams)) { 68 require(s.length == p.length, "params do not match with the exuOutput") 69 } 70 source 71 } 72 final def writebackSource1(sourceMod: HasWritebackSourceImp): Seq[Seq[DecoupledIO[ExuOutput]]] = { 73 require(sourceMod.writebackSource1.isDefined, "should not use DecoupledIO[ExuOutput]") 74 val source = sourceMod.writebackSource1.get 75 require(source.length == writebackSourceParams.length, "length mismatch between sources") 76 for ((s, p) <- source.zip(writebackSourceParams)) { 77 require(s.length == p.length, "params do not match with the exuOutput") 78 } 79 source 80 } 81 val writebackSourceImp: HasWritebackSourceImp 82} 83 84trait HasWritebackSourceImp { 85 def writebackSource: Option[Seq[Seq[Valid[ExuOutput]]]] = None 86 def writebackSource1: Option[Seq[Seq[DecoupledIO[ExuOutput]]]] = None 87} 88 89trait HasWritebackSink { 90 // Caches all sources. The selected source will be the one with smallest length. 91 var writebackSinks = ListBuffer.empty[(Seq[HasWritebackSource], Seq[Int])] 92 def addWritebackSink(source: Seq[HasWritebackSource], index: Option[Seq[Int]] = None): HasWritebackSink = { 93 val realIndex = if (index.isDefined) index.get else Seq.fill(source.length)(0) 94 writebackSinks += ((source, realIndex)) 95 this 96 } 97 98 def writebackSinksParams: Seq[WritebackSourceParams] = { 99 writebackSinks.map{ case (s, i) => s.zip(i).map(x => x._1.writebackSourceParams(x._2)).reduce(_ ++ _) } 100 } 101 final def writebackSinksMod( 102 thisMod: Option[HasWritebackSource] = None, 103 thisModImp: Option[HasWritebackSourceImp] = None 104 ): Seq[Seq[HasWritebackSourceImp]] = { 105 require(thisMod.isDefined == thisModImp.isDefined) 106 writebackSinks.map(_._1.map(source => 107 if (thisMod.isDefined && source == thisMod.get) thisModImp.get else source.writebackSourceImp) 108 ) 109 } 110 final def writebackSinksImp( 111 thisMod: Option[HasWritebackSource] = None, 112 thisModImp: Option[HasWritebackSourceImp] = None 113 ): Seq[Seq[ValidIO[ExuOutput]]] = { 114 val sourceMod = writebackSinksMod(thisMod, thisModImp) 115 writebackSinks.zip(sourceMod).map{ case ((s, i), m) => 116 s.zip(i).zip(m).flatMap(x => x._1._1.writebackSource(x._2)(x._1._2)) 117 } 118 } 119 def selWritebackSinks(func: WritebackSourceParams => Int): Int = { 120 writebackSinksParams.zipWithIndex.minBy(params => func(params._1))._2 121 } 122 def generateWritebackIO( 123 thisMod: Option[HasWritebackSource] = None, 124 thisModImp: Option[HasWritebackSourceImp] = None 125 ): Unit 126} 127 128abstract class XSBundle(implicit val p: Parameters) extends Bundle 129 with HasXSParameter 130 131abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 132 with HasXSParameter with HasExuWbHelper 133{ 134 // interrupt sinks 135 val clint_int_sink = IntSinkNode(IntSinkPortSimple(1, 2)) 136 val debug_int_sink = IntSinkNode(IntSinkPortSimple(1, 1)) 137 val plic_int_sink = IntSinkNode(IntSinkPortSimple(2, 1)) 138 // outer facing nodes 139 val frontend = LazyModule(new Frontend()) 140 val ptw = LazyModule(new L2TLBWrapper()) 141 val ptw_to_l2_buffer = if (!coreParams.softPTW) LazyModule(new TLBuffer) else null 142 val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO())) 143 144 if (!coreParams.softPTW) { 145 ptw_to_l2_buffer.node := ptw.node 146 } 147 148 val wbArbiter = LazyModule(new WbArbiterWrapper(exuConfigs, NRIntWritePorts, NRFpWritePorts)) 149 val intWbPorts = wbArbiter.intWbPorts 150 val fpWbPorts = wbArbiter.fpWbPorts 151 152 // TODO: better RS organization 153 // generate rs according to number of function units 154 require(exuParameters.JmpCnt == 1) 155 require(exuParameters.MduCnt <= exuParameters.AluCnt && exuParameters.MduCnt > 0) 156 require(exuParameters.FmiscCnt <= exuParameters.FmacCnt && exuParameters.FmiscCnt > 0) 157 require(exuParameters.LduCnt == exuParameters.StuCnt) // TODO: remove this limitation 158 159 // one RS every 2 MDUs 160 val schedulePorts = Seq( 161 // exuCfg, numDeq, intFastWakeupTarget, fpFastWakeupTarget 162 Seq( 163 (AluExeUnitCfg, exuParameters.AluCnt, Seq(AluExeUnitCfg, LdExeUnitCfg, StaExeUnitCfg), Seq()), 164 (MulDivExeUnitCfg, exuParameters.MduCnt, Seq(AluExeUnitCfg, MulDivExeUnitCfg), Seq()), 165 (JumpCSRExeUnitCfg, 1, Seq(), Seq()), 166 (LdExeUnitCfg, exuParameters.LduCnt, Seq(AluExeUnitCfg, LdExeUnitCfg), Seq()), 167 (StaExeUnitCfg, exuParameters.StuCnt, Seq(), Seq()), 168 (StdExeUnitCfg, exuParameters.StuCnt, Seq(), Seq()) 169 ), 170 Seq( 171 (FmacExeUnitCfg, exuParameters.FmacCnt, Seq(), Seq(FmacExeUnitCfg, FmiscExeUnitCfg)), 172 (FmiscExeUnitCfg, exuParameters.FmiscCnt, Seq(), Seq()) 173 ) 174 ) 175 176 // should do outer fast wakeup ports here 177 val otherFastPorts = schedulePorts.zipWithIndex.map { case (sche, i) => 178 val otherCfg = schedulePorts.zipWithIndex.filter(_._2 != i).map(_._1).reduce(_ ++ _) 179 val outerPorts = sche.map(cfg => { 180 // exe units from this scheduler need fastUops from exeunits 181 val outerWakeupInSche = sche.filter(_._1.wakeupFromExu) 182 val intraIntScheOuter = outerWakeupInSche.filter(_._3.contains(cfg._1)).map(_._1) 183 val intraFpScheOuter = outerWakeupInSche.filter(_._4.contains(cfg._1)).map(_._1) 184 // exe units from other schedulers need fastUop from outside 185 val otherIntSource = otherCfg.filter(_._3.contains(cfg._1)).map(_._1) 186 val otherFpSource = otherCfg.filter(_._4.contains(cfg._1)).map(_._1) 187 val intSource = findInWbPorts(intWbPorts, intraIntScheOuter ++ otherIntSource) 188 val fpSource = findInWbPorts(fpWbPorts, intraFpScheOuter ++ otherFpSource) 189 getFastWakeupIndex(cfg._1, intSource, fpSource, intWbPorts.length).sorted 190 }) 191 println(s"inter-scheduler wakeup sources for $i: $outerPorts") 192 outerPorts 193 } 194 195 // allow mdu and fmisc to have 2*numDeq enqueue ports 196 val intDpPorts = (0 until exuParameters.AluCnt).map(i => { 197 if (i < exuParameters.JmpCnt) Seq((0, i), (1, i), (2, i)) 198 else if (i < 2 * exuParameters.MduCnt) Seq((0, i), (1, i)) 199 else Seq((0, i)) 200 }) 201 val lsDpPorts = (0 until exuParameters.LduCnt).map(i => Seq((3, i))) ++ 202 (0 until exuParameters.StuCnt).map(i => Seq((4, i))) ++ 203 (0 until exuParameters.StuCnt).map(i => Seq((5, i))) 204 val fpDpPorts = (0 until exuParameters.FmacCnt).map(i => { 205 if (i < 2 * exuParameters.FmiscCnt) Seq((0, i), (1, i)) 206 else Seq((0, i)) 207 }) 208 209 val dispatchPorts = Seq(intDpPorts ++ lsDpPorts, fpDpPorts) 210 211 val outIntRfReadPorts = Seq(0, 0) 212 val outFpRfReadPorts = Seq(0, StorePipelineWidth) 213 val hasIntRf = Seq(true, false) 214 val hasFpRf = Seq(false, true) 215 val exuBlocks = schedulePorts.zip(dispatchPorts).zip(otherFastPorts).zipWithIndex.map { 216 case (((sche, disp), other), i) => 217 LazyModule(new ExuBlock(sche, disp, intWbPorts, fpWbPorts, other, outIntRfReadPorts(i), outFpRfReadPorts(i), hasIntRf(i), hasFpRf(i))) 218 } 219 220 val memBlock = LazyModule(new MemBlock()(p.alter((site, here, up) => { 221 case XSCoreParamsKey => up(XSCoreParamsKey).copy( 222 IssQueSize = exuBlocks.head.scheduler.getMemRsEntries 223 ) 224 }))) 225 226 val wb2Ctrl = LazyModule(new Wb2Ctrl(exuConfigs)) 227 wb2Ctrl.addWritebackSink(exuBlocks :+ memBlock) 228 val dpExuConfigs = exuBlocks.flatMap(_.scheduler.dispatch2.map(_.configs)) 229 val ctrlBlock = LazyModule(new CtrlBlock(dpExuConfigs)) 230 val writebackSources = Seq(Seq(wb2Ctrl), Seq(wbArbiter)) 231 writebackSources.foreach(s => ctrlBlock.addWritebackSink(s)) 232} 233 234class XSCore()(implicit p: config.Parameters) extends XSCoreBase 235 with HasXSDts 236{ 237 lazy val module = new XSCoreImp(this) 238} 239 240class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 241 with HasXSParameter 242 with HasSoCParameter { 243 val io = IO(new Bundle { 244 val hartId = Input(UInt(64.W)) 245 val reset_vector = Input(UInt(PAddrBits.W)) 246 val cpu_halt = Output(Bool()) 247 val l2_pf_enable = Output(Bool()) 248 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)) 249 val beu_errors = Output(new XSL1BusErrors()) 250 }) 251 252 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 253 254 val frontend = outer.frontend.module 255 val ctrlBlock = outer.ctrlBlock.module 256 val wb2Ctrl = outer.wb2Ctrl.module 257 val memBlock = outer.memBlock.module 258 val ptw = outer.ptw.module 259 val ptw_to_l2_buffer = if (!coreParams.softPTW) outer.ptw_to_l2_buffer.module else null 260 val exuBlocks = outer.exuBlocks.map(_.module) 261 262 frontend.io.hartId := io.hartId 263 ctrlBlock.io.hartId := io.hartId 264 exuBlocks.foreach(_.io.hartId := io.hartId) 265 memBlock.io.hartId := io.hartId 266 outer.wbArbiter.module.io.hartId := io.hartId 267 frontend.io.reset_vector := io.reset_vector 268 269 io.cpu_halt := ctrlBlock.io.cpu_halt 270 271 outer.wbArbiter.module.io.redirect <> ctrlBlock.io.redirect 272 val allWriteback = exuBlocks.flatMap(_.io.fuWriteback) ++ memBlock.io.writeback 273 require(exuConfigs.length == allWriteback.length, s"${exuConfigs.length} != ${allWriteback.length}") 274 outer.wbArbiter.module.io.in <> allWriteback 275 val rfWriteback = outer.wbArbiter.module.io.out 276 277 // memblock error exception writeback, 1 cycle after normal writeback 278 wb2Ctrl.io.s3_delayed_load_error <> memBlock.io.s3_delayed_load_error 279 280 wb2Ctrl.io.redirect <> ctrlBlock.io.redirect 281 outer.wb2Ctrl.generateWritebackIO() 282 283 io.beu_errors.icache <> frontend.io.error.toL1BusErrorUnitInfo() 284 io.beu_errors.dcache <> memBlock.io.error.toL1BusErrorUnitInfo() 285 286 require(exuBlocks.count(_.fuConfigs.map(_._1).contains(JumpCSRExeUnitCfg)) == 1) 287 val csrFenceMod = exuBlocks.filter(_.fuConfigs.map(_._1).contains(JumpCSRExeUnitCfg)).head 288 val csrioIn = csrFenceMod.io.fuExtra.csrio.get 289 val fenceio = csrFenceMod.io.fuExtra.fenceio.get 290 291 frontend.io.backend <> ctrlBlock.io.frontend 292 frontend.io.sfence <> fenceio.sfence 293 frontend.io.tlbCsr <> csrioIn.tlb 294 frontend.io.csrCtrl <> csrioIn.customCtrl 295 frontend.io.fencei := fenceio.fencei 296 297 ctrlBlock.io.csrCtrl <> csrioIn.customCtrl 298 val redirectBlocks = exuBlocks.reverse.filter(_.fuConfigs.map(_._1).map(_.hasRedirect).reduce(_ || _)) 299 ctrlBlock.io.exuRedirect <> redirectBlocks.flatMap(_.io.fuExtra.exuRedirect) 300 ctrlBlock.io.stIn <> memBlock.io.stIn 301 ctrlBlock.io.memoryViolation <> memBlock.io.memoryViolation 302 exuBlocks.head.io.scheExtra.enqLsq.get <> memBlock.io.enqLsq 303 exuBlocks.foreach(b => { 304 b.io.scheExtra.lcommit := ctrlBlock.io.robio.lsq.lcommit 305 b.io.scheExtra.scommit := memBlock.io.sqDeq 306 b.io.scheExtra.lqCancelCnt := memBlock.io.lqCancelCnt 307 b.io.scheExtra.sqCancelCnt := memBlock.io.sqCancelCnt 308 }) 309 val sourceModules = outer.writebackSources.map(_.map(_.module.asInstanceOf[HasWritebackSourceImp])) 310 outer.ctrlBlock.generateWritebackIO() 311 312 val allFastUop = exuBlocks.flatMap(b => b.io.fastUopOut.dropRight(b.numOutFu)) ++ memBlock.io.otherFastWakeup 313 require(allFastUop.length == exuConfigs.length, s"${allFastUop.length} != ${exuConfigs.length}") 314 val intFastUop = allFastUop.zip(exuConfigs).filter(_._2.writeIntRf).map(_._1) 315 val fpFastUop = allFastUop.zip(exuConfigs).filter(_._2.writeFpRf).map(_._1) 316 val intFastUop1 = outer.wbArbiter.intConnections.map(c => intFastUop(c.head)) 317 val fpFastUop1 = outer.wbArbiter.fpConnections.map(c => fpFastUop(c.head)) 318 val allFastUop1 = intFastUop1 ++ fpFastUop1 319 320 ctrlBlock.io.dispatch <> exuBlocks.flatMap(_.io.in) 321 ctrlBlock.io.rsReady := exuBlocks.flatMap(_.io.scheExtra.rsReady) 322 ctrlBlock.io.enqLsq <> memBlock.io.enqLsq 323 ctrlBlock.io.sqDeq := memBlock.io.sqDeq 324 ctrlBlock.io.lqCancelCnt := memBlock.io.lqCancelCnt 325 ctrlBlock.io.sqCancelCnt := memBlock.io.sqCancelCnt 326 327 exuBlocks(0).io.scheExtra.fpRfReadIn.get <> exuBlocks(1).io.scheExtra.fpRfReadOut.get 328 exuBlocks(0).io.scheExtra.fpStateReadIn.get <> exuBlocks(1).io.scheExtra.fpStateReadOut.get 329 330 memBlock.io.issue <> exuBlocks(0).io.issue.get 331 // By default, instructions do not have exceptions when they enter the function units. 332 memBlock.io.issue.map(_.bits.uop.clearExceptions()) 333 exuBlocks(0).io.scheExtra.loadFastMatch.get <> memBlock.io.loadFastMatch 334 exuBlocks(0).io.scheExtra.loadFastImm.get <> memBlock.io.loadFastImm 335 336 val stdIssue = exuBlocks(0).io.issue.get.takeRight(exuParameters.StuCnt) 337 exuBlocks.map(_.io).foreach { exu => 338 exu.redirect <> ctrlBlock.io.redirect 339 exu.allocPregs <> ctrlBlock.io.allocPregs 340 exu.rfWriteback <> rfWriteback 341 exu.fastUopIn <> allFastUop1 342 exu.scheExtra.jumpPc <> ctrlBlock.io.jumpPc 343 exu.scheExtra.jalr_target <> ctrlBlock.io.jalr_target 344 exu.scheExtra.stIssuePtr <> memBlock.io.stIssuePtr 345 exu.scheExtra.debug_fp_rat <> ctrlBlock.io.debug_fp_rat 346 exu.scheExtra.debug_int_rat <> ctrlBlock.io.debug_int_rat 347 exu.scheExtra.lqFull := memBlock.io.lqFull 348 exu.scheExtra.sqFull := memBlock.io.sqFull 349 exu.scheExtra.memWaitUpdateReq.staIssue.zip(memBlock.io.stIn).foreach{case (sink, src) => { 350 sink.bits := src.bits 351 sink.valid := src.valid 352 }} 353 exu.scheExtra.memWaitUpdateReq.stdIssue.zip(stdIssue).foreach{case (sink, src) => { 354 sink.valid := src.valid 355 sink.bits := src.bits 356 }} 357 } 358 XSPerfHistogram("fastIn_count", PopCount(allFastUop1.map(_.valid)), true.B, 0, allFastUop1.length, 1) 359 XSPerfHistogram("wakeup_count", PopCount(rfWriteback.map(_.valid)), true.B, 0, rfWriteback.length, 1) 360 361 ctrlBlock.perfinfo.perfEventsEu0 := exuBlocks(0).getPerf.dropRight(outer.exuBlocks(0).scheduler.numRs) 362 ctrlBlock.perfinfo.perfEventsEu1 := exuBlocks(1).getPerf.dropRight(outer.exuBlocks(1).scheduler.numRs) 363 if (!coreParams.softPTW) { 364 memBlock.io.perfEventsPTW := ptw.getPerf 365 } else { 366 memBlock.io.perfEventsPTW := DontCare 367 } 368 ctrlBlock.perfinfo.perfEventsRs := outer.exuBlocks.flatMap(b => b.module.getPerf.takeRight(b.scheduler.numRs)) 369 370 csrioIn.hartId <> io.hartId 371 csrioIn.perf <> DontCare 372 csrioIn.perf.retiredInstr <> ctrlBlock.io.robio.toCSR.perfinfo.retiredInstr 373 csrioIn.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 374 csrioIn.perf.memInfo <> memBlock.io.memInfo 375 csrioIn.perf.frontendInfo <> frontend.io.frontendInfo 376 377 csrioIn.perf.perfEventsFrontend <> frontend.getPerf 378 csrioIn.perf.perfEventsCtrl <> ctrlBlock.getPerf 379 csrioIn.perf.perfEventsLsu <> memBlock.getPerf 380 csrioIn.perf.perfEventsHc <> io.perfEvents 381 382 csrioIn.fpu.fflags <> ctrlBlock.io.robio.toCSR.fflags 383 csrioIn.fpu.isIllegal := false.B 384 csrioIn.fpu.dirty_fs <> ctrlBlock.io.robio.toCSR.dirty_fs 385 csrioIn.fpu.frm <> exuBlocks(1).io.fuExtra.frm.get 386 csrioIn.exception <> ctrlBlock.io.robio.exception 387 csrioIn.isXRet <> ctrlBlock.io.robio.toCSR.isXRet 388 csrioIn.trapTarget <> ctrlBlock.io.robio.toCSR.trapTarget 389 csrioIn.interrupt <> ctrlBlock.io.robio.toCSR.intrBitSet 390 csrioIn.wfi_event <> ctrlBlock.io.robio.toCSR.wfiEvent 391 csrioIn.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 392 393 csrioIn.externalInterrupt.msip := outer.clint_int_sink.in.head._1(0) 394 csrioIn.externalInterrupt.mtip := outer.clint_int_sink.in.head._1(1) 395 csrioIn.externalInterrupt.meip := outer.plic_int_sink.in.head._1(0) 396 csrioIn.externalInterrupt.seip := outer.plic_int_sink.in.last._1(0) 397 csrioIn.externalInterrupt.debug := outer.debug_int_sink.in.head._1(0) 398 399 csrioIn.distributedUpdate(0).w.valid := memBlock.io.csrUpdate.w.valid 400 csrioIn.distributedUpdate(0).w.bits := memBlock.io.csrUpdate.w.bits 401 csrioIn.distributedUpdate(1).w.valid := frontend.io.csrUpdate.w.valid 402 csrioIn.distributedUpdate(1).w.bits := frontend.io.csrUpdate.w.bits 403 404 fenceio.sfence <> memBlock.io.sfence 405 fenceio.sbuffer <> memBlock.io.fenceToSbuffer 406 407 memBlock.io.redirect <> ctrlBlock.io.redirect 408 memBlock.io.rsfeedback <> exuBlocks(0).io.scheExtra.feedback.get 409 memBlock.io.csrCtrl <> csrioIn.customCtrl 410 memBlock.io.tlbCsr <> csrioIn.tlb 411 memBlock.io.lsqio.rob <> ctrlBlock.io.robio.lsq 412 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.uop.ctrl.commitType) 413 414 val itlbRepeater1 = PTWFilter(itlbParams.fenceDelay,frontend.io.ptw, fenceio.sfence, csrioIn.tlb, l2tlbParams.ifilterSize) 415 val itlbRepeater2 = PTWRepeaterNB(passReady = false, itlbParams.fenceDelay, itlbRepeater1.io.ptw, ptw.io.tlb(0), fenceio.sfence, csrioIn.tlb) 416 val dtlbRepeater1 = PTWFilter(ldtlbParams.fenceDelay, memBlock.io.ptw, fenceio.sfence, csrioIn.tlb, l2tlbParams.dfilterSize) 417 val dtlbRepeater2 = PTWRepeaterNB(passReady = false, ldtlbParams.fenceDelay, dtlbRepeater1.io.ptw, ptw.io.tlb(1), fenceio.sfence, csrioIn.tlb) 418 ptw.io.sfence <> fenceio.sfence 419 ptw.io.csr.tlb <> csrioIn.tlb 420 ptw.io.csr.distribute_csr <> csrioIn.customCtrl.distribute_csr 421 422 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 423 io.l2_pf_enable := csrioIn.customCtrl.l2_pf_enable 424 425 // Modules are reset one by one 426 val resetTree = ResetGenNode( 427 Seq( 428 ModuleNode(memBlock), ModuleNode(dtlbRepeater1), 429 ResetGenNode(Seq( 430 ModuleNode(itlbRepeater2), 431 ModuleNode(ptw), 432 ModuleNode(dtlbRepeater2), 433 ModuleNode(ptw_to_l2_buffer), 434 )), 435 ResetGenNode(Seq( 436 ModuleNode(exuBlocks.head), 437 ResetGenNode( 438 exuBlocks.tail.map(m => ModuleNode(m)) :+ ModuleNode(outer.wbArbiter.module) 439 ), 440 ResetGenNode(Seq( 441 ModuleNode(ctrlBlock), 442 ResetGenNode(Seq( 443 ModuleNode(frontend), ModuleNode(itlbRepeater1) 444 )) 445 )) 446 )) 447 ) 448 ) 449 450 ResetGen(resetTree, reset, !debugOpts.FPGAPlatform) 451 452} 453