xref: /XiangShan/src/main/scala/xiangshan/XSCore.scala (revision 53c7ab8b2e79de0fa70909ea81a51720f666aaeb) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import top.Parameters
6import xiangshan.backend._
7import xiangshan.backend.dispatch.DispatchParameters
8import xiangshan.backend.exu.ExuParameters
9import xiangshan.backend.exu.Exu._
10import xiangshan.frontend._
11import xiangshan.mem._
12import xiangshan.backend.fu.HasExceptionNO
13import xiangshan.cache.{DCache,InstrUncache, DCacheParameters, ICache, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, PTWRepeater, Uncache, MemoryOpConstants, MissReq}
14import xiangshan.cache.prefetch._
15import chipsalliance.rocketchip.config
16import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp}
17import freechips.rocketchip.tilelink.{TLBuffer, TLBundleParameters, TLCacheCork, TLClientNode, TLFilter, TLIdentityNode, TLToAXI4, TLWidthWidget, TLXbar}
18import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError}
19import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters}
20import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4IdentityNode, AXI4ToTL, AXI4UserYanker}
21import freechips.rocketchip.tile.HasFPUParameters
22import sifive.blocks.inclusivecache.PrefetcherIO
23import utils._
24
25object hartIdCore extends (() => Int) {
26  var x = 0
27  def apply(): Int = {
28    x = x + 1
29    x-1
30  }
31}
32
33case class XSCoreParameters
34(
35  XLEN: Int = 64,
36  HasMExtension: Boolean = true,
37  HasCExtension: Boolean = true,
38  HasDiv: Boolean = true,
39  HasICache: Boolean = true,
40  HasDCache: Boolean = true,
41  EnableStoreQueue: Boolean = true,
42  AddrBits: Int = 64,
43  VAddrBits: Int = 39,
44  PAddrBits: Int = 40,
45  HasFPU: Boolean = true,
46  FectchWidth: Int = 8,
47  EnableBPU: Boolean = true,
48  EnableBPD: Boolean = true,
49  EnableRAS: Boolean = true,
50  EnableLB: Boolean = false,
51  EnableLoop: Boolean = false,
52  EnableSC: Boolean = false,
53  EnableJal: Boolean = false,
54  EnableUBTB: Boolean = true,
55  HistoryLength: Int = 64,
56  BtbSize: Int = 2048,
57  JbtacSize: Int = 1024,
58  JbtacBanks: Int = 8,
59  RasSize: Int = 16,
60  CacheLineSize: Int = 512,
61  UBtbWays: Int = 16,
62  BtbWays: Int = 2,
63
64  EnableL1plusPrefetcher: Boolean = true,
65  IBufSize: Int = 32,
66  DecodeWidth: Int = 6,
67  RenameWidth: Int = 6,
68  CommitWidth: Int = 6,
69  BrqSize: Int = 32,
70  FtqSize: Int = 48,
71  IssQueSize: Int = 12,
72  NRPhyRegs: Int = 160,
73  NRIntReadPorts: Int = 14,
74  NRIntWritePorts: Int = 8,
75  NRFpReadPorts: Int = 14,
76  NRFpWritePorts: Int = 8,
77  LoadQueueSize: Int = 64,
78  StoreQueueSize: Int = 48,
79  RoqSize: Int = 192,
80  dpParams: DispatchParameters = DispatchParameters(
81    IntDqSize = 32,
82    FpDqSize = 32,
83    LsDqSize = 32,
84    IntDqDeqWidth = 4,
85    FpDqDeqWidth = 4,
86    LsDqDeqWidth = 4
87  ),
88  exuParameters: ExuParameters = ExuParameters(
89    JmpCnt = 1,
90    AluCnt = 4,
91    MulCnt = 0,
92    MduCnt = 2,
93    FmacCnt = 4,
94    FmiscCnt = 2,
95    FmiscDivSqrtCnt = 0,
96    LduCnt = 2,
97    StuCnt = 2
98  ),
99  LoadPipelineWidth: Int = 2,
100  StorePipelineWidth: Int = 2,
101  StoreBufferSize: Int = 16,
102  RefillSize: Int = 512,
103  TlbEntrySize: Int = 32,
104  TlbSPEntrySize: Int = 4,
105  TlbL2EntrySize: Int = 256, // or 512
106  TlbL2SPEntrySize: Int = 16,
107  PtwL1EntrySize: Int = 16,
108  PtwL2EntrySize: Int = 256,
109  NumPerfCounters: Int = 16,
110  NrExtIntr: Int = 1
111)
112
113trait HasXSParameter {
114
115  val core = Parameters.get.coreParameters
116  val env = Parameters.get.envParameters
117
118  val XLEN = 64
119  val minFLen = 32
120  val fLen = 64
121  def xLen = 64
122  val HasMExtension = core.HasMExtension
123  val HasCExtension = core.HasCExtension
124  val HasDiv = core.HasDiv
125  val HasIcache = core.HasICache
126  val HasDcache = core.HasDCache
127  val EnableStoreQueue = core.EnableStoreQueue
128  val AddrBits = core.AddrBits // AddrBits is used in some cases
129  val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits
130  val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits
131  val AddrBytes = AddrBits / 8 // unused
132  val DataBits = XLEN
133  val DataBytes = DataBits / 8
134  val HasFPU = core.HasFPU
135  val FetchWidth = core.FectchWidth
136  val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1)
137  val EnableBPU = core.EnableBPU
138  val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3
139  val EnableRAS = core.EnableRAS
140  val EnableLB = core.EnableLB
141  val EnableLoop = core.EnableLoop
142  val EnableSC = core.EnableSC
143  val HistoryLength = core.HistoryLength
144  val BtbSize = core.BtbSize
145  // val BtbWays = 4
146  val BtbBanks = PredictWidth
147  // val BtbSets = BtbSize / BtbWays
148  val JbtacSize = core.JbtacSize
149  val JbtacBanks = core.JbtacBanks
150  val RasSize = core.RasSize
151  val CacheLineSize = core.CacheLineSize
152  val CacheLineHalfWord = CacheLineSize / 16
153  val ExtHistoryLength = HistoryLength + 64
154  val UBtbWays = core.UBtbWays
155  val BtbWays = core.BtbWays
156  val EnableL1plusPrefetcher = core.EnableL1plusPrefetcher
157  val IBufSize = core.IBufSize
158  val DecodeWidth = core.DecodeWidth
159  val RenameWidth = core.RenameWidth
160  val CommitWidth = core.CommitWidth
161  val BrqSize = core.BrqSize
162  val FtqSize = core.FtqSize
163  val IssQueSize = core.IssQueSize
164  val BrTagWidth = log2Up(BrqSize)
165  val NRPhyRegs = core.NRPhyRegs
166  val PhyRegIdxWidth = log2Up(NRPhyRegs)
167  val RoqSize = core.RoqSize
168  val LoadQueueSize = core.LoadQueueSize
169  val StoreQueueSize = core.StoreQueueSize
170  val dpParams = core.dpParams
171  val exuParameters = core.exuParameters
172  val NRIntReadPorts = core.NRIntReadPorts
173  val NRIntWritePorts = core.NRIntWritePorts
174  val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt
175  val NRFpReadPorts = core.NRFpReadPorts
176  val NRFpWritePorts = core.NRFpWritePorts
177  val LoadPipelineWidth = core.LoadPipelineWidth
178  val StorePipelineWidth = core.StorePipelineWidth
179  val StoreBufferSize = core.StoreBufferSize
180  val RefillSize = core.RefillSize
181  val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth
182  val TlbEntrySize = core.TlbEntrySize
183  val TlbSPEntrySize = core.TlbSPEntrySize
184  val TlbL2EntrySize = core.TlbL2EntrySize
185  val TlbL2SPEntrySize = core.TlbL2SPEntrySize
186  val PtwL1EntrySize = core.PtwL1EntrySize
187  val PtwL2EntrySize = core.PtwL2EntrySize
188  val NumPerfCounters = core.NumPerfCounters
189  val NrExtIntr = core.NrExtIntr
190
191  val instBytes = if (HasCExtension) 2 else 4
192  val instOffsetBits = log2Ceil(instBytes)
193
194  val icacheParameters = ICacheParameters(
195    tagECC = Some("parity"),
196    dataECC = Some("parity"),
197    replacer = Some("setlru"),
198    nMissEntries = 2
199  )
200
201  val l1plusCacheParameters = L1plusCacheParameters(
202    tagECC = Some("secded"),
203    dataECC = Some("secded"),
204    nMissEntries = 8
205  )
206
207  val dcacheParameters = DCacheParameters(
208    tagECC = Some("secded"),
209    dataECC = Some("secded"),
210    nMissEntries = 16,
211    nProbeEntries = 16,
212    nReleaseEntries = 16,
213    nStoreReplayEntries = 16
214  )
215
216  val LRSCCycles = 100
217
218
219  // cache hierarchy configurations
220  val l1BusDataWidth = 256
221
222  // L2 configurations
223  val L1BusWidth = 256
224  val L2Size = 512 * 1024 // 512KB
225  val L2BlockSize = 64
226  val L2NWays = 8
227  val L2NSets = L2Size / L2BlockSize / L2NWays
228
229  // L3 configurations
230  val L2BusWidth = 256
231  val L3Size = 4 * 1024 * 1024 // 4MB
232  val L3BlockSize = 64
233  val L3NBanks = 4
234  val L3NWays = 8
235  val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays
236
237  // on chip network configurations
238  val L3BusWidth = 256
239
240  // icache prefetcher
241  val l1plusPrefetcherParameters = L1plusPrefetcherParameters(
242    enable = true,
243    _type = "stream",
244    streamParams = StreamPrefetchParameters(
245      streamCnt = 2,
246      streamSize = 4,
247      ageWidth = 4,
248      blockBytes = l1plusCacheParameters.blockBytes,
249      reallocStreamOnMissInstantly = true,
250      cacheName = "icache"
251    )
252  )
253
254  // dcache prefetcher
255  val l2PrefetcherParameters = L2PrefetcherParameters(
256    enable = true,
257    _type = "bop",// "stream" or "bop"
258    streamParams = StreamPrefetchParameters(
259      streamCnt = 4,
260      streamSize = 4,
261      ageWidth = 4,
262      blockBytes = L2BlockSize,
263      reallocStreamOnMissInstantly = true,
264      cacheName = "dcache"
265    ),
266    bopParams = BOPParameters(
267      rrTableEntries = 256,
268      rrTagBits = 12,
269      scoreBits = 5,
270      roundMax = 50,
271      badScore = 1,
272      blockBytes = L2BlockSize,
273      nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large
274    ),
275  )
276}
277
278trait HasXSLog { this: RawModule =>
279  implicit val moduleName: String = this.name
280}
281
282abstract class XSModule extends MultiIOModule
283  with HasXSParameter
284  with HasExceptionNO
285  with HasXSLog
286  with HasFPUParameters
287{
288  def io: Record
289}
290
291//remove this trait after impl module logic
292trait NeedImpl { this: RawModule =>
293  override protected def IO[T <: Data](iodef: T): T = {
294    println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module")
295    val io = chisel3.experimental.IO(iodef)
296    io <> DontCare
297    io
298  }
299}
300
301abstract class XSBundle extends Bundle
302  with HasXSParameter
303
304case class EnviromentParameters
305(
306  FPGAPlatform: Boolean = true,
307  EnableDebug: Boolean = false,
308  EnablePerfDebug: Boolean = false,
309  DualCoreDifftest: Boolean = false
310)
311
312// object AddressSpace extends HasXSParameter {
313//   // (start, size)
314//   // address out of MMIO will be considered as DRAM
315//   def mmio = List(
316//     (0x00000000L, 0x40000000L),  // internal devices, such as CLINT and PLIC
317//     (0x40000000L, 0x40000000L)   // external devices
318//   )
319
320//   def isMMIO(addr: UInt): Bool = mmio.map(range => {
321//     require(isPow2(range._2))
322//     val bits = log2Up(range._2)
323//     (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U
324//   }).reduce(_ || _)
325// }
326
327
328
329class XSCore()(implicit p: config.Parameters) extends LazyModule
330  with HasXSParameter
331  with HasExeBlockHelper
332{
333
334  // to fast wake up fp, mem rs
335  val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter)
336  val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter)
337  val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter)
338  val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter)
339
340  val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter)
341  val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter)
342  val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter)
343  val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter)
344
345  // outer facing nodes
346  val frontend = LazyModule(new Frontend())
347  val l1pluscache = LazyModule(new L1plusCache())
348  val ptw = LazyModule(new PTW())
349  val l2Prefetcher = LazyModule(new L2Prefetcher())
350  val memBlock = LazyModule(new MemBlock(
351    fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp,
352    slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp,
353    fastFpOut = Seq(),
354    slowFpOut = loadExuConfigs,
355    fastIntOut = Seq(),
356    slowIntOut = loadExuConfigs
357  ))
358
359  lazy val module = new XSCoreImp(this)
360}
361
362class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
363  with HasXSParameter
364  with HasExeBlockHelper
365{
366  val io = IO(new Bundle {
367    val externalInterrupt = new ExternalInterruptIO
368    val l2ToPrefetcher = Flipped(new PrefetcherIO(PAddrBits))
369  })
370
371  val difftestIO = IO(new DifftestBundle())
372  difftestIO <> DontCare
373
374  val trapIO = IO(new TrapIO())
375  trapIO <> DontCare
376
377  println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}")
378  AddressSpace.printMemmap()
379
380  // to fast wake up fp, mem rs
381  val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter)
382  val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter)
383  val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter)
384  val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter)
385
386  val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter)
387  val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter)
388  val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter)
389  val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter)
390
391  val ctrlBlock = Module(new CtrlBlock)
392  val integerBlock = Module(new IntegerBlock(
393    fastWakeUpIn = fpBlockFastWakeUpInt,
394    slowWakeUpIn = fpBlockSlowWakeUpInt ++ loadExuConfigs,
395    fastFpOut = intBlockFastWakeUpFp,
396    slowFpOut = intBlockSlowWakeUpFp,
397    fastIntOut = intBlockFastWakeUpInt,
398    slowIntOut = intBlockSlowWakeUpInt
399  ))
400  val floatBlock = Module(new FloatBlock(
401    fastWakeUpIn = intBlockFastWakeUpFp,
402    slowWakeUpIn = intBlockSlowWakeUpFp ++ loadExuConfigs,
403    fastFpOut = fpBlockFastWakeUpFp,
404    slowFpOut = fpBlockSlowWakeUpFp,
405    fastIntOut = fpBlockFastWakeUpInt,
406    slowIntOut = fpBlockSlowWakeUpInt
407  ))
408
409  val frontend = outer.frontend.module
410  val memBlock = outer.memBlock.module
411  val l1pluscache = outer.l1pluscache.module
412  val ptw = outer.ptw.module
413  val l2Prefetcher = outer.l2Prefetcher.module
414
415  frontend.io.backend <> ctrlBlock.io.frontend
416  frontend.io.sfence <> integerBlock.io.fenceio.sfence
417  frontend.io.tlbCsr := RegNext(integerBlock.io.csrio.tlb)
418
419  frontend.io.icacheMemAcq <> l1pluscache.io.req
420  l1pluscache.io.resp <> frontend.io.icacheMemGrant
421  l1pluscache.io.flush := frontend.io.l1plusFlush
422  frontend.io.fencei := integerBlock.io.fenceio.fencei
423
424  ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock
425  ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock
426  ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock
427  ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock
428  ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock
429  ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock
430
431  integerBlock.io.wakeUpIn.fastUops <> floatBlock.io.wakeUpIntOut.fastUops
432  integerBlock.io.wakeUpIn.fast <> floatBlock.io.wakeUpIntOut.fast
433  integerBlock.io.wakeUpIn.slow <> floatBlock.io.wakeUpIntOut.slow ++ memBlock.io.wakeUpIntOut.slow
434  integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock
435
436  floatBlock.io.wakeUpIn.fastUops <> integerBlock.io.wakeUpFpOut.fastUops
437  floatBlock.io.wakeUpIn.fast <> integerBlock.io.wakeUpFpOut.fast
438  floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlock.io.wakeUpFpOut.slow
439  floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock
440
441
442  integerBlock.io.wakeUpIntOut.fast.map(_.ready := true.B)
443  integerBlock.io.wakeUpIntOut.slow.map(_.ready := true.B)
444  floatBlock.io.wakeUpFpOut.fast.map(_.ready := true.B)
445  floatBlock.io.wakeUpFpOut.slow.map(_.ready := true.B)
446
447  val wakeUpMem = Seq(
448    integerBlock.io.wakeUpIntOut,
449    integerBlock.io.wakeUpFpOut,
450    floatBlock.io.wakeUpIntOut,
451    floatBlock.io.wakeUpFpOut
452  )
453  memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops)
454  memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(w => w.fast.map(f => {
455	val raw = WireInit(f)
456	raw
457  }))
458  memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(w => w.slow.map(s => {
459	val raw = WireInit(s)
460	raw
461  }))
462
463  integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags
464  integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs
465  integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception
466  integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget
467  integerBlock.io.csrio.isXRet <> ctrlBlock.io.roqio.toCSR.isXRet
468  integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet
469  integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr
470  integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt
471  integerBlock.io.csrio.perfinfo <> ctrlBlock.io.roqio.toCSR.perfinfo
472  integerBlock.io.fenceio.sfence <> memBlock.io.sfence
473  integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer
474  memBlock.io.tlbCsr := RegNext(integerBlock.io.csrio.tlb)
475
476  floatBlock.io.frm <> integerBlock.io.csrio.frm
477
478  memBlock.io.lsqio.roq <> ctrlBlock.io.roqio.lsq
479  memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.uop.lqIdx
480  memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.uop.sqIdx
481  memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.uop.ctrl.commitType)
482
483  val itlbRepester = Module(new PTWRepeater())
484  val dtlbRepester = Module(new PTWRepeater())
485  itlbRepester.io.tlb <> frontend.io.ptw
486  dtlbRepester.io.tlb <> memBlock.io.ptw
487  itlbRepester.io.sfence <> integerBlock.io.fenceio.sfence
488  dtlbRepester.io.sfence <> integerBlock.io.fenceio.sfence
489  ptw.io.tlb(0) <> dtlbRepester.io.ptw
490  ptw.io.tlb(1) <> itlbRepester.io.ptw
491  ptw.io.sfence <> integerBlock.io.fenceio.sfence
492  ptw.io.csr    <> integerBlock.io.csrio.tlb
493
494  val l2PrefetcherIn = Wire(Decoupled(new MissReq))
495  if (l2PrefetcherParameters.enable && l2PrefetcherParameters._type == "bop") {
496    l2PrefetcherIn.valid := io.l2ToPrefetcher.acquire.valid
497    l2PrefetcherIn.bits := DontCare
498    l2PrefetcherIn.bits.addr := io.l2ToPrefetcher.acquire.bits.address
499    l2PrefetcherIn.bits.cmd := Mux(io.l2ToPrefetcher.acquire.bits.write, MemoryOpConstants.M_XWR, MemoryOpConstants.M_XRD)
500  } else {
501    l2PrefetcherIn <> memBlock.io.toDCachePrefetch
502  }
503  l2Prefetcher.io.in <> l2PrefetcherIn
504
505  if (!env.FPGAPlatform) {
506    val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
507    ExcitingUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG", ExcitingUtils.Debug)
508    ExcitingUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG", ExcitingUtils.Debug)
509    val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
510    ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug)
511  }
512
513  if (env.DualCoreDifftest) {
514    val id = hartIdCore()
515    difftestIO.fromSbuffer <> memBlock.difftestIO.fromSbuffer
516    difftestIO.fromSQ <> memBlock.difftestIO.fromSQ
517    difftestIO.fromCSR <> integerBlock.difftestIO.fromCSR
518    difftestIO.fromRoq <> ctrlBlock.difftestIO.fromRoq
519    trapIO <> ctrlBlock.trapIO
520
521    val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
522    ExcitingUtils.addSink(debugIntReg, s"DEBUG_INT_ARCH_REG$id", ExcitingUtils.Debug)
523    ExcitingUtils.addSink(debugFpReg, s"DEBUG_FP_ARCH_REG$id", ExcitingUtils.Debug)
524    val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
525    difftestIO.fromXSCore.r := debugArchReg
526  }
527
528}
529