1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.frontend._ 10import xiangshan.mem._ 11import xiangshan.backend.fu.HasExceptionNO 12import xiangshan.cache.{ICache, DCache, L1plusCache, DCacheParameters, ICacheParameters, L1plusCacheParameters, PTW, Uncache} 13import chipsalliance.rocketchip.config 14import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 15import freechips.rocketchip.tilelink.{TLBundleParameters, TLCacheCork, TLBuffer, TLClientNode, TLIdentityNode, TLXbar} 16import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 17import utils._ 18 19case class XSCoreParameters 20( 21 XLEN: Int = 64, 22 HasMExtension: Boolean = true, 23 HasCExtension: Boolean = true, 24 HasDiv: Boolean = true, 25 HasICache: Boolean = true, 26 HasDCache: Boolean = true, 27 EnableStoreQueue: Boolean = true, 28 AddrBits: Int = 64, 29 VAddrBits: Int = 39, 30 PAddrBits: Int = 40, 31 HasFPU: Boolean = true, 32 FectchWidth: Int = 8, 33 EnableBPU: Boolean = true, 34 EnableBPD: Boolean = true, 35 EnableRAS: Boolean = true, 36 EnableLB: Boolean = true, 37 EnableLoop: Boolean = false, 38 EnableSC: Boolean = true, 39 HistoryLength: Int = 64, 40 BtbSize: Int = 2048, 41 JbtacSize: Int = 1024, 42 JbtacBanks: Int = 8, 43 RasSize: Int = 16, 44 CacheLineSize: Int = 512, 45 UBtbWays: Int = 16, 46 BtbWays: Int = 2, 47 IBufSize: Int = 64, 48 DecodeWidth: Int = 6, 49 RenameWidth: Int = 6, 50 CommitWidth: Int = 6, 51 BrqSize: Int = 12, 52 IssQueSize: Int = 8, 53 NRPhyRegs: Int = 128, 54 NRIntReadPorts: Int = 14, 55 NRIntWritePorts: Int = 8, 56 NRFpReadPorts: Int = 14, 57 NRFpWritePorts: Int = 8, 58 EnableUnifiedLSQ: Boolean = false, 59 LsroqSize: Int = 16, 60 LoadQueueSize: Int = 12, 61 StoreQueueSize: Int = 10, 62 RoqSize: Int = 32, 63 dpParams: DispatchParameters = DispatchParameters( 64 DqEnqWidth = 4, 65 IntDqSize = 24, 66 FpDqSize = 16, 67 LsDqSize = 16, 68 IntDqDeqWidth = 4, 69 FpDqDeqWidth = 4, 70 LsDqDeqWidth = 4, 71 IntDqReplayWidth = 4, 72 FpDqReplayWidth = 4, 73 LsDqReplayWidth = 4 74 ), 75 exuParameters: ExuParameters = ExuParameters( 76 JmpCnt = 1, 77 AluCnt = 4, 78 MulCnt = 0, 79 MduCnt = 2, 80 FmacCnt = 4, 81 FmiscCnt = 2, 82 FmiscDivSqrtCnt = 0, 83 LduCnt = 2, 84 StuCnt = 2 85 ), 86 LoadPipelineWidth: Int = 2, 87 StorePipelineWidth: Int = 2, 88 StoreBufferSize: Int = 16, 89 RefillSize: Int = 512, 90 TlbEntrySize: Int = 32, 91 TlbL2EntrySize: Int = 256, // or 512 92 PtwL1EntrySize: Int = 16, 93 PtwL2EntrySize: Int = 256, 94 NumPerfCounters: Int = 16 95) 96 97trait HasXSParameter { 98 99 val core = Parameters.get.coreParameters 100 val env = Parameters.get.envParameters 101 102 val XLEN = core.XLEN 103 val HasMExtension = core.HasMExtension 104 val HasCExtension = core.HasCExtension 105 val HasDiv = core.HasDiv 106 val HasIcache = core.HasICache 107 val HasDcache = core.HasDCache 108 val EnableStoreQueue = core.EnableStoreQueue 109 val AddrBits = core.AddrBits // AddrBits is used in some cases 110 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 111 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 112 val AddrBytes = AddrBits / 8 // unused 113 val DataBits = XLEN 114 val DataBytes = DataBits / 8 115 val HasFPU = core.HasFPU 116 val FetchWidth = core.FectchWidth 117 val PredictWidth = FetchWidth * 2 118 val EnableBPU = core.EnableBPU 119 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 120 val EnableRAS = core.EnableRAS 121 val EnableLB = core.EnableLB 122 val EnableLoop = core.EnableLoop 123 val EnableSC = core.EnableSC 124 val HistoryLength = core.HistoryLength 125 val BtbSize = core.BtbSize 126 // val BtbWays = 4 127 val BtbBanks = PredictWidth 128 // val BtbSets = BtbSize / BtbWays 129 val JbtacSize = core.JbtacSize 130 val JbtacBanks = core.JbtacBanks 131 val RasSize = core.RasSize 132 val CacheLineSize = core.CacheLineSize 133 val CacheLineHalfWord = CacheLineSize / 16 134 val ExtHistoryLength = HistoryLength + 64 135 val UBtbWays = core.UBtbWays 136 val BtbWays = core.BtbWays 137 val IBufSize = core.IBufSize 138 val DecodeWidth = core.DecodeWidth 139 val RenameWidth = core.RenameWidth 140 val CommitWidth = core.CommitWidth 141 val BrqSize = core.BrqSize 142 val IssQueSize = core.IssQueSize 143 val BrTagWidth = log2Up(BrqSize) 144 val NRPhyRegs = core.NRPhyRegs 145 val PhyRegIdxWidth = log2Up(NRPhyRegs) 146 val RoqSize = core.RoqSize 147 val EnableUnifiedLSQ = core.EnableUnifiedLSQ 148 val LsroqSize = core.LsroqSize // 64 149 val InnerLsroqIdxWidth = log2Up(LsroqSize) 150 val LsroqIdxWidth = InnerLsroqIdxWidth + 1 151 val LoadQueueSize = core.LoadQueueSize 152 val StoreQueueSize = core.StoreQueueSize 153 val dpParams = core.dpParams 154 val ReplayWidth = dpParams.IntDqReplayWidth + dpParams.FpDqReplayWidth + dpParams.LsDqReplayWidth 155 val exuParameters = core.exuParameters 156 val NRIntReadPorts = core.NRIntReadPorts 157 val NRIntWritePorts = core.NRIntWritePorts 158 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 159 val NRFpReadPorts = core.NRFpReadPorts 160 val NRFpWritePorts = core.NRFpWritePorts 161 val LoadPipelineWidth = core.LoadPipelineWidth 162 val StorePipelineWidth = core.StorePipelineWidth 163 val StoreBufferSize = core.StoreBufferSize 164 val RefillSize = core.RefillSize 165 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 166 val TlbEntrySize = core.TlbEntrySize 167 val TlbL2EntrySize = core.TlbL2EntrySize 168 val PtwL1EntrySize = core.PtwL1EntrySize 169 val PtwL2EntrySize = core.PtwL2EntrySize 170 val NumPerfCounters = core.NumPerfCounters 171 172 val l1BusDataWidth = 256 173 174 val icacheParameters = ICacheParameters( 175 nMissEntries = 2 176 ) 177 178 val l1plusCacheParameters = L1plusCacheParameters( 179 tagECC = Some("secded"), 180 dataECC = Some("secded"), 181 nMissEntries = 8 182 ) 183 184 val dcacheParameters = DCacheParameters( 185 tagECC = Some("secded"), 186 dataECC = Some("secded"), 187 nMissEntries = 16, 188 nLoadMissEntries = 8, 189 nStoreMissEntries = 8 190 ) 191 192 val LRSCCycles = 100 193} 194 195trait HasXSLog { this: RawModule => 196 implicit val moduleName: String = this.name 197} 198 199abstract class XSModule extends MultiIOModule 200 with HasXSParameter 201 with HasExceptionNO 202 with HasXSLog 203{ 204 def io: Record 205} 206 207//remove this trait after impl module logic 208trait NeedImpl { this: RawModule => 209 override protected def IO[T <: Data](iodef: T): T = { 210 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 211 val io = chisel3.experimental.IO(iodef) 212 io <> DontCare 213 io 214 } 215} 216 217abstract class XSBundle extends Bundle 218 with HasXSParameter 219 220case class EnviromentParameters 221( 222 FPGAPlatform: Boolean = true, 223 EnableDebug: Boolean = false 224) 225 226object AddressSpace extends HasXSParameter { 227 // (start, size) 228 // address out of MMIO will be considered as DRAM 229 def mmio = List( 230 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 231 (0x40000000L, 0x40000000L) // external devices 232 ) 233 234 def isMMIO(addr: UInt): Bool = mmio.map(range => { 235 require(isPow2(range._2)) 236 val bits = log2Up(range._2) 237 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 238 }).reduce(_ || _) 239} 240 241 242 243class XSCore()(implicit p: config.Parameters) extends LazyModule { 244 245 val dcache = LazyModule(new DCache()) 246 val uncache = LazyModule(new Uncache()) 247 val l1pluscache = LazyModule(new L1plusCache()) 248 val ptw = LazyModule(new PTW()) 249 250 val mem = TLIdentityNode() 251 val mmio = uncache.clientNode 252 253 // TODO: refactor these params 254 private val l2 = LazyModule(new InclusiveCache( 255 CacheParameters( 256 level = 2, 257 ways = 4, 258 sets = 512 * 1024 / (64 * 4), 259 blockBytes = 64, 260 beatBytes = 32 // beatBytes = l1BusDataWidth / 8 261 ), 262 InclusiveCacheMicroParameters( 263 writeBytes = 8 264 ) 265 )) 266 267 private val xbar = TLXbar() 268 269 xbar := TLBuffer() := DebugIdentityNode() := dcache.clientNode 270 xbar := TLBuffer() := DebugIdentityNode() := l1pluscache.clientNode 271 xbar := TLBuffer() := DebugIdentityNode() := ptw.node 272 273 l2.node := xbar 274 275 mem := TLBuffer() := TLCacheCork() := TLBuffer() := l2.node 276 277 lazy val module = new XSCoreImp(this) 278} 279 280class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) with HasXSParameter { 281 val io = IO(new Bundle { 282 val externalInterrupt = new ExternalInterruptIO 283 }) 284 285 val front = Module(new Frontend) 286 val backend = Module(new Backend) 287 val mem = Module(new Memend) 288 289 val dcache = outer.dcache.module 290 val uncache = outer.uncache.module 291 val l1pluscache = outer.l1pluscache.module 292 val ptw = outer.ptw.module 293 val icache = Module(new ICache) 294 295 front.io.backend <> backend.io.frontend 296 front.io.icacheResp <> icache.io.resp 297 front.io.icacheToTlb <> icache.io.tlb 298 icache.io.req <> front.io.icacheReq 299 icache.io.flush <> front.io.icacheFlush 300 301 icache.io.mem_acquire <> l1pluscache.io.req 302 l1pluscache.io.resp <> icache.io.mem_grant 303 l1pluscache.io.flush := icache.io.l1plusflush 304 icache.io.fencei := backend.io.fencei 305 306 mem.io.backend <> backend.io.mem 307 io.externalInterrupt <> backend.io.externalInterrupt 308 309 ptw.io.tlb(0) <> mem.io.ptw 310 ptw.io.tlb(1) <> front.io.ptw 311 ptw.io.sfence <> backend.io.mem.sfence//sfence 312 ptw.io.csr <> backend.io.tlbCsrIO 313 314 dcache.io.lsu.load <> mem.io.loadUnitToDcacheVec 315 dcache.io.lsu.lsroq <> mem.io.loadMiss 316 dcache.io.lsu.atomics <> mem.io.atomics 317 dcache.io.lsu.store <> mem.io.sbufferToDcache 318 uncache.io.lsroq <> mem.io.uncache 319 320} 321