1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.backend.exu.Exu._ 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.backend.fu.HasExceptionNO 13<<<<<<< HEAD 14import xiangshan.cache.{ICache, icacheUncache,DCache, L1plusCache, DCacheParameters, ICacheParameters, L1plusCacheParameters, PTW, Uncache} 15======= 16import xiangshan.cache.{DCache, DCacheParameters, ICache, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, Uncache} 17import xiangshan.cache.prefetch._ 18>>>>>>> master 19import chipsalliance.rocketchip.config 20import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp} 21import freechips.rocketchip.tilelink.{TLBuffer, TLBundleParameters, TLCacheCork, TLClientNode, TLFilter, TLIdentityNode, TLToAXI4, TLWidthWidget, TLXbar} 22import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError} 23import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 24import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4IdentityNode, AXI4ToTL, AXI4UserYanker} 25import freechips.rocketchip.tile.HasFPUParameters 26import utils._ 27 28case class XSCoreParameters 29( 30 XLEN: Int = 64, 31 HasMExtension: Boolean = true, 32 HasCExtension: Boolean = true, 33 HasDiv: Boolean = true, 34 HasICache: Boolean = true, 35 HasDCache: Boolean = true, 36 EnableStoreQueue: Boolean = true, 37 AddrBits: Int = 64, 38 VAddrBits: Int = 39, 39 PAddrBits: Int = 40, 40 HasFPU: Boolean = true, 41 FectchWidth: Int = 8, 42 EnableBPU: Boolean = true, 43 EnableBPD: Boolean = true, 44 EnableRAS: Boolean = true, 45 EnableLB: Boolean = false, 46 EnableLoop: Boolean = true, 47 EnableSC: Boolean = false, 48 HistoryLength: Int = 64, 49 BtbSize: Int = 2048, 50 JbtacSize: Int = 1024, 51 JbtacBanks: Int = 8, 52 RasSize: Int = 16, 53 CacheLineSize: Int = 512, 54 UBtbWays: Int = 16, 55 BtbWays: Int = 2, 56 57 EnableL1plusPrefetcher: Boolean = true, 58 IBufSize: Int = 32, 59 DecodeWidth: Int = 6, 60 RenameWidth: Int = 6, 61 CommitWidth: Int = 6, 62 BrqSize: Int = 32, 63 IssQueSize: Int = 12, 64 NRPhyRegs: Int = 160, 65 NRIntReadPorts: Int = 14, 66 NRIntWritePorts: Int = 8, 67 NRFpReadPorts: Int = 14, 68 NRFpWritePorts: Int = 8, 69 LoadQueueSize: Int = 64, 70 StoreQueueSize: Int = 48, 71 RoqSize: Int = 192, 72 dpParams: DispatchParameters = DispatchParameters( 73 IntDqSize = 32, 74 FpDqSize = 32, 75 LsDqSize = 32, 76 IntDqDeqWidth = 4, 77 FpDqDeqWidth = 4, 78 LsDqDeqWidth = 4 79 ), 80 exuParameters: ExuParameters = ExuParameters( 81 JmpCnt = 1, 82 AluCnt = 4, 83 MulCnt = 0, 84 MduCnt = 2, 85 FmacCnt = 4, 86 FmiscCnt = 2, 87 FmiscDivSqrtCnt = 0, 88 LduCnt = 2, 89 StuCnt = 2 90 ), 91 LoadPipelineWidth: Int = 2, 92 StorePipelineWidth: Int = 2, 93 StoreBufferSize: Int = 16, 94 RefillSize: Int = 512, 95 TlbEntrySize: Int = 32, 96 TlbL2EntrySize: Int = 256, // or 512 97 PtwL1EntrySize: Int = 16, 98 PtwL2EntrySize: Int = 256, 99 NumPerfCounters: Int = 16, 100 NrExtIntr: Int = 1 101) 102 103trait HasXSParameter { 104 105 val core = Parameters.get.coreParameters 106 val env = Parameters.get.envParameters 107 108 val XLEN = 64 109 val minFLen = 32 110 val fLen = 64 111 def xLen = 64 112 val HasMExtension = core.HasMExtension 113 val HasCExtension = core.HasCExtension 114 val HasDiv = core.HasDiv 115 val HasIcache = core.HasICache 116 val HasDcache = core.HasDCache 117 val EnableStoreQueue = core.EnableStoreQueue 118 val AddrBits = core.AddrBits // AddrBits is used in some cases 119 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 120 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 121 val AddrBytes = AddrBits / 8 // unused 122 val DataBits = XLEN 123 val DataBytes = DataBits / 8 124 val HasFPU = core.HasFPU 125 val FetchWidth = core.FectchWidth 126 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 127 val EnableBPU = core.EnableBPU 128 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 129 val EnableRAS = core.EnableRAS 130 val EnableLB = core.EnableLB 131 val EnableLoop = core.EnableLoop 132 val EnableSC = core.EnableSC 133 val HistoryLength = core.HistoryLength 134 val BtbSize = core.BtbSize 135 // val BtbWays = 4 136 val BtbBanks = PredictWidth 137 // val BtbSets = BtbSize / BtbWays 138 val JbtacSize = core.JbtacSize 139 val JbtacBanks = core.JbtacBanks 140 val RasSize = core.RasSize 141 val CacheLineSize = core.CacheLineSize 142 val CacheLineHalfWord = CacheLineSize / 16 143 val ExtHistoryLength = HistoryLength + 64 144 val UBtbWays = core.UBtbWays 145 val BtbWays = core.BtbWays 146 val EnableL1plusPrefetcher = core.EnableL1plusPrefetcher 147 val IBufSize = core.IBufSize 148 val DecodeWidth = core.DecodeWidth 149 val RenameWidth = core.RenameWidth 150 val CommitWidth = core.CommitWidth 151 val BrqSize = core.BrqSize 152 val IssQueSize = core.IssQueSize 153 val BrTagWidth = log2Up(BrqSize) 154 val NRPhyRegs = core.NRPhyRegs 155 val PhyRegIdxWidth = log2Up(NRPhyRegs) 156 val RoqSize = core.RoqSize 157 val LoadQueueSize = core.LoadQueueSize 158 val StoreQueueSize = core.StoreQueueSize 159 val dpParams = core.dpParams 160 val exuParameters = core.exuParameters 161 val NRIntReadPorts = core.NRIntReadPorts 162 val NRIntWritePorts = core.NRIntWritePorts 163 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 164 val NRFpReadPorts = core.NRFpReadPorts 165 val NRFpWritePorts = core.NRFpWritePorts 166 val LoadPipelineWidth = core.LoadPipelineWidth 167 val StorePipelineWidth = core.StorePipelineWidth 168 val StoreBufferSize = core.StoreBufferSize 169 val RefillSize = core.RefillSize 170 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 171 val TlbEntrySize = core.TlbEntrySize 172 val TlbL2EntrySize = core.TlbL2EntrySize 173 val PtwL1EntrySize = core.PtwL1EntrySize 174 val PtwL2EntrySize = core.PtwL2EntrySize 175 val NumPerfCounters = core.NumPerfCounters 176 val NrExtIntr = core.NrExtIntr 177 178 val icacheParameters = ICacheParameters( 179 tagECC = Some("parity"), 180 dataECC = Some("parity"), 181 nMissEntries = 2 182 ) 183 184 val l1plusCacheParameters = L1plusCacheParameters( 185 tagECC = Some("secded"), 186 dataECC = Some("secded"), 187 nMissEntries = 8 188 ) 189 190 // icache prefetcher 191 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 192 enable = false, 193 _type = "stream", 194 streamParams = StreamPrefetchParameters( 195 streamCnt = 4, 196 streamSize = 4, 197 ageWidth = 4, 198 blockBytes = l1plusCacheParameters.blockBytes, 199 reallocStreamOnMissInstantly = true 200 ) 201 ) 202 203 // dcache prefetcher 204 val l2PrefetcherParameters = L2PrefetcherParameters( 205 enable = true, 206 _type = "stream", 207 streamParams = StreamPrefetchParameters( 208 streamCnt = 4, 209 streamSize = 4, 210 ageWidth = 4, 211 blockBytes = L2BlockSize, 212 reallocStreamOnMissInstantly = true 213 ) 214 ) 215 216 val dcacheParameters = DCacheParameters( 217 tagECC = Some("secded"), 218 dataECC = Some("secded"), 219 nMissEntries = 16, 220 nLoadMissEntries = 8, 221 nStoreMissEntries = 8 222 ) 223 224 val LRSCCycles = 100 225 226 227 // cache hierarchy configurations 228 val l1BusDataWidth = 256 229 230 // L2 configurations 231 val L1BusWidth = 256 232 val L2Size = 512 * 1024 // 512KB 233 val L2BlockSize = 64 234 val L2NWays = 8 235 val L2NSets = L2Size / L2BlockSize / L2NWays 236 237 // L3 configurations 238 val L2BusWidth = 256 239 val L3Size = 4 * 1024 * 1024 // 4MB 240 val L3BlockSize = 64 241 val L3NBanks = 4 242 val L3NWays = 8 243 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 244 245 // on chip network configurations 246 val L3BusWidth = 256 247} 248 249trait HasXSLog { this: RawModule => 250 implicit val moduleName: String = this.name 251} 252 253abstract class XSModule extends MultiIOModule 254 with HasXSParameter 255 with HasExceptionNO 256 with HasXSLog 257 with HasFPUParameters 258{ 259 def io: Record 260} 261 262//remove this trait after impl module logic 263trait NeedImpl { this: RawModule => 264 override protected def IO[T <: Data](iodef: T): T = { 265 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 266 val io = chisel3.experimental.IO(iodef) 267 io <> DontCare 268 io 269 } 270} 271 272abstract class XSBundle extends Bundle 273 with HasXSParameter 274 275case class EnviromentParameters 276( 277 FPGAPlatform: Boolean = true, 278 EnableDebug: Boolean = false 279) 280 281object AddressSpace extends HasXSParameter { 282 // (start, size) 283 // address out of MMIO will be considered as DRAM 284 def mmio = List( 285 (0x00000000L, 0x40000000L), // internal devices, such as CLINT and PLIC 286 (0x40000000L, 0x40000000L) // external devices 287 ) 288 289 def isMMIO(addr: UInt): Bool = mmio.map(range => { 290 require(isPow2(range._2)) 291 val bits = log2Up(range._2) 292 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 293 }).reduce(_ || _) 294} 295 296 297 298class XSCore()(implicit p: config.Parameters) extends LazyModule 299 with HasXSParameter 300 with HasExeBlockHelper 301{ 302 303 // to fast wake up fp, mem rs 304 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 305 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 306 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 307 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 308 309 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 310 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 311 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 312 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 313 314 // outer facing nodes 315<<<<<<< HEAD 316 val dcache = LazyModule(new DCache()) 317 val uncache = LazyModule(new Uncache()) 318 val icacheUncache = LazyModule(new icacheUncache()) 319======= 320>>>>>>> master 321 val l1pluscache = LazyModule(new L1plusCache()) 322 val ptw = LazyModule(new PTW()) 323 val l2Prefetcher = LazyModule(new L2Prefetcher()) 324 val memBlock = LazyModule(new MemBlock( 325 fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp, 326 slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp, 327 fastFpOut = Seq(), 328 slowFpOut = loadExuConfigs, 329 fastIntOut = Seq(), 330 slowIntOut = loadExuConfigs 331 )) 332 333 lazy val module = new XSCoreImp(this) 334} 335 336class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 337 with HasXSParameter 338 with HasExeBlockHelper 339{ 340 val io = IO(new Bundle { 341 val externalInterrupt = new ExternalInterruptIO 342 }) 343 344 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 345 346 // to fast wake up fp, mem rs 347 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 348 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 349 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 350 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 351 352 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 353 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 354 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 355 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 356 357 val frontend = Module(new Frontend) 358 val ctrlBlock = Module(new CtrlBlock) 359 val integerBlock = Module(new IntegerBlock( 360 fastWakeUpIn = fpBlockFastWakeUpInt, 361 slowWakeUpIn = fpBlockSlowWakeUpInt ++ loadExuConfigs, 362 fastFpOut = intBlockFastWakeUpFp, 363 slowFpOut = intBlockSlowWakeUpFp, 364 fastIntOut = intBlockFastWakeUpInt, 365 slowIntOut = intBlockSlowWakeUpInt 366 )) 367 val floatBlock = Module(new FloatBlock( 368 fastWakeUpIn = intBlockFastWakeUpFp, 369 slowWakeUpIn = intBlockSlowWakeUpFp ++ loadExuConfigs, 370 fastFpOut = fpBlockFastWakeUpFp, 371 slowFpOut = fpBlockSlowWakeUpFp, 372 fastIntOut = fpBlockFastWakeUpInt, 373 slowIntOut = fpBlockSlowWakeUpInt 374 )) 375 376<<<<<<< HEAD 377 val dcache = outer.dcache.module 378 val uncache = outer.uncache.module 379 val icacheUncache = outer.icacheUncache.module 380======= 381 val memBlock = outer.memBlock.module 382>>>>>>> master 383 val l1pluscache = outer.l1pluscache.module 384 val ptw = outer.ptw.module 385 val l2Prefetcher = outer.l2Prefetcher.module 386 387 frontend.io.backend <> ctrlBlock.io.frontend 388 frontend.io.sfence <> integerBlock.io.fenceio.sfence 389 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 390 391 frontend.io.icacheMemAcq <> l1pluscache.io.req 392 l1pluscache.io.resp <> frontend.io.icacheMemGrant 393 l1pluscache.io.flush := frontend.io.l1plusFlush 394 frontend.io.fencei := integerBlock.io.fenceio.fencei 395 396 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 397 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 398 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 399 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 400 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 401 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 402 403 integerBlock.io.wakeUpIn.fastUops <> floatBlock.io.wakeUpIntOut.fastUops 404 integerBlock.io.wakeUpIn.fast <> floatBlock.io.wakeUpIntOut.fast 405 integerBlock.io.wakeUpIn.slow <> floatBlock.io.wakeUpIntOut.slow ++ memBlock.io.wakeUpIntOut.slow 406 integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock 407 408 floatBlock.io.wakeUpIn.fastUops <> integerBlock.io.wakeUpFpOut.fastUops 409 floatBlock.io.wakeUpIn.fast <> integerBlock.io.wakeUpFpOut.fast 410 floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlock.io.wakeUpFpOut.slow 411 floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock 412 413 414 integerBlock.io.wakeUpIntOut.fast.map(_.ready := true.B) 415 integerBlock.io.wakeUpIntOut.slow.map(_.ready := true.B) 416 floatBlock.io.wakeUpFpOut.fast.map(_.ready := true.B) 417 floatBlock.io.wakeUpFpOut.slow.map(_.ready := true.B) 418 419 val wakeUpMem = Seq( 420 integerBlock.io.wakeUpIntOut, 421 integerBlock.io.wakeUpFpOut, 422 floatBlock.io.wakeUpIntOut, 423 floatBlock.io.wakeUpFpOut 424 ) 425 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 426 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(w => w.fast.map(f => { 427 val raw = WireInit(f) 428 raw 429 })) 430 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(w => w.slow.map(s => { 431 val raw = WireInit(s) 432 raw 433 })) 434 435 integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags 436 integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 437 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 438 integerBlock.io.csrio.isInterrupt <> ctrlBlock.io.roqio.isInterrupt 439 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 440 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 441 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 442 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 443 integerBlock.io.csrio.tlb <> memBlock.io.tlbCsr 444 integerBlock.io.csrio.perfinfo <> ctrlBlock.io.roqio.toCSR.perfinfo 445 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 446 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 447 448 floatBlock.io.frm <> integerBlock.io.csrio.frm 449 450 memBlock.io.lsqio.commits <> ctrlBlock.io.roqio.commits 451 memBlock.io.lsqio.roqDeqPtr <> ctrlBlock.io.roqio.roqDeqPtr 452 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.lqIdx 453 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.sqIdx 454 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.ctrl.commitType) 455 456 ptw.io.tlb(0) <> memBlock.io.ptw 457 ptw.io.tlb(1) <> frontend.io.ptw 458 ptw.io.sfence <> integerBlock.io.fenceio.sfence 459 ptw.io.csr <> integerBlock.io.csrio.tlb 460 461<<<<<<< HEAD 462 dcache.io.lsu.load <> memBlock.io.dcache.loadUnitToDcacheVec 463 dcache.io.lsu.lsq <> memBlock.io.dcache.loadMiss 464 dcache.io.lsu.atomics <> memBlock.io.dcache.atomics 465 dcache.io.lsu.store <> memBlock.io.dcache.sbufferToDcache 466 uncache.io.lsq <> memBlock.io.dcache.uncache 467 icacheUncache.io.req <> icache.io.mmio_acquire 468 icache.io.mmio_grant <> icacheUncache.io.resp 469 icacheUncache.io.flush <> icache.io.mmio_flush 470======= 471 l2Prefetcher.io.in <> memBlock.io.toDCachePrefetch 472>>>>>>> master 473 474 if (!env.FPGAPlatform) { 475 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 476 ExcitingUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG", ExcitingUtils.Debug) 477 ExcitingUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG", ExcitingUtils.Debug) 478 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 479 ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug) 480 } 481 482} 483