1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 6import top.Parameters 7import xiangshan.backend._ 8import xiangshan.backend.dispatch.DispatchParameters 9import xiangshan.backend.exu.ExuParameters 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.cache.{ICache, DCache, DCacheParameters, ICacheParameters, PTW, Uncache} 13import chipsalliance.rocketchip.config 14import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 15import freechips.rocketchip.tilelink.{TLBundleParameters, TLCacheCork, TLBuffer, TLClientNode, TLIdentityNode, TLXbar} 16import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 17import utils._ 18 19case class XSCoreParameters 20( 21 XLEN: Int = 64, 22 HasMExtension: Boolean = true, 23 HasCExtension: Boolean = true, 24 HasDiv: Boolean = true, 25 HasICache: Boolean = true, 26 HasDCache: Boolean = true, 27 EnableStoreQueue: Boolean = true, 28 AddrBits: Int = 64, 29 VAddrBits: Int = 39, 30 PAddrBits: Int = 40, 31 HasFPU: Boolean = true, 32 FectchWidth: Int = 8, 33 EnableBPU: Boolean = true, 34 EnableBPD: Boolean = true, 35 EnableRAS: Boolean = true, 36 EnableLB: Boolean = false, 37 EnableLoop: Boolean = false, 38 HistoryLength: Int = 64, 39 BtbSize: Int = 2048, 40 JbtacSize: Int = 1024, 41 JbtacBanks: Int = 8, 42 RasSize: Int = 16, 43 CacheLineSize: Int = 512, 44 UBtbWays: Int = 16, 45 BtbWays: Int = 2, 46 IBufSize: Int = 64, 47 DecodeWidth: Int = 6, 48 RenameWidth: Int = 6, 49 CommitWidth: Int = 6, 50 BrqSize: Int = 12, 51 IssQueSize: Int = 8, 52 NRPhyRegs: Int = 72, 53 NRIntReadPorts: Int = 8, 54 NRIntWritePorts: Int = 8, 55 NRFpReadPorts: Int = 14, 56 NRFpWritePorts: Int = 8, 57 EnableUnifiedLSQ: Boolean = false, 58 LsroqSize: Int = 16, 59 LoadQueueSize: Int = 12, 60 StoreQueueSize: Int = 10, 61 RoqSize: Int = 32, 62 dpParams: DispatchParameters = DispatchParameters( 63 DqEnqWidth = 4, 64 IntDqSize = 24, 65 FpDqSize = 16, 66 LsDqSize = 16, 67 IntDqDeqWidth = 4, 68 FpDqDeqWidth = 4, 69 LsDqDeqWidth = 4, 70 IntDqReplayWidth = 4, 71 FpDqReplayWidth = 4, 72 LsDqReplayWidth = 4 73 ), 74 exuParameters: ExuParameters = ExuParameters( 75 JmpCnt = 1, 76 AluCnt = 4, 77 MulCnt = 0, 78 MduCnt = 2, 79 FmacCnt = 4, 80 FmiscCnt = 2, 81 FmiscDivSqrtCnt = 0, 82 LduCnt = 2, 83 StuCnt = 2 84 ), 85 LoadPipelineWidth: Int = 2, 86 StorePipelineWidth: Int = 2, 87 StoreBufferSize: Int = 16, 88 RefillSize: Int = 512, 89 TlbEntrySize: Int = 32, 90 TlbL2EntrySize: Int = 256, // or 512 91 PtwL1EntrySize: Int = 16, 92 PtwL2EntrySize: Int = 256 93) 94 95trait HasXSParameter { 96 97 val core = Parameters.get.coreParameters 98 val env = Parameters.get.envParameters 99 100 val XLEN = core.XLEN 101 val HasMExtension = core.HasMExtension 102 val HasCExtension = core.HasCExtension 103 val HasDiv = core.HasDiv 104 val HasIcache = core.HasICache 105 val HasDcache = core.HasDCache 106 val EnableStoreQueue = core.EnableStoreQueue 107 val AddrBits = core.AddrBits // AddrBits is used in some cases 108 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 109 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 110 val AddrBytes = AddrBits / 8 // unused 111 val DataBits = XLEN 112 val DataBytes = DataBits / 8 113 val HasFPU = core.HasFPU 114 val FetchWidth = core.FectchWidth 115 val PredictWidth = FetchWidth * 2 116 val EnableBPU = core.EnableBPU 117 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 118 val EnableRAS = core.EnableRAS 119 val EnableLB = core.EnableLB 120 val EnableLoop = core.EnableLoop 121 val HistoryLength = core.HistoryLength 122 val BtbSize = core.BtbSize 123 // val BtbWays = 4 124 val BtbBanks = PredictWidth 125 // val BtbSets = BtbSize / BtbWays 126 val JbtacSize = core.JbtacSize 127 val JbtacBanks = core.JbtacBanks 128 val RasSize = core.RasSize 129 val CacheLineSize = core.CacheLineSize 130 val CacheLineHalfWord = CacheLineSize / 16 131 val ExtHistoryLength = HistoryLength + 64 132 val UBtbWays = core.UBtbWays 133 val BtbWays = core.BtbWays 134 val IBufSize = core.IBufSize 135 val DecodeWidth = core.DecodeWidth 136 val RenameWidth = core.RenameWidth 137 val CommitWidth = core.CommitWidth 138 val BrqSize = core.BrqSize 139 val IssQueSize = core.IssQueSize 140 val BrTagWidth = log2Up(BrqSize) 141 val NRPhyRegs = core.NRPhyRegs 142 val PhyRegIdxWidth = log2Up(NRPhyRegs) 143 val RoqSize = core.RoqSize 144 val EnableUnifiedLSQ = core.EnableUnifiedLSQ 145 val LsroqSize = core.LsroqSize // 64 146 val InnerLsroqIdxWidth = log2Up(LsroqSize) 147 val LsroqIdxWidth = InnerLsroqIdxWidth + 1 148 val LoadQueueSize = core.LoadQueueSize 149 val StoreQueueSize = core.StoreQueueSize 150 val dpParams = core.dpParams 151 val ReplayWidth = dpParams.IntDqReplayWidth + dpParams.FpDqReplayWidth + dpParams.LsDqReplayWidth 152 val exuParameters = core.exuParameters 153 val NRIntReadPorts = core.NRIntReadPorts 154 val NRIntWritePorts = core.NRIntWritePorts 155 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 156 val NRFpReadPorts = core.NRFpReadPorts 157 val NRFpWritePorts = core.NRFpWritePorts 158 val LoadPipelineWidth = core.LoadPipelineWidth 159 val StorePipelineWidth = core.StorePipelineWidth 160 val StoreBufferSize = core.StoreBufferSize 161 val RefillSize = core.RefillSize 162 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 163 val TlbEntrySize = core.TlbEntrySize 164 val TlbL2EntrySize = core.TlbL2EntrySize 165 val PtwL1EntrySize = core.PtwL1EntrySize 166 val PtwL2EntrySize = core.PtwL2EntrySize 167 168 val l1BusDataWidth = 256 169 170 val icacheParameters = ICacheParameters( 171 ) 172 173 val LRSCCycles = 100 174 val dcacheParameters = DCacheParameters( 175 tagECC = Some("secded"), 176 dataECC = Some("secded"), 177 nMissEntries = 16, 178 nLoadMissEntries = 8, 179 nStoreMissEntries = 8 180 ) 181} 182 183trait HasXSLog { this: RawModule => 184 implicit val moduleName: String = this.name 185} 186 187abstract class XSModule extends Module 188 with HasXSParameter 189 with HasExceptionNO 190 with HasXSLog 191 192//remove this trait after impl module logic 193trait NeedImpl { this: Module => 194 override protected def IO[T <: Data](iodef: T): T = { 195 val io = chisel3.experimental.IO(iodef) 196 io <> DontCare 197 io 198 } 199} 200 201abstract class XSBundle extends Bundle 202 with HasXSParameter 203 204case class EnviromentParameters 205( 206 FPGAPlatform: Boolean = true, 207 EnableDebug: Boolean = false 208) 209 210object AddressSpace extends HasXSParameter { 211 // (start, size) 212 // address out of MMIO will be considered as DRAM 213 def mmio = List( 214 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 215 (0x40000000L, 0x40000000L) // external devices 216 ) 217 218 def isMMIO(addr: UInt): Bool = mmio.map(range => { 219 require(isPow2(range._2)) 220 val bits = log2Up(range._2) 221 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 222 }).reduce(_ || _) 223} 224 225 226 227class XSCore()(implicit p: config.Parameters) extends LazyModule { 228 229 val dcache = LazyModule(new DCache()) 230 val uncache = LazyModule(new Uncache()) 231 val icache = LazyModule(new ICache()) 232 val ptw = LazyModule(new PTW()) 233 234 val mem = TLIdentityNode() 235 val mmio = uncache.clientNode 236 237 // TODO: refactor these params 238 private val l2 = LazyModule(new InclusiveCache( 239 CacheParameters( 240 level = 2, 241 ways = 4, 242 sets = 512 * 1024 / (64 * 4), 243 blockBytes = 64, 244 beatBytes = 32 // beatBytes = l1BusDataWidth / 8 245 ), 246 InclusiveCacheMicroParameters( 247 writeBytes = 8 248 ) 249 )) 250 251 private val xbar = TLXbar() 252 253 xbar := TLBuffer() := DebugIdentityNode() := dcache.clientNode 254 xbar := TLBuffer() := DebugIdentityNode() := icache.clientNode 255 xbar := TLBuffer() := DebugIdentityNode() := ptw.node 256 257 l2.node := xbar 258 259 mem := TLBuffer() := TLCacheCork() := TLBuffer() := l2.node 260 261 lazy val module = new XSCoreImp(this) 262} 263 264class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) with HasXSParameter { 265 266 val front = Module(new Frontend) 267 val backend = Module(new Backend) 268 val mem = Module(new Memend) 269 270 val dcache = outer.dcache.module 271 val uncache = outer.uncache.module 272 val icache = outer.icache.module 273 val ptw = outer.ptw.module 274 275 // TODO: connect this 276 277 front.io.backend <> backend.io.frontend 278 front.io.icacheResp <> icache.io.resp 279 front.io.icacheToTlb <> icache.io.tlb 280 icache.io.req <> front.io.icacheReq 281 icache.io.flush <> front.io.icacheFlush 282 mem.io.backend <> backend.io.mem 283 284 ptw.io.tlb(0) <> mem.io.ptw 285 ptw.io.tlb(1) <> front.io.ptw 286 287 dcache.io.lsu.load <> mem.io.loadUnitToDcacheVec 288 dcache.io.lsu.lsroq <> mem.io.loadMiss 289 dcache.io.lsu.atomics <> mem.io.atomics 290 dcache.io.lsu.store <> mem.io.sbufferToDcache 291 uncache.io.lsroq <> mem.io.uncache 292 293} 294