1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import device.MsiInfoBundle 24import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp} 25import freechips.rocketchip.tile.HasFPUParameters 26import system.HasSoCParameter 27import utils._ 28import utility._ 29import xiangshan.backend._ 30import xiangshan.cache.mmu._ 31import xiangshan.frontend._ 32import xiangshan.mem.L1PrefetchFuzzer 33import scala.collection.mutable.ListBuffer 34import xiangshan.cache.mmu.TlbRequestIO 35 36abstract class XSModule(implicit val p: Parameters) extends Module 37 with HasXSParameter 38 with HasFPUParameters 39 40//remove this trait after impl module logic 41trait NeedImpl { 42 this: RawModule => 43 protected def IO[T <: Data](iodef: T): T = { 44 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 45 val io = chisel3.IO(iodef) 46 io <> DontCare 47 io 48 } 49} 50 51abstract class XSBundle(implicit val p: Parameters) extends Bundle 52 with HasXSParameter 53 54abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 55 with HasXSParameter 56{ 57 override def shouldBeInlined: Boolean = false 58 // outer facing nodes 59 val frontend = LazyModule(new Frontend()) 60 val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO())) 61 val backend = LazyModule(new Backend(backendParams)) 62 63 val memBlock = LazyModule(new MemBlock) 64 65 memBlock.frontendBridge.icache_node := frontend.icache.clientNode 66 memBlock.frontendBridge.instr_uncache_node := frontend.instrUncache.clientNode 67} 68 69class XSCore()(implicit p: config.Parameters) extends XSCoreBase 70 with HasXSDts 71{ 72 lazy val module = new XSCoreImp(this) 73} 74 75class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 76 with HasXSParameter 77 with HasSoCParameter { 78 val io = IO(new Bundle { 79 val hartId = Input(UInt(hartIdLen.W)) 80 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 81 val clintTime = Input(ValidIO(UInt(64.W))) 82 val reset_vector = Input(UInt(PAddrBits.W)) 83 val cpu_halt = Output(Bool()) 84 val l2_pf_enable = Output(Bool()) 85 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)) 86 val beu_errors = Output(new XSL1BusErrors()) 87 val l2_hint = Input(Valid(new L2ToL1Hint())) 88 val l2_tlb_req = Flipped(new TlbRequestIO(nRespDups = 2)) 89 val l2PfqBusy = Input(Bool()) 90 val debugTopDown = new Bundle { 91 val robTrueCommit = Output(UInt(64.W)) 92 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 93 val l2MissMatch = Input(Bool()) 94 val l3MissMatch = Input(Bool()) 95 } 96 }) 97 98 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 99 100 val frontend = outer.frontend.module 101 val backend = outer.backend.module 102 val memBlock = outer.memBlock.module 103 104 frontend.io.hartId := memBlock.io.inner_hartId 105 frontend.io.reset_vector := memBlock.io.inner_reset_vector 106 frontend.io.backend <> backend.io.frontend 107 frontend.io.sfence <> backend.io.frontendSfence 108 frontend.io.tlbCsr <> backend.io.frontendTlbCsr 109 frontend.io.csrCtrl <> backend.io.frontendCsrCtrl 110 frontend.io.fencei <> backend.io.fenceio.fencei 111 112 backend.io.fromTop.hartId := memBlock.io.inner_hartId 113 backend.io.fromTop.msiInfo := io.msiInfo 114 backend.io.fromTop.clintTime := io.clintTime 115 116 backend.io.fromTop.externalInterrupt := memBlock.io.externalInterrupt 117 118 require(backend.io.mem.stIn.length == memBlock.io.mem_to_ooo.stIn.length) 119 backend.io.mem.stIn.zip(memBlock.io.mem_to_ooo.stIn).foreach { case (sink, source) => 120 sink.valid := source.valid 121 sink.bits := 0.U.asTypeOf(sink.bits) 122 sink.bits.robIdx := source.bits.uop.robIdx 123 sink.bits.ssid := source.bits.uop.ssid 124 sink.bits.storeSetHit := source.bits.uop.storeSetHit 125 // The other signals have not been used 126 } 127 backend.io.mem.memoryViolation <> memBlock.io.mem_to_ooo.memoryViolation 128 backend.io.mem.lsqEnqIO <> memBlock.io.ooo_to_mem.enqLsq 129 backend.io.mem.sqDeq := memBlock.io.mem_to_ooo.sqDeq 130 backend.io.mem.lqDeq := memBlock.io.mem_to_ooo.lqDeq 131 backend.io.mem.sqDeqPtr := memBlock.io.mem_to_ooo.sqDeqPtr 132 backend.io.mem.lqDeqPtr := memBlock.io.mem_to_ooo.lqDeqPtr 133 backend.io.mem.lqCancelCnt := memBlock.io.mem_to_ooo.lqCancelCnt 134 backend.io.mem.sqCancelCnt := memBlock.io.mem_to_ooo.sqCancelCnt 135 backend.io.mem.otherFastWakeup := memBlock.io.mem_to_ooo.otherFastWakeup 136 backend.io.mem.stIssuePtr := memBlock.io.mem_to_ooo.stIssuePtr 137 backend.io.mem.ldaIqFeedback <> memBlock.io.mem_to_ooo.ldaIqFeedback 138 backend.io.mem.staIqFeedback <> memBlock.io.mem_to_ooo.staIqFeedback 139 backend.io.mem.hyuIqFeedback <> memBlock.io.mem_to_ooo.hyuIqFeedback 140 backend.io.mem.vstuIqFeedback <> memBlock.io.mem_to_ooo.vstuIqFeedback 141 backend.io.mem.vlduIqFeedback <> memBlock.io.mem_to_ooo.vlduIqFeedback 142 backend.io.mem.ldCancel <> memBlock.io.mem_to_ooo.ldCancel 143 backend.io.mem.wakeup <> memBlock.io.mem_to_ooo.wakeup 144 backend.io.mem.writebackLda <> memBlock.io.mem_to_ooo.writebackLda 145 backend.io.mem.writebackSta <> memBlock.io.mem_to_ooo.writebackSta 146 backend.io.mem.writebackHyuLda <> memBlock.io.mem_to_ooo.writebackHyuLda 147 backend.io.mem.writebackHyuSta <> memBlock.io.mem_to_ooo.writebackHyuSta 148 backend.io.mem.writebackStd <> memBlock.io.mem_to_ooo.writebackStd 149 backend.io.mem.writebackVldu <> memBlock.io.mem_to_ooo.writebackVldu 150 backend.io.mem.robLsqIO.mmio := memBlock.io.mem_to_ooo.lsqio.mmio 151 backend.io.mem.robLsqIO.uop := memBlock.io.mem_to_ooo.lsqio.uop 152 153 // memblock error exception writeback, 1 cycle after normal writeback 154 backend.io.mem.s3_delayed_load_error <> memBlock.io.mem_to_ooo.s3_delayed_load_error 155 156 backend.io.mem.exceptionAddr.vaddr := memBlock.io.mem_to_ooo.lsqio.vaddr 157 backend.io.mem.exceptionAddr.gpaddr := memBlock.io.mem_to_ooo.lsqio.gpaddr 158 backend.io.mem.debugLS := memBlock.io.debug_ls 159 backend.io.mem.lsTopdownInfo := memBlock.io.mem_to_ooo.lsTopdownInfo 160 backend.io.mem.lqCanAccept := memBlock.io.mem_to_ooo.lsqio.lqCanAccept 161 backend.io.mem.sqCanAccept := memBlock.io.mem_to_ooo.lsqio.sqCanAccept 162 backend.io.fenceio.sbuffer.sbIsEmpty := memBlock.io.mem_to_ooo.sbIsEmpty 163 164 backend.io.perf.frontendInfo := frontend.io.frontendInfo 165 backend.io.perf.memInfo := memBlock.io.memInfo 166 backend.io.perf.perfEventsFrontend := frontend.getPerf 167 backend.io.perf.perfEventsLsu := memBlock.getPerf 168 backend.io.perf.perfEventsHc := io.perfEvents 169 backend.io.perf.perfEventsBackend := DontCare 170 backend.io.perf.retiredInstr := DontCare 171 backend.io.perf.ctrlInfo := DontCare 172 173 // top -> memBlock 174 memBlock.io.hartId := io.hartId 175 memBlock.io.outer_reset_vector := io.reset_vector 176 // frontend -> memBlock 177 memBlock.io.inner_beu_errors_icache <> frontend.io.error.bits.toL1BusErrorUnitInfo(frontend.io.error.valid) 178 memBlock.io.inner_l2_pf_enable := backend.io.csrCustomCtrl.l2_pf_enable 179 memBlock.io.inner_cpu_halt := backend.io.toTop.cpuHalted 180 memBlock.io.ooo_to_mem.issueLda <> backend.io.mem.issueLda 181 memBlock.io.ooo_to_mem.issueSta <> backend.io.mem.issueSta 182 memBlock.io.ooo_to_mem.issueStd <> backend.io.mem.issueStd 183 memBlock.io.ooo_to_mem.issueHya <> backend.io.mem.issueHylda 184 backend.io.mem.issueHysta.map(_.ready := false.B) // this fake port should not be used 185 memBlock.io.ooo_to_mem.issueVldu <> backend.io.mem.issueVldu 186 187 // By default, instructions do not have exceptions when they enter the function units. 188 memBlock.io.ooo_to_mem.issueUops.map(_.bits.uop.clearExceptions()) 189 memBlock.io.ooo_to_mem.loadPc := backend.io.mem.loadPcRead 190 memBlock.io.ooo_to_mem.storePc := backend.io.mem.storePcRead 191 memBlock.io.ooo_to_mem.hybridPc := backend.io.mem.hyuPcRead 192 memBlock.io.ooo_to_mem.flushSb := backend.io.fenceio.sbuffer.flushSb 193 memBlock.io.ooo_to_mem.loadFastMatch := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastMatch) 194 memBlock.io.ooo_to_mem.loadFastImm := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastImm) 195 memBlock.io.ooo_to_mem.loadFastFuOpType := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastFuOpType) 196 197 memBlock.io.ooo_to_mem.sfence <> backend.io.mem.sfence 198 199 memBlock.io.redirect <> backend.io.mem.redirect 200 memBlock.io.ooo_to_mem.csrCtrl <> backend.io.mem.csrCtrl 201 memBlock.io.ooo_to_mem.tlbCsr <> backend.io.mem.tlbCsr 202 memBlock.io.ooo_to_mem.lsqio.lcommit := backend.io.mem.robLsqIO.lcommit 203 memBlock.io.ooo_to_mem.lsqio.scommit := backend.io.mem.robLsqIO.scommit 204 memBlock.io.ooo_to_mem.lsqio.pendingld := backend.io.mem.robLsqIO.pendingld 205 memBlock.io.ooo_to_mem.lsqio.pendingst := backend.io.mem.robLsqIO.pendingst 206 memBlock.io.ooo_to_mem.lsqio.pendingVst := backend.io.mem.robLsqIO.pendingVst 207 memBlock.io.ooo_to_mem.lsqio.commit := backend.io.mem.robLsqIO.commit 208 memBlock.io.ooo_to_mem.lsqio.pendingPtr := backend.io.mem.robLsqIO.pendingPtr 209 memBlock.io.ooo_to_mem.lsqio.pendingPtrNext := backend.io.mem.robLsqIO.pendingPtrNext 210 memBlock.io.ooo_to_mem.isStoreException := backend.io.mem.isStoreException 211 memBlock.io.ooo_to_mem.isVlsException := backend.io.mem.isVlsException 212 213 memBlock.io.fetch_to_mem.itlb <> frontend.io.ptw 214 memBlock.io.l2_hint.valid := io.l2_hint.valid 215 memBlock.io.l2_hint.bits.sourceId := io.l2_hint.bits.sourceId 216 memBlock.io.l2_tlb_req <> io.l2_tlb_req 217 memBlock.io.l2_hint.bits.isKeyword := io.l2_hint.bits.isKeyword 218 memBlock.io.l2PfqBusy := io.l2PfqBusy 219 220 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 221 222 // top-down info 223 memBlock.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 224 frontend.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 225 io.debugTopDown.robHeadPaddr := backend.io.debugTopDown.fromRob.robHeadPaddr 226 io.debugTopDown.robTrueCommit := backend.io.debugRolling.robTrueCommit 227 backend.io.debugTopDown.fromCore.l2MissMatch := io.debugTopDown.l2MissMatch 228 backend.io.debugTopDown.fromCore.l3MissMatch := io.debugTopDown.l3MissMatch 229 backend.io.debugTopDown.fromCore.fromMem := memBlock.io.debugTopDown.toCore 230 memBlock.io.debugRolling := backend.io.debugRolling 231 232 io.cpu_halt := memBlock.io.outer_cpu_halt 233 io.beu_errors.icache <> memBlock.io.outer_beu_errors_icache 234 io.beu_errors.dcache <> memBlock.io.error.bits.toL1BusErrorUnitInfo(memBlock.io.error.valid) 235 io.beu_errors.l2 <> DontCare 236 io.l2_pf_enable := memBlock.io.outer_l2_pf_enable 237 // Modules are reset one by one 238 val resetTree = ResetGenNode( 239 Seq( 240 ModuleNode(memBlock), 241 ResetGenNode(Seq( 242 ModuleNode(backend), 243 ResetGenNode(Seq( 244 ResetGenNode(Seq( 245 ModuleNode(frontend) 246 )) 247 )) 248 )) 249 ) 250 ) 251 252 // ResetGen(resetTree, reset, !debugOpts.FPGAPlatform) 253 if (debugOpts.ResetGen) { 254 frontend.reset := memBlock.reset_io_frontend 255 backend.reset := memBlock.reset_io_backend 256 } 257} 258