xref: /XiangShan/src/main/scala/xiangshan/Parameters.scala (revision f320e0f01bd645f0a3045a8a740e60dd770734a9) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import chipsalliance.rocketchip.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import xiangshan.backend.exu._
23import xiangshan.backend.fu._
24import xiangshan.backend.fu.fpu._
25import xiangshan.backend.dispatch.DispatchParameters
26import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters}
27import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters}
28
29case object XSCoreParamsKey extends Field[XSCoreParameters]
30
31case class XSCoreParameters
32(
33  HasPrefetch: Boolean = false,
34  HartId: Int = 0,
35  XLEN: Int = 64,
36  HasMExtension: Boolean = true,
37  HasCExtension: Boolean = true,
38  HasDiv: Boolean = true,
39  HasICache: Boolean = true,
40  HasDCache: Boolean = true,
41  AddrBits: Int = 64,
42  VAddrBits: Int = 39,
43  PAddrBits: Int = 40,
44  HasFPU: Boolean = true,
45  FetchWidth: Int = 8,
46  EnableBPU: Boolean = true,
47  EnableBPD: Boolean = true,
48  EnableRAS: Boolean = true,
49  EnableLB: Boolean = false,
50  EnableLoop: Boolean = true,
51  EnableSC: Boolean = true,
52  EnbaleTlbDebug: Boolean = false,
53  EnableJal: Boolean = false,
54  EnableUBTB: Boolean = true,
55  HistoryLength: Int = 64,
56  BtbSize: Int = 2048,
57  JbtacSize: Int = 1024,
58  JbtacBanks: Int = 8,
59  RasSize: Int = 16,
60  CacheLineSize: Int = 512,
61  UBtbWays: Int = 16,
62  BtbWays: Int = 2,
63
64  EnableL1plusPrefetcher: Boolean = true,
65  IBufSize: Int = 48,
66  DecodeWidth: Int = 6,
67  RenameWidth: Int = 6,
68  CommitWidth: Int = 6,
69  BrqSize: Int = 32,
70  FtqSize: Int = 48,
71  EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false
72  IssQueSize: Int = 16,
73  NRPhyRegs: Int = 160,
74  NRIntReadPorts: Int = 14,
75  NRIntWritePorts: Int = 8,
76  NRFpReadPorts: Int = 14,
77  NRFpWritePorts: Int = 8,
78  LoadQueueSize: Int = 64,
79  StoreQueueSize: Int = 48,
80  RoqSize: Int = 192,
81  dpParams: DispatchParameters = DispatchParameters(
82    IntDqSize = 16,
83    FpDqSize = 16,
84    LsDqSize = 16,
85    IntDqDeqWidth = 4,
86    FpDqDeqWidth = 4,
87    LsDqDeqWidth = 4
88  ),
89  exuParameters: ExuParameters = ExuParameters(
90    JmpCnt = 1,
91    AluCnt = 4,
92    MulCnt = 0,
93    MduCnt = 2,
94    FmacCnt = 4,
95    FmiscCnt = 2,
96    FmiscDivSqrtCnt = 0,
97    LduCnt = 2,
98    StuCnt = 2
99  ),
100  LoadPipelineWidth: Int = 2,
101  StorePipelineWidth: Int = 2,
102  StoreBufferSize: Int = 16,
103  StoreBufferThreshold: Int = 7,
104  RefillSize: Int = 512,
105  TlbEntrySize: Int = 32,
106  TlbSPEntrySize: Int = 4,
107  PtwL3EntrySize: Int = 4096, //(256 * 16) or 512
108  PtwSPEntrySize: Int = 16,
109  PtwL1EntrySize: Int = 16,
110  PtwL2EntrySize: Int = 2048, //(256 * 8)
111  PtwMissQueueSize: Int = 8,
112  NumPerfCounters: Int = 16,
113  icacheParameters: ICacheParameters = ICacheParameters(
114    tagECC = Some("parity"),
115    dataECC = Some("parity"),
116    replacer = Some("setplru"),
117    nMissEntries = 2
118  ),
119  l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters(
120    tagECC = Some("secded"),
121    dataECC = Some("secded"),
122    replacer = Some("setplru"),
123    nMissEntries = 8
124  ),
125  dcacheParameters: DCacheParameters = DCacheParameters(
126    tagECC = Some("secded"),
127    dataECC = Some("secded"),
128    replacer = Some("setplru"),
129    nMissEntries = 16,
130    nProbeEntries = 16,
131    nReleaseEntries = 16,
132    nStoreReplayEntries = 16
133  ),
134  L2Size: Int = 512 * 1024, // 512KB
135  L2NWays: Int = 8,
136  usePTWRepeater: Boolean = false,
137  useFakePTW: Boolean = false,
138  useFakeDCache: Boolean = false,
139  useFakeL1plusCache: Boolean = false,
140  useFakeL2Cache: Boolean = false
141){
142  val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg)
143  val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StExeUnitCfg)
144
145  val intExuConfigs = Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++
146    Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpExeUnitCfg
147
148  val fpExuConfigs =
149    Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++
150      Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg)
151
152  val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs
153}
154
155case object DebugOptionsKey extends Field[DebugOptions]
156
157case class DebugOptions
158(
159  FPGAPlatform: Boolean = true,
160  EnableDebug: Boolean = true,
161  EnablePerfDebug: Boolean = true,
162  UseDRAMSim: Boolean = false
163)
164
165trait HasXSParameter {
166
167  implicit val p: Parameters
168
169  val coreParams = p(XSCoreParamsKey)
170  val env = p(DebugOptionsKey)
171
172  val XLEN = coreParams.XLEN
173  val hardId = coreParams.HartId
174  val minFLen = 32
175  val fLen = 64
176  def xLen = XLEN
177
178  val HasMExtension = coreParams.HasMExtension
179  val HasCExtension = coreParams.HasCExtension
180  val HasDiv = coreParams.HasDiv
181  val HasIcache = coreParams.HasICache
182  val HasDcache = coreParams.HasDCache
183  val AddrBits = coreParams.AddrBits // AddrBits is used in some cases
184  val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits
185  val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits
186  val AddrBytes = AddrBits / 8 // unused
187  val DataBits = XLEN
188  val DataBytes = DataBits / 8
189  val HasFPU = coreParams.HasFPU
190  val FetchWidth = coreParams.FetchWidth
191  val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1)
192  val EnableBPU = coreParams.EnableBPU
193  val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3
194  val EnableRAS = coreParams.EnableRAS
195  val EnableLB = coreParams.EnableLB
196  val EnableLoop = coreParams.EnableLoop
197  val EnableSC = coreParams.EnableSC
198  val EnbaleTlbDebug = coreParams.EnbaleTlbDebug
199  val HistoryLength = coreParams.HistoryLength
200  val BtbSize = coreParams.BtbSize
201  // val BtbWays = 4
202  val BtbBanks = PredictWidth
203  // val BtbSets = BtbSize / BtbWays
204  val JbtacSize = coreParams.JbtacSize
205  val JbtacBanks = coreParams.JbtacBanks
206  val RasSize = coreParams.RasSize
207  val CacheLineSize = coreParams.CacheLineSize
208  val CacheLineHalfWord = CacheLineSize / 16
209  val ExtHistoryLength = HistoryLength + 64
210  val UBtbWays = coreParams.UBtbWays
211  val BtbWays = coreParams.BtbWays
212  val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher
213  val IBufSize = coreParams.IBufSize
214  val DecodeWidth = coreParams.DecodeWidth
215  val RenameWidth = coreParams.RenameWidth
216  val CommitWidth = coreParams.CommitWidth
217  val BrqSize = coreParams.BrqSize
218  val FtqSize = coreParams.FtqSize
219  val IssQueSize = coreParams.IssQueSize
220  val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp
221  val BrTagWidth = log2Up(BrqSize)
222  val NRPhyRegs = coreParams.NRPhyRegs
223  val PhyRegIdxWidth = log2Up(NRPhyRegs)
224  val RoqSize = coreParams.RoqSize
225  val LoadQueueSize = coreParams.LoadQueueSize
226  val StoreQueueSize = coreParams.StoreQueueSize
227  val dpParams = coreParams.dpParams
228  val exuParameters = coreParams.exuParameters
229  val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt
230  val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts
231  val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt
232  val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt
233  val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt
234  val LoadPipelineWidth = coreParams.LoadPipelineWidth
235  val StorePipelineWidth = coreParams.StorePipelineWidth
236  val StoreBufferSize = coreParams.StoreBufferSize
237  val StoreBufferThreshold = coreParams.StoreBufferThreshold
238  val RefillSize = coreParams.RefillSize
239  val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth
240  val TlbEntrySize = coreParams.TlbEntrySize
241  val TlbSPEntrySize = coreParams.TlbSPEntrySize
242  val PtwL3EntrySize = coreParams.PtwL3EntrySize
243  val PtwSPEntrySize = coreParams.PtwSPEntrySize
244  val PtwL1EntrySize = coreParams.PtwL1EntrySize
245  val PtwL2EntrySize = coreParams.PtwL2EntrySize
246  val PtwMissQueueSize = coreParams.PtwMissQueueSize
247  val NumPerfCounters = coreParams.NumPerfCounters
248
249  val instBytes = if (HasCExtension) 2 else 4
250  val instOffsetBits = log2Ceil(instBytes)
251
252  val icacheParameters = coreParams.icacheParameters
253  val l1plusCacheParameters = coreParams.l1plusCacheParameters
254  val dcacheParameters = coreParams.dcacheParameters
255
256  val LRSCCycles = 100
257
258
259  // cache hierarchy configurations
260  val l1BusDataWidth = 256
261
262  val usePTWRepeater = coreParams.usePTWRepeater
263  val useFakeDCache = coreParams.useFakeDCache
264  val useFakePTW = coreParams.useFakePTW
265  val useFakeL1plusCache = coreParams.useFakeL1plusCache
266  // L2 configurations
267  val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache
268  val L1BusWidth = 256
269  val L2Size = coreParams.L2Size
270  val L2BlockSize = 64
271  val L2NWays = coreParams.L2NWays
272  val L2NSets = L2Size / L2BlockSize / L2NWays
273
274  // L3 configurations
275  val L2BusWidth = 256
276
277  // icache prefetcher
278  val l1plusPrefetcherParameters = L1plusPrefetcherParameters(
279    enable = true,
280    _type = "stream",
281    streamParams = StreamPrefetchParameters(
282      streamCnt = 2,
283      streamSize = 4,
284      ageWidth = 4,
285      blockBytes = l1plusCacheParameters.blockBytes,
286      reallocStreamOnMissInstantly = true,
287      cacheName = "icache"
288    )
289  )
290
291  // dcache prefetcher
292  val l2PrefetcherParameters = L2PrefetcherParameters(
293    enable = true,
294    _type = "bop", // "stream" or "bop"
295    streamParams = StreamPrefetchParameters(
296      streamCnt = 4,
297      streamSize = 4,
298      ageWidth = 4,
299      blockBytes = L2BlockSize,
300      reallocStreamOnMissInstantly = true,
301      cacheName = "dcache"
302    ),
303    bopParams = BOPParameters(
304      rrTableEntries = 256,
305      rrTagBits = 12,
306      scoreBits = 5,
307      roundMax = 50,
308      badScore = 1,
309      blockBytes = L2BlockSize,
310      nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large
311    ),
312  )
313
314  // load violation predict
315  val ResetTimeMax2Pow = 20 //1078576
316  val ResetTimeMin2Pow = 10 //1024
317  // wait table parameters
318  val WaitTableSize = 1024
319  val MemPredPCWidth = log2Up(WaitTableSize)
320  val LWTUse2BitCounter = true
321  // store set parameters
322  val SSITSize = WaitTableSize
323  val LFSTSize = 32
324  val SSIDWidth = log2Up(LFSTSize)
325  val LFSTWidth = 4
326  val StoreSetEnable = true // LWT will be disabled if SS is enabled
327
328  val loadExuConfigs = coreParams.loadExuConfigs
329  val storeExuConfigs = coreParams.storeExuConfigs
330
331  val intExuConfigs = coreParams.intExuConfigs
332
333  val fpExuConfigs = coreParams.fpExuConfigs
334
335  val exuConfigs = coreParams.exuConfigs
336
337}
338