1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import freechips.rocketchip.tile.MaxHartIdBits 42import system.SoCParamsKey 43import huancun._ 44import huancun.debug._ 45import xiangshan.cache.wpu.WPUParameters 46import coupledL2._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.min 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBits: Int = 39, 72 GPAddrBits: Int = 41, 73 HasFPU: Boolean = true, 74 HasVPU: Boolean = true, 75 HasCustomCSRCacheOp: Boolean = true, 76 FetchWidth: Int = 8, 77 AsidLength: Int = 16, 78 VmidLength: Int = 14, 79 EnableBPU: Boolean = true, 80 EnableBPD: Boolean = true, 81 EnableRAS: Boolean = true, 82 EnableLB: Boolean = false, 83 EnableLoop: Boolean = true, 84 EnableSC: Boolean = true, 85 EnbaleTlbDebug: Boolean = false, 86 EnableClockGate: Boolean = true, 87 EnableJal: Boolean = false, 88 EnableFauFTB: Boolean = true, 89 UbtbGHRLength: Int = 4, 90 // HistoryLength: Int = 512, 91 EnableGHistDiff: Boolean = true, 92 EnableCommitGHistDiff: Boolean = true, 93 UbtbSize: Int = 256, 94 FtbSize: Int = 2048, 95 RasSize: Int = 16, 96 RasSpecSize: Int = 32, 97 RasCtrSize: Int = 3, 98 CacheLineSize: Int = 512, 99 FtbWays: Int = 4, 100 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 101 // Sets Hist Tag 102 Seq(( 4096, 8, 8), 103 ( 4096, 13, 8), 104 ( 4096, 32, 8), 105 ( 4096, 119, 8)), 106 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 107 // Sets Hist Tag 108 Seq(( 256, 4, 9), 109 ( 256, 8, 9), 110 ( 512, 13, 9), 111 ( 512, 16, 9), 112 ( 512, 32, 9)), 113 SCNRows: Int = 512, 114 SCNTables: Int = 4, 115 SCCtrBits: Int = 6, 116 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 117 numBr: Int = 2, 118 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 119 (resp_in: BranchPredictionResp, p: Parameters) => { 120 val ftb = Module(new FTB()(p)) 121 val uftb = Module(new FauFTB()(p)) 122 val tage = Module(new Tage_SC()(p)) 123 val ras = Module(new RAS()(p)) 124 val ittage = Module(new ITTage()(p)) 125 val preds = Seq(uftb, tage, ftb, ittage, ras) 126 preds.map(_.io := DontCare) 127 128 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 129 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 130 131 uftb.io.in.bits.resp_in(0) := resp_in 132 tage.io.in.bits.resp_in(0) := uftb.io.out 133 ftb.io.in.bits.resp_in(0) := tage.io.out 134 ittage.io.in.bits.resp_in(0) := ftb.io.out 135 ras.io.in.bits.resp_in(0) := ittage.io.out 136 137 (preds, ras.io.out) 138 }, 139 ICacheForceMetaECCError: Boolean = false, 140 ICacheForceDataECCError: Boolean = false, 141 IBufSize: Int = 48, 142 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 143 DecodeWidth: Int = 6, 144 RenameWidth: Int = 6, 145 CommitWidth: Int = 8, 146 RobCommitWidth: Int = 8, 147 RabCommitWidth: Int = 6, 148 MaxUopSize: Int = 65, 149 EnableRenameSnapshot: Boolean = true, 150 RenameSnapshotNum: Int = 4, 151 FtqSize: Int = 64, 152 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 153 IntLogicRegs: Int = 32, 154 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 155 VecLogicRegs: Int = 32 + 15, // 15: tmp 156 V0LogicRegs: Int = 1, // V0 157 VlLogicRegs: Int = 1, // Vl 158 V0_IDX: Int = 0, 159 Vl_IDX: Int = 0, 160 NRPhyRegs: Int = 192, 161 VirtualLoadQueueSize: Int = 72, 162 LoadQueueRARSize: Int = 72, 163 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 164 RollbackGroupSize: Int = 8, 165 LoadQueueReplaySize: Int = 72, 166 LoadUncacheBufferSize: Int = 20, 167 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 168 StoreQueueSize: Int = 64, 169 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 170 StoreQueueForwardWithMask: Boolean = true, 171 VlsQueueSize: Int = 8, 172 RobSize: Int = 160, 173 RabSize: Int = 256, 174 VTypeBufferSize: Int = 64, // used to reorder vtype 175 IssueQueueSize: Int = 24, 176 IssueQueueCompEntrySize: Int = 16, 177 dpParams: DispatchParameters = DispatchParameters( 178 IntDqSize = 16, 179 FpDqSize = 16, 180 LsDqSize = 18, 181 IntDqDeqWidth = 8, 182 FpDqDeqWidth = 6, 183 VecDqDeqWidth = 6, 184 LsDqDeqWidth = 6, 185 ), 186 intPreg: PregParams = IntPregParams( 187 numEntries = 224, 188 numRead = None, 189 numWrite = None, 190 ), 191 fpPreg: PregParams = FpPregParams( 192 numEntries = 192, 193 numRead = None, 194 numWrite = None, 195 ), 196 vfPreg: VfPregParams = VfPregParams( 197 numEntries = 128, 198 numRead = None, 199 numWrite = None, 200 ), 201 v0Preg: V0PregParams = V0PregParams( 202 numEntries = 22, 203 numRead = None, 204 numWrite = None, 205 ), 206 vlPreg: VlPregParams = VlPregParams( 207 numEntries = 32, 208 numRead = None, 209 numWrite = None, 210 ), 211 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 212 LoadPipelineWidth: Int = 3, 213 StorePipelineWidth: Int = 2, 214 VecLoadPipelineWidth: Int = 2, 215 VecStorePipelineWidth: Int = 2, 216 VecMemSrcInWidth: Int = 2, 217 VecMemInstWbWidth: Int = 1, 218 VecMemDispatchWidth: Int = 1, 219 VecMemDispatchMaxNumber: Int = 16, 220 VecMemUnitStrideMaxFlowNum: Int = 2, 221 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 2, 2, 2, 2, 2), 222 StoreBufferSize: Int = 16, 223 StoreBufferThreshold: Int = 7, 224 EnsbufferWidth: Int = 2, 225 LoadDependencyWidth: Int = 2, 226 // ============ VLSU ============ 227 VlMergeBufferSize: Int = 16, 228 VsMergeBufferSize: Int = 16, 229 UopWritebackWidth: Int = 2, 230 VLUopWritebackWidth: Int = 2, 231 VSUopWritebackWidth: Int = 1, 232 VSegmentBufferSize: Int = 8, 233 // ============================== 234 UncacheBufferSize: Int = 4, 235 EnableLoadToLoadForward: Boolean = false, 236 EnableFastForward: Boolean = true, 237 EnableLdVioCheckAfterReset: Boolean = true, 238 EnableSoftPrefetchAfterReset: Boolean = true, 239 EnableCacheErrorAfterReset: Boolean = true, 240 EnableAccurateLoadError: Boolean = false, 241 EnableUncacheWriteOutstanding: Boolean = false, 242 EnableStorePrefetchAtIssue: Boolean = false, 243 EnableStorePrefetchAtCommit: Boolean = false, 244 EnableAtCommitMissTrigger: Boolean = true, 245 EnableStorePrefetchSMS: Boolean = false, 246 EnableStorePrefetchSPB: Boolean = false, 247 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 248 MMUVmidLen: Int = 14, 249 ReSelectLen: Int = 7, // load replay queue replay select counter len 250 iwpuParameters: WPUParameters = WPUParameters( 251 enWPU = false, 252 algoName = "mmru", 253 isICache = true, 254 ), 255 dwpuParameters: WPUParameters = WPUParameters( 256 enWPU = false, 257 algoName = "mmru", 258 enCfPred = false, 259 isICache = false, 260 ), 261 itlbParameters: TLBParameters = TLBParameters( 262 name = "itlb", 263 fetchi = true, 264 useDmode = false, 265 NWays = 48, 266 ), 267 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 268 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 269 ldtlbParameters: TLBParameters = TLBParameters( 270 name = "ldtlb", 271 NWays = 48, 272 outReplace = false, 273 partialStaticPMP = true, 274 outsideRecvFlush = true, 275 saveLevel = true, 276 lgMaxSize = 4 277 ), 278 sttlbParameters: TLBParameters = TLBParameters( 279 name = "sttlb", 280 NWays = 48, 281 outReplace = false, 282 partialStaticPMP = true, 283 outsideRecvFlush = true, 284 saveLevel = true, 285 lgMaxSize = 4 286 ), 287 hytlbParameters: TLBParameters = TLBParameters( 288 name = "hytlb", 289 NWays = 48, 290 outReplace = false, 291 partialStaticPMP = true, 292 outsideRecvFlush = true, 293 saveLevel = true, 294 lgMaxSize = 4 295 ), 296 pftlbParameters: TLBParameters = TLBParameters( 297 name = "pftlb", 298 NWays = 48, 299 outReplace = false, 300 partialStaticPMP = true, 301 outsideRecvFlush = true, 302 saveLevel = true, 303 lgMaxSize = 4 304 ), 305 l2ToL1tlbParameters: TLBParameters = TLBParameters( 306 name = "l2tlb", 307 NWays = 48, 308 outReplace = false, 309 partialStaticPMP = true, 310 outsideRecvFlush = true, 311 saveLevel = true 312 ), 313 refillBothTlb: Boolean = false, 314 btlbParameters: TLBParameters = TLBParameters( 315 name = "btlb", 316 NWays = 48, 317 ), 318 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 319 NumPerfCounters: Int = 16, 320 icacheParameters: ICacheParameters = ICacheParameters( 321 tagECC = Some("parity"), 322 dataECC = Some("parity"), 323 replacer = Some("setplru"), 324 ), 325 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 326 tagECC = Some("secded"), 327 dataECC = Some("secded"), 328 replacer = Some("setplru"), 329 nMissEntries = 16, 330 nProbeEntries = 8, 331 nReleaseEntries = 18, 332 nMaxPrefetchEntry = 6, 333 )), 334 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 335 name = "l2", 336 ways = 8, 337 sets = 1024, // default 512KB L2 338 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 339 coupledL2.prefetch.TPParameters()), 340 )), 341 L2NBanks: Int = 1, 342 usePTWRepeater: Boolean = false, 343 softTLB: Boolean = false, // dpi-c l1tlb debug only 344 softPTW: Boolean = false, // dpi-c l2tlb debug only 345 softPTWDelay: Int = 1 346){ 347 def vlWidth = log2Up(VLEN) + 1 348 349 /** 350 * the minimum element length of vector elements 351 */ 352 val minVecElen: Int = 8 353 354 /** 355 * the maximum number of elements in vector register 356 */ 357 val maxElemPerVreg: Int = VLEN / minVecElen 358 359 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 360 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 361 362 val intSchdParams = { 363 implicit val schdType: SchedulerType = IntScheduler() 364 SchdBlockParams(Seq( 365 IssueBlockParams(Seq( 366 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 367 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(1, 1))), true, 2), 368 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 369 IssueBlockParams(Seq( 370 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 371 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(3, 1))), true, 2), 372 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 373 IssueBlockParams(Seq( 374 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 375 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = 0, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(5, 1)))), 376 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 377 IssueBlockParams(Seq( 378 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 379 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(7, 1)))), 380 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 381 ), 382 numPregs = intPreg.numEntries, 383 numDeqOutside = 0, 384 schdType = schdType, 385 rfDataWidth = intPreg.dataCfg.dataWidth, 386 numUopIn = dpParams.IntDqDeqWidth, 387 ) 388 } 389 390 val fpSchdParams = { 391 implicit val schdType: SchedulerType = FpScheduler() 392 SchdBlockParams(Seq( 393 IssueBlockParams(Seq( 394 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 395 ), numEntries = 18, numEnq = 2, numComp = 16), 396 IssueBlockParams(Seq( 397 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 398 ), numEntries = 18, numEnq = 2, numComp = 16), 399 IssueBlockParams(Seq( 400 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 401 ), numEntries = 18, numEnq = 2, numComp = 16), 402 IssueBlockParams(Seq( 403 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 404 ), numEntries = 18, numEnq = 2, numComp = 16), 405 IssueBlockParams(Seq( 406 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 407 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 408 ), numEntries = 18, numEnq = 2, numComp = 16), 409 ), 410 numPregs = fpPreg.numEntries, 411 numDeqOutside = 0, 412 schdType = schdType, 413 rfDataWidth = fpPreg.dataCfg.dataWidth, 414 numUopIn = dpParams.VecDqDeqWidth, 415 ) 416 } 417 418 val vfSchdParams = { 419 implicit val schdType: SchedulerType = VfScheduler() 420 SchdBlockParams(Seq( 421 IssueBlockParams(Seq( 422 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 423 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = 1, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 424 ), numEntries = 16, numEnq = 2, numComp = 14), 425 IssueBlockParams(Seq( 426 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 427 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 428 ), numEntries = 16, numEnq = 2, numComp = 14), 429 IssueBlockParams(Seq( 430 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 431 ), numEntries = 10, numEnq = 2, numComp = 8), 432 ), 433 numPregs = vfPreg.numEntries, 434 numDeqOutside = 0, 435 schdType = schdType, 436 rfDataWidth = vfPreg.dataCfg.dataWidth, 437 numUopIn = dpParams.VecDqDeqWidth, 438 ) 439 } 440 441 val memSchdParams = { 442 implicit val schdType: SchedulerType = MemScheduler() 443 val rfDataWidth = 64 444 445 SchdBlockParams(Seq( 446 IssueBlockParams(Seq( 447 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(11, 1)))), 448 ), numEntries = 16, numEnq = 2, numComp = 14), 449 IssueBlockParams(Seq( 450 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(8, 1)))), 451 ), numEntries = 16, numEnq = 2, numComp = 14), 452 IssueBlockParams(Seq( 453 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 454 ), numEntries = 16, numEnq = 2, numComp = 14), 455 IssueBlockParams(Seq( 456 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 457 ), numEntries = 16, numEnq = 2, numComp = 14), 458 IssueBlockParams(Seq( 459 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 460 ), numEntries = 16, numEnq = 2, numComp = 14), 461 IssueBlockParams(Seq( 462 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 463 ), numEntries = 16, numEnq = 2, numComp = 14), 464 IssueBlockParams(Seq( 465 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 466 ), numEntries = 16, numEnq = 2, numComp = 14), 467 IssueBlockParams(Seq( 468 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(10, 1), FpRD(12, 0)))), 469 ), numEntries = 16, numEnq = 2, numComp = 14), 470 IssueBlockParams(Seq( 471 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(11, 1), FpRD(13, 0)))), 472 ), numEntries = 16, numEnq = 2, numComp = 14), 473 ), 474 numPregs = intPreg.numEntries max vfPreg.numEntries, 475 numDeqOutside = 0, 476 schdType = schdType, 477 rfDataWidth = rfDataWidth, 478 numUopIn = dpParams.LsDqDeqWidth, 479 ) 480 } 481 482 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 483 484 def iqWakeUpParams = { 485 Seq( 486 WakeUpConfig( 487 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 488 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 489 ), 490 WakeUpConfig( 491 Seq("FEX0", "FEX1", "FEX2", "FEX3", "LDU0", "LDU1", "LDU2") -> 492 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 493 ), 494 WakeUpConfig( 495 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 496 Seq("STD0", "STD1") 497 ), 498 WakeUpConfig( 499 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 500 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "VFEX4") 501 ), 502 ).flatten 503 } 504 505 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 506 507 val backendParams: BackendParams = backend.BackendParams( 508 Map( 509 IntScheduler() -> intSchdParams, 510 FpScheduler() -> fpSchdParams, 511 VfScheduler() -> vfSchdParams, 512 MemScheduler() -> memSchdParams, 513 ), 514 Seq( 515 intPreg, 516 fpPreg, 517 vfPreg, 518 v0Preg, 519 vlPreg, 520 fakeIntPreg 521 ), 522 iqWakeUpParams, 523 ) 524} 525 526case object DebugOptionsKey extends Field[DebugOptions] 527 528case class DebugOptions 529( 530 FPGAPlatform: Boolean = false, 531 ResetGen: Boolean = false, 532 EnableDifftest: Boolean = false, 533 AlwaysBasicDiff: Boolean = true, 534 EnableDebug: Boolean = false, 535 EnablePerfDebug: Boolean = true, 536 UseDRAMSim: Boolean = false, 537 EnableConstantin: Boolean = false, 538 EnableChiselDB: Boolean = false, 539 AlwaysBasicDB: Boolean = true, 540 EnableTopDown: Boolean = false, 541 EnableRollingDB: Boolean = false 542) 543 544trait HasXSParameter { 545 546 implicit val p: Parameters 547 548 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 549 def NodeIDWidth = p(SoCParamsKey).NodeIDWidth // NodeID width among NoC 550 551 def coreParams = p(XSCoreParamsKey) 552 def env = p(DebugOptionsKey) 553 554 def XLEN = coreParams.XLEN 555 def VLEN = coreParams.VLEN 556 def ELEN = coreParams.ELEN 557 def HSXLEN = coreParams.HSXLEN 558 val minFLen = 32 559 val fLen = 64 560 def hartIdLen = p(MaxHartIdBits) 561 val xLen = XLEN 562 563 def HasMExtension = coreParams.HasMExtension 564 def HasCExtension = coreParams.HasCExtension 565 def HasHExtension = coreParams.HasHExtension 566 def HasDiv = coreParams.HasDiv 567 def HasIcache = coreParams.HasICache 568 def HasDcache = coreParams.HasDCache 569 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 570 def GPAddrBits = coreParams.GPAddrBits 571 def VAddrBits = { 572 if(HasHExtension){ 573 coreParams.GPAddrBits 574 }else{ 575 coreParams.VAddrBits 576 } 577 } // VAddrBits is Virtual Memory addr bits 578 579 def AsidLength = coreParams.AsidLength 580 def VmidLength = coreParams.VmidLength 581 def ReSelectLen = coreParams.ReSelectLen 582 def AddrBytes = AddrBits / 8 // unused 583 def DataBits = XLEN 584 def DataBytes = DataBits / 8 585 def VDataBytes = VLEN / 8 586 def HasFPU = coreParams.HasFPU 587 def HasVPU = coreParams.HasVPU 588 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 589 def FetchWidth = coreParams.FetchWidth 590 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 591 def EnableBPU = coreParams.EnableBPU 592 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 593 def EnableRAS = coreParams.EnableRAS 594 def EnableLB = coreParams.EnableLB 595 def EnableLoop = coreParams.EnableLoop 596 def EnableSC = coreParams.EnableSC 597 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 598 def HistoryLength = coreParams.HistoryLength 599 def EnableGHistDiff = coreParams.EnableGHistDiff 600 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 601 def EnableClockGate = coreParams.EnableClockGate 602 def UbtbGHRLength = coreParams.UbtbGHRLength 603 def UbtbSize = coreParams.UbtbSize 604 def EnableFauFTB = coreParams.EnableFauFTB 605 def FtbSize = coreParams.FtbSize 606 def FtbWays = coreParams.FtbWays 607 def RasSize = coreParams.RasSize 608 def RasSpecSize = coreParams.RasSpecSize 609 def RasCtrSize = coreParams.RasCtrSize 610 611 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 612 coreParams.branchPredictor(resp_in, p) 613 } 614 def numBr = coreParams.numBr 615 def TageTableInfos = coreParams.TageTableInfos 616 def TageBanks = coreParams.numBr 617 def SCNRows = coreParams.SCNRows 618 def SCCtrBits = coreParams.SCCtrBits 619 def SCHistLens = coreParams.SCHistLens 620 def SCNTables = coreParams.SCNTables 621 622 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 623 case ((n, cb), h) => (n, cb, h) 624 } 625 def ITTageTableInfos = coreParams.ITTageTableInfos 626 type FoldedHistoryInfo = Tuple2[Int, Int] 627 def foldedGHistInfos = 628 (TageTableInfos.map{ case (nRows, h, t) => 629 if (h > 0) 630 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 631 else 632 Set[FoldedHistoryInfo]() 633 }.reduce(_++_).toSet ++ 634 SCTableInfos.map{ case (nRows, _, h) => 635 if (h > 0) 636 Set((h, min(log2Ceil(nRows/TageBanks), h))) 637 else 638 Set[FoldedHistoryInfo]() 639 }.reduce(_++_).toSet ++ 640 ITTageTableInfos.map{ case (nRows, h, t) => 641 if (h > 0) 642 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 643 else 644 Set[FoldedHistoryInfo]() 645 }.reduce(_++_) ++ 646 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 647 ).toList 648 649 650 651 def CacheLineSize = coreParams.CacheLineSize 652 def CacheLineHalfWord = CacheLineSize / 16 653 def ExtHistoryLength = HistoryLength + 64 654 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 655 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 656 def IBufSize = coreParams.IBufSize 657 def IBufNBank = coreParams.IBufNBank 658 def backendParams: BackendParams = coreParams.backendParams 659 def DecodeWidth = coreParams.DecodeWidth 660 def RenameWidth = coreParams.RenameWidth 661 def CommitWidth = coreParams.CommitWidth 662 def RobCommitWidth = coreParams.RobCommitWidth 663 def RabCommitWidth = coreParams.RabCommitWidth 664 def MaxUopSize = coreParams.MaxUopSize 665 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 666 def RenameSnapshotNum = coreParams.RenameSnapshotNum 667 def FtqSize = coreParams.FtqSize 668 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 669 def IntLogicRegs = coreParams.IntLogicRegs 670 def FpLogicRegs = coreParams.FpLogicRegs 671 def VecLogicRegs = coreParams.VecLogicRegs 672 def V0LogicRegs = coreParams.V0LogicRegs 673 def VlLogicRegs = coreParams.VlLogicRegs 674 def V0_IDX = coreParams.V0_IDX 675 def Vl_IDX = coreParams.Vl_IDX 676 def IntPhyRegs = coreParams.intPreg.numEntries 677 def FpPhyRegs = coreParams.fpPreg.numEntries 678 def VfPhyRegs = coreParams.vfPreg.numEntries 679 def V0PhyRegs = coreParams.v0Preg.numEntries 680 def VlPhyRegs = coreParams.vlPreg.numEntries 681 def MaxPhyPregs = IntPhyRegs max VfPhyRegs 682 def PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(FpPhyRegs) max log2Up(VfPhyRegs) 683 def RobSize = coreParams.RobSize 684 def RabSize = coreParams.RabSize 685 def VTypeBufferSize = coreParams.VTypeBufferSize 686 /** 687 * the minimum element length of vector elements 688 */ 689 def minVecElen: Int = coreParams.minVecElen 690 691 /** 692 * the maximum number of elements in vector register 693 */ 694 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 695 696 def IntRefCounterWidth = log2Ceil(RobSize) 697 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 698 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 699 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 700 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 701 def LoadQueueRARSize = coreParams.LoadQueueRARSize 702 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 703 def RollbackGroupSize = coreParams.RollbackGroupSize 704 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 705 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 706 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 707 def StoreQueueSize = coreParams.StoreQueueSize 708 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 709 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 710 def VlsQueueSize = coreParams.VlsQueueSize 711 def dpParams = coreParams.dpParams 712 713 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 714 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 715 716 def NumRedirect = backendParams.numRedirect 717 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 718 def FtqRedirectAheadNum = NumRedirect 719 def LoadPipelineWidth = coreParams.LoadPipelineWidth 720 def StorePipelineWidth = coreParams.StorePipelineWidth 721 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 722 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 723 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 724 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 725 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 726 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 727 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 728 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 729 def StoreBufferSize = coreParams.StoreBufferSize 730 def StoreBufferThreshold = coreParams.StoreBufferThreshold 731 def EnsbufferWidth = coreParams.EnsbufferWidth 732 def LoadDependencyWidth = coreParams.LoadDependencyWidth 733 def VlMergeBufferSize = coreParams.VlMergeBufferSize 734 def VsMergeBufferSize = coreParams.VsMergeBufferSize 735 def UopWritebackWidth = coreParams.UopWritebackWidth 736 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 737 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 738 def VSegmentBufferSize = coreParams.VSegmentBufferSize 739 def UncacheBufferSize = coreParams.UncacheBufferSize 740 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 741 def EnableFastForward = coreParams.EnableFastForward 742 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 743 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 744 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 745 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 746 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 747 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 748 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 749 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 750 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 751 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 752 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 753 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 754 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 755 def asidLen = coreParams.MMUAsidLen 756 def vmidLen = coreParams.MMUVmidLen 757 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 758 def refillBothTlb = coreParams.refillBothTlb 759 def iwpuParam = coreParams.iwpuParameters 760 def dwpuParam = coreParams.dwpuParameters 761 def itlbParams = coreParams.itlbParameters 762 def ldtlbParams = coreParams.ldtlbParameters 763 def sttlbParams = coreParams.sttlbParameters 764 def hytlbParams = coreParams.hytlbParameters 765 def pftlbParams = coreParams.pftlbParameters 766 def l2ToL1Params = coreParams.l2ToL1tlbParameters 767 def btlbParams = coreParams.btlbParameters 768 def l2tlbParams = coreParams.l2tlbParameters 769 def NumPerfCounters = coreParams.NumPerfCounters 770 771 def instBytes = if (HasCExtension) 2 else 4 772 def instOffsetBits = log2Ceil(instBytes) 773 774 def icacheParameters = coreParams.icacheParameters 775 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 776 777 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 778 // for constrained LR/SC loop 779 def LRSCCycles = 64 780 // for lr storm 781 def LRSCBackOff = 8 782 783 // cache hierarchy configurations 784 def l1BusDataWidth = 256 785 786 // load violation predict 787 def ResetTimeMax2Pow = 20 //1078576 788 def ResetTimeMin2Pow = 10 //1024 789 // wait table parameters 790 def WaitTableSize = 1024 791 def MemPredPCWidth = log2Up(WaitTableSize) 792 def LWTUse2BitCounter = true 793 // store set parameters 794 def SSITSize = WaitTableSize 795 def LFSTSize = 32 796 def SSIDWidth = log2Up(LFSTSize) 797 def LFSTWidth = 4 798 def StoreSetEnable = true // LWT will be disabled if SS is enabled 799 def LFSTEnable = true 800 801 def PCntIncrStep: Int = 6 802 def numPCntHc: Int = 25 803 def numPCntPtw: Int = 19 804 805 def numCSRPCntFrontend = 8 806 def numCSRPCntCtrl = 8 807 def numCSRPCntLsu = 8 808 def numCSRPCntHc = 5 809 def printEventCoding = true 810 811 // Parameters for Sdtrig extension 812 protected def TriggerNum = 4 813 protected def TriggerChainMaxLength = 2 814} 815