1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.dispatch.DispatchParameters 26import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters} 27import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 28import xiangshan.cache.mmu.{L2TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30 31case object XSCoreParamsKey extends Field[XSCoreParameters] 32 33case class XSCoreParameters 34( 35 HasPrefetch: Boolean = false, 36 HartId: Int = 0, 37 XLEN: Int = 64, 38 HasMExtension: Boolean = true, 39 HasCExtension: Boolean = true, 40 HasDiv: Boolean = true, 41 HasICache: Boolean = true, 42 HasDCache: Boolean = true, 43 AddrBits: Int = 64, 44 VAddrBits: Int = 39, 45 PAddrBits: Int = 40, 46 HasFPU: Boolean = true, 47 FetchWidth: Int = 8, 48 EnableBPU: Boolean = true, 49 EnableBPD: Boolean = true, 50 EnableRAS: Boolean = true, 51 EnableLB: Boolean = false, 52 EnableLoop: Boolean = true, 53 EnableSC: Boolean = true, 54 EnbaleTlbDebug: Boolean = false, 55 EnableJal: Boolean = false, 56 EnableUBTB: Boolean = true, 57 HistoryLength: Int = 64, 58 BtbSize: Int = 2048, 59 JbtacSize: Int = 1024, 60 JbtacBanks: Int = 8, 61 RasSize: Int = 16, 62 CacheLineSize: Int = 512, 63 UBtbWays: Int = 16, 64 BtbWays: Int = 2, 65 66 EnableL1plusPrefetcher: Boolean = true, 67 IBufSize: Int = 48, 68 DecodeWidth: Int = 6, 69 RenameWidth: Int = 6, 70 CommitWidth: Int = 6, 71 BrqSize: Int = 32, 72 FtqSize: Int = 48, 73 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 74 IssQueSize: Int = 16, 75 NRPhyRegs: Int = 160, 76 NRIntReadPorts: Int = 14, 77 NRIntWritePorts: Int = 8, 78 NRFpReadPorts: Int = 14, 79 NRFpWritePorts: Int = 8, 80 LoadQueueSize: Int = 64, 81 StoreQueueSize: Int = 48, 82 RoqSize: Int = 192, 83 dpParams: DispatchParameters = DispatchParameters( 84 IntDqSize = 16, 85 FpDqSize = 16, 86 LsDqSize = 16, 87 IntDqDeqWidth = 4, 88 FpDqDeqWidth = 4, 89 LsDqDeqWidth = 4 90 ), 91 exuParameters: ExuParameters = ExuParameters( 92 JmpCnt = 1, 93 AluCnt = 4, 94 MulCnt = 0, 95 MduCnt = 2, 96 FmacCnt = 4, 97 FmiscCnt = 2, 98 FmiscDivSqrtCnt = 0, 99 LduCnt = 2, 100 StuCnt = 2 101 ), 102 LoadPipelineWidth: Int = 2, 103 StorePipelineWidth: Int = 2, 104 StoreBufferSize: Int = 16, 105 StoreBufferThreshold: Int = 7, 106 RefillSize: Int = 512, 107 TlbEntrySize: Int = 32, 108 TlbSPEntrySize: Int = 4, 109 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 110 NumPerfCounters: Int = 16, 111 icacheParameters: ICacheParameters = ICacheParameters( 112 tagECC = Some("parity"), 113 dataECC = Some("parity"), 114 replacer = Some("setplru"), 115 nMissEntries = 2 116 ), 117 l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters( 118 tagECC = Some("secded"), 119 dataECC = Some("secded"), 120 replacer = Some("setplru"), 121 nMissEntries = 8 122 ), 123 dcacheParameters: DCacheParameters = DCacheParameters( 124 tagECC = Some("secded"), 125 dataECC = Some("secded"), 126 replacer = Some("setplru"), 127 nMissEntries = 16, 128 nProbeEntries = 16, 129 nReleaseEntries = 16, 130 nStoreReplayEntries = 16 131 ), 132 L2Size: Int = 512 * 1024, // 512KB 133 L2NWays: Int = 8, 134 usePTWRepeater: Boolean = false, 135 useFakePTW: Boolean = false, 136 useFakeDCache: Boolean = false, 137 useFakeL1plusCache: Boolean = false, 138 useFakeL2Cache: Boolean = false 139){ 140 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 141 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) 142 143 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 144 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) ++ 145 Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 146 147 val fpExuConfigs = 148 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 149 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 150 151 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 152} 153 154case object DebugOptionsKey extends Field[DebugOptions] 155 156case class DebugOptions 157( 158 FPGAPlatform: Boolean = true, 159 EnableDebug: Boolean = true, 160 EnablePerfDebug: Boolean = true, 161 UseDRAMSim: Boolean = false 162) 163 164trait HasXSParameter { 165 166 implicit val p: Parameters 167 168 val coreParams = p(XSCoreParamsKey) 169 val env = p(DebugOptionsKey) 170 171 val XLEN = coreParams.XLEN 172 val hardId = coreParams.HartId 173 val minFLen = 32 174 val fLen = 64 175 def xLen = XLEN 176 177 val HasMExtension = coreParams.HasMExtension 178 val HasCExtension = coreParams.HasCExtension 179 val HasDiv = coreParams.HasDiv 180 val HasIcache = coreParams.HasICache 181 val HasDcache = coreParams.HasDCache 182 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 183 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 184 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 185 val AddrBytes = AddrBits / 8 // unused 186 val DataBits = XLEN 187 val DataBytes = DataBits / 8 188 val HasFPU = coreParams.HasFPU 189 val FetchWidth = coreParams.FetchWidth 190 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 191 val EnableBPU = coreParams.EnableBPU 192 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 193 val EnableRAS = coreParams.EnableRAS 194 val EnableLB = coreParams.EnableLB 195 val EnableLoop = coreParams.EnableLoop 196 val EnableSC = coreParams.EnableSC 197 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 198 val HistoryLength = coreParams.HistoryLength 199 val BtbSize = coreParams.BtbSize 200 // val BtbWays = 4 201 val BtbBanks = PredictWidth 202 // val BtbSets = BtbSize / BtbWays 203 val JbtacSize = coreParams.JbtacSize 204 val JbtacBanks = coreParams.JbtacBanks 205 val RasSize = coreParams.RasSize 206 val CacheLineSize = coreParams.CacheLineSize 207 val CacheLineHalfWord = CacheLineSize / 16 208 val ExtHistoryLength = HistoryLength + 64 209 val UBtbWays = coreParams.UBtbWays 210 val BtbWays = coreParams.BtbWays 211 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 212 val IBufSize = coreParams.IBufSize 213 val DecodeWidth = coreParams.DecodeWidth 214 val RenameWidth = coreParams.RenameWidth 215 val CommitWidth = coreParams.CommitWidth 216 val BrqSize = coreParams.BrqSize 217 val FtqSize = coreParams.FtqSize 218 val IssQueSize = coreParams.IssQueSize 219 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 220 val BrTagWidth = log2Up(BrqSize) 221 val NRPhyRegs = coreParams.NRPhyRegs 222 val PhyRegIdxWidth = log2Up(NRPhyRegs) 223 val RoqSize = coreParams.RoqSize 224 val LoadQueueSize = coreParams.LoadQueueSize 225 val StoreQueueSize = coreParams.StoreQueueSize 226 val dpParams = coreParams.dpParams 227 val exuParameters = coreParams.exuParameters 228 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 229 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 230 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 231 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 232 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 233 val LoadPipelineWidth = coreParams.LoadPipelineWidth 234 val StorePipelineWidth = coreParams.StorePipelineWidth 235 val StoreBufferSize = coreParams.StoreBufferSize 236 val StoreBufferThreshold = coreParams.StoreBufferThreshold 237 val RefillSize = coreParams.RefillSize 238 val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 239 val TlbEntrySize = coreParams.TlbEntrySize 240 val TlbSPEntrySize = coreParams.TlbSPEntrySize 241 val l2tlbParams = coreParams.l2tlbParameters 242 val NumPerfCounters = coreParams.NumPerfCounters 243 244 val instBytes = if (HasCExtension) 2 else 4 245 val instOffsetBits = log2Ceil(instBytes) 246 247 val icacheParameters = coreParams.icacheParameters 248 val l1plusCacheParameters = coreParams.l1plusCacheParameters 249 val dcacheParameters = coreParams.dcacheParameters 250 251 val LRSCCycles = 100 252 253 254 // cache hierarchy configurations 255 val l1BusDataWidth = 256 256 257 val usePTWRepeater = coreParams.usePTWRepeater 258 val useFakeDCache = coreParams.useFakeDCache 259 val useFakePTW = coreParams.useFakePTW 260 val useFakeL1plusCache = coreParams.useFakeL1plusCache 261 // L2 configurations 262 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 263 val L1BusWidth = 256 264 val L2Size = coreParams.L2Size 265 val L2BlockSize = 64 266 val L2NWays = coreParams.L2NWays 267 val L2NSets = L2Size / L2BlockSize / L2NWays 268 269 // L3 configurations 270 val L2BusWidth = 256 271 272 // icache prefetcher 273 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 274 enable = true, 275 _type = "stream", 276 streamParams = StreamPrefetchParameters( 277 streamCnt = 2, 278 streamSize = 4, 279 ageWidth = 4, 280 blockBytes = l1plusCacheParameters.blockBytes, 281 reallocStreamOnMissInstantly = true, 282 cacheName = "icache" 283 ) 284 ) 285 286 // dcache prefetcher 287 val l2PrefetcherParameters = L2PrefetcherParameters( 288 enable = true, 289 _type = "bop", // "stream" or "bop" 290 streamParams = StreamPrefetchParameters( 291 streamCnt = 4, 292 streamSize = 4, 293 ageWidth = 4, 294 blockBytes = L2BlockSize, 295 reallocStreamOnMissInstantly = true, 296 cacheName = "dcache" 297 ), 298 bopParams = BOPParameters( 299 rrTableEntries = 256, 300 rrTagBits = 12, 301 scoreBits = 5, 302 roundMax = 50, 303 badScore = 1, 304 blockBytes = L2BlockSize, 305 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 306 ), 307 ) 308 309 // load violation predict 310 val ResetTimeMax2Pow = 20 //1078576 311 val ResetTimeMin2Pow = 10 //1024 312 // wait table parameters 313 val WaitTableSize = 1024 314 val MemPredPCWidth = log2Up(WaitTableSize) 315 val LWTUse2BitCounter = true 316 // store set parameters 317 val SSITSize = WaitTableSize 318 val LFSTSize = 32 319 val SSIDWidth = log2Up(LFSTSize) 320 val LFSTWidth = 4 321 val StoreSetEnable = true // LWT will be disabled if SS is enabled 322 323 val loadExuConfigs = coreParams.loadExuConfigs 324 val storeExuConfigs = coreParams.storeExuConfigs 325 326 val intExuConfigs = coreParams.intExuConfigs 327 328 val fpExuConfigs = coreParams.fpExuConfigs 329 330 val exuConfigs = coreParams.exuConfigs 331 332} 333