xref: /XiangShan/src/main/scala/xiangshan/Parameters.scala (revision d4aca96cccdcdafa80dd344996e18d1978a01af7) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import chipsalliance.rocketchip.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import xiangshan.backend.exu._
23import xiangshan.backend.fu._
24import xiangshan.backend.fu.fpu._
25import xiangshan.backend.dispatch.DispatchParameters
26import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters}
27import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters}
28import freechips.rocketchip.diplomacy.AddressSet
29
30case object XSCoreParamsKey extends Field[XSCoreParameters]
31
32case class XSCoreParameters
33(
34  HasPrefetch: Boolean = false,
35  HartId: Int = 0,
36  XLEN: Int = 64,
37  HasMExtension: Boolean = true,
38  HasCExtension: Boolean = true,
39  HasDiv: Boolean = true,
40  HasICache: Boolean = true,
41  HasDCache: Boolean = true,
42  AddrBits: Int = 64,
43  VAddrBits: Int = 39,
44  PAddrBits: Int = 40,
45  HasFPU: Boolean = true,
46  FetchWidth: Int = 8,
47  EnableBPU: Boolean = true,
48  EnableBPD: Boolean = true,
49  EnableRAS: Boolean = true,
50  EnableLB: Boolean = false,
51  EnableLoop: Boolean = true,
52  EnableSC: Boolean = true,
53  EnbaleTlbDebug: Boolean = false,
54  EnableJal: Boolean = false,
55  EnableUBTB: Boolean = true,
56  HistoryLength: Int = 64,
57  BtbSize: Int = 2048,
58  JbtacSize: Int = 1024,
59  JbtacBanks: Int = 8,
60  RasSize: Int = 16,
61  CacheLineSize: Int = 512,
62  UBtbWays: Int = 16,
63  BtbWays: Int = 2,
64
65  EnableL1plusPrefetcher: Boolean = true,
66  IBufSize: Int = 48,
67  DecodeWidth: Int = 6,
68  RenameWidth: Int = 6,
69  CommitWidth: Int = 6,
70  BrqSize: Int = 32,
71  FtqSize: Int = 48,
72  EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false
73  IssQueSize: Int = 16,
74  NRPhyRegs: Int = 160,
75  NRIntReadPorts: Int = 14,
76  NRIntWritePorts: Int = 8,
77  NRFpReadPorts: Int = 14,
78  NRFpWritePorts: Int = 8,
79  LoadQueueSize: Int = 64,
80  StoreQueueSize: Int = 48,
81  RoqSize: Int = 192,
82  dpParams: DispatchParameters = DispatchParameters(
83    IntDqSize = 16,
84    FpDqSize = 16,
85    LsDqSize = 16,
86    IntDqDeqWidth = 4,
87    FpDqDeqWidth = 4,
88    LsDqDeqWidth = 4
89  ),
90  exuParameters: ExuParameters = ExuParameters(
91    JmpCnt = 1,
92    AluCnt = 4,
93    MulCnt = 0,
94    MduCnt = 2,
95    FmacCnt = 4,
96    FmiscCnt = 2,
97    FmiscDivSqrtCnt = 0,
98    LduCnt = 2,
99    StuCnt = 2
100  ),
101  LoadPipelineWidth: Int = 2,
102  StorePipelineWidth: Int = 2,
103  StoreBufferSize: Int = 16,
104  StoreBufferThreshold: Int = 7,
105  RefillSize: Int = 512,
106  TlbEntrySize: Int = 32,
107  TlbSPEntrySize: Int = 4,
108  PtwL3EntrySize: Int = 4096, //(256 * 16) or 512
109  PtwSPEntrySize: Int = 16,
110  PtwL1EntrySize: Int = 16,
111  PtwL2EntrySize: Int = 2048, //(256 * 8)
112  PtwMissQueueSize: Int = 8,
113  NumPerfCounters: Int = 16,
114  icacheParameters: ICacheParameters = ICacheParameters(
115    tagECC = Some("parity"),
116    dataECC = Some("parity"),
117    replacer = Some("setplru"),
118    nMissEntries = 2
119  ),
120  l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters(
121    tagECC = Some("secded"),
122    dataECC = Some("secded"),
123    replacer = Some("setplru"),
124    nMissEntries = 8
125  ),
126  dcacheParameters: DCacheParameters = DCacheParameters(
127    tagECC = Some("secded"),
128    dataECC = Some("secded"),
129    replacer = Some("setplru"),
130    nMissEntries = 16,
131    nProbeEntries = 16,
132    nReleaseEntries = 16,
133    nStoreReplayEntries = 16
134  ),
135  L2Size: Int = 512 * 1024, // 512KB
136  L2NWays: Int = 8,
137  usePTWRepeater: Boolean = false,
138  useFakePTW: Boolean = false,
139  useFakeDCache: Boolean = false,
140  useFakeL1plusCache: Boolean = false,
141  useFakeL2Cache: Boolean = false
142){
143  val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg)
144  val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StExeUnitCfg)
145
146  val intExuConfigs = Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++
147    Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg
148
149  val fpExuConfigs =
150    Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++
151      Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg)
152
153  val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs
154}
155
156case object DebugOptionsKey extends Field[DebugOptions]
157
158case class DebugOptions
159(
160  FPGAPlatform: Boolean = true,
161  EnableDebug: Boolean = true,
162  EnablePerfDebug: Boolean = true,
163  UseDRAMSim: Boolean = false
164)
165
166trait HasXSParameter {
167
168  implicit val p: Parameters
169
170  val coreParams = p(XSCoreParamsKey)
171  val env = p(DebugOptionsKey)
172
173  val XLEN = coreParams.XLEN
174  val hardId = coreParams.HartId
175  val minFLen = 32
176  val fLen = 64
177  def xLen = XLEN
178
179  val HasMExtension = coreParams.HasMExtension
180  val HasCExtension = coreParams.HasCExtension
181  val HasDiv = coreParams.HasDiv
182  val HasIcache = coreParams.HasICache
183  val HasDcache = coreParams.HasDCache
184  val AddrBits = coreParams.AddrBits // AddrBits is used in some cases
185  val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits
186  val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits
187  val AddrBytes = AddrBits / 8 // unused
188  val DataBits = XLEN
189  val DataBytes = DataBits / 8
190  val HasFPU = coreParams.HasFPU
191  val FetchWidth = coreParams.FetchWidth
192  val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1)
193  val EnableBPU = coreParams.EnableBPU
194  val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3
195  val EnableRAS = coreParams.EnableRAS
196  val EnableLB = coreParams.EnableLB
197  val EnableLoop = coreParams.EnableLoop
198  val EnableSC = coreParams.EnableSC
199  val EnbaleTlbDebug = coreParams.EnbaleTlbDebug
200  val HistoryLength = coreParams.HistoryLength
201  val BtbSize = coreParams.BtbSize
202  // val BtbWays = 4
203  val BtbBanks = PredictWidth
204  // val BtbSets = BtbSize / BtbWays
205  val JbtacSize = coreParams.JbtacSize
206  val JbtacBanks = coreParams.JbtacBanks
207  val RasSize = coreParams.RasSize
208  val CacheLineSize = coreParams.CacheLineSize
209  val CacheLineHalfWord = CacheLineSize / 16
210  val ExtHistoryLength = HistoryLength + 64
211  val UBtbWays = coreParams.UBtbWays
212  val BtbWays = coreParams.BtbWays
213  val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher
214  val IBufSize = coreParams.IBufSize
215  val DecodeWidth = coreParams.DecodeWidth
216  val RenameWidth = coreParams.RenameWidth
217  val CommitWidth = coreParams.CommitWidth
218  val BrqSize = coreParams.BrqSize
219  val FtqSize = coreParams.FtqSize
220  val IssQueSize = coreParams.IssQueSize
221  val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp
222  val BrTagWidth = log2Up(BrqSize)
223  val NRPhyRegs = coreParams.NRPhyRegs
224  val PhyRegIdxWidth = log2Up(NRPhyRegs)
225  val RoqSize = coreParams.RoqSize
226  val LoadQueueSize = coreParams.LoadQueueSize
227  val StoreQueueSize = coreParams.StoreQueueSize
228  val dpParams = coreParams.dpParams
229  val exuParameters = coreParams.exuParameters
230  val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt
231  val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts
232  val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt
233  val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt
234  val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt
235  val LoadPipelineWidth = coreParams.LoadPipelineWidth
236  val StorePipelineWidth = coreParams.StorePipelineWidth
237  val StoreBufferSize = coreParams.StoreBufferSize
238  val StoreBufferThreshold = coreParams.StoreBufferThreshold
239  val RefillSize = coreParams.RefillSize
240  val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth
241  val TlbEntrySize = coreParams.TlbEntrySize
242  val TlbSPEntrySize = coreParams.TlbSPEntrySize
243  val PtwL3EntrySize = coreParams.PtwL3EntrySize
244  val PtwSPEntrySize = coreParams.PtwSPEntrySize
245  val PtwL1EntrySize = coreParams.PtwL1EntrySize
246  val PtwL2EntrySize = coreParams.PtwL2EntrySize
247  val PtwMissQueueSize = coreParams.PtwMissQueueSize
248  val NumPerfCounters = coreParams.NumPerfCounters
249
250  val instBytes = if (HasCExtension) 2 else 4
251  val instOffsetBits = log2Ceil(instBytes)
252
253  val icacheParameters = coreParams.icacheParameters
254  val l1plusCacheParameters = coreParams.l1plusCacheParameters
255  val dcacheParameters = coreParams.dcacheParameters
256
257  val LRSCCycles = 100
258
259
260  // cache hierarchy configurations
261  val l1BusDataWidth = 256
262
263  val usePTWRepeater = coreParams.usePTWRepeater
264  val useFakeDCache = coreParams.useFakeDCache
265  val useFakePTW = coreParams.useFakePTW
266  val useFakeL1plusCache = coreParams.useFakeL1plusCache
267  // L2 configurations
268  val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache
269  val L1BusWidth = 256
270  val L2Size = coreParams.L2Size
271  val L2BlockSize = 64
272  val L2NWays = coreParams.L2NWays
273  val L2NSets = L2Size / L2BlockSize / L2NWays
274
275  // L3 configurations
276  val L2BusWidth = 256
277
278  // icache prefetcher
279  val l1plusPrefetcherParameters = L1plusPrefetcherParameters(
280    enable = true,
281    _type = "stream",
282    streamParams = StreamPrefetchParameters(
283      streamCnt = 2,
284      streamSize = 4,
285      ageWidth = 4,
286      blockBytes = l1plusCacheParameters.blockBytes,
287      reallocStreamOnMissInstantly = true,
288      cacheName = "icache"
289    )
290  )
291
292  // dcache prefetcher
293  val l2PrefetcherParameters = L2PrefetcherParameters(
294    enable = true,
295    _type = "bop", // "stream" or "bop"
296    streamParams = StreamPrefetchParameters(
297      streamCnt = 4,
298      streamSize = 4,
299      ageWidth = 4,
300      blockBytes = L2BlockSize,
301      reallocStreamOnMissInstantly = true,
302      cacheName = "dcache"
303    ),
304    bopParams = BOPParameters(
305      rrTableEntries = 256,
306      rrTagBits = 12,
307      scoreBits = 5,
308      roundMax = 50,
309      badScore = 1,
310      blockBytes = L2BlockSize,
311      nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large
312    ),
313  )
314
315  // load violation predict
316  val ResetTimeMax2Pow = 20 //1078576
317  val ResetTimeMin2Pow = 10 //1024
318  // wait table parameters
319  val WaitTableSize = 1024
320  val MemPredPCWidth = log2Up(WaitTableSize)
321  val LWTUse2BitCounter = true
322  // store set parameters
323  val SSITSize = WaitTableSize
324  val LFSTSize = 32
325  val SSIDWidth = log2Up(LFSTSize)
326  val LFSTWidth = 4
327  val StoreSetEnable = true // LWT will be disabled if SS is enabled
328
329  val loadExuConfigs = coreParams.loadExuConfigs
330  val storeExuConfigs = coreParams.storeExuConfigs
331
332  val intExuConfigs = coreParams.intExuConfigs
333
334  val fpExuConfigs = coreParams.fpExuConfigs
335
336  val exuConfigs = coreParams.exuConfigs
337
338}
339