1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.{max, min} 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HSXLEN: Int = 64, 63 HasMExtension: Boolean = true, 64 HasCExtension: Boolean = true, 65 HasHExtension: Boolean = true, 66 HasDiv: Boolean = true, 67 HasICache: Boolean = true, 68 HasDCache: Boolean = true, 69 AddrBits: Int = 64, 70 VAddrBits: Int = 39, 71 GPAddrBits: Int = 41, 72 HasFPU: Boolean = true, 73 HasVPU: Boolean = true, 74 HasCustomCSRCacheOp: Boolean = true, 75 FetchWidth: Int = 8, 76 AsidLength: Int = 16, 77 VmidLength: Int = 14, 78 EnableBPU: Boolean = true, 79 EnableBPD: Boolean = true, 80 EnableRAS: Boolean = true, 81 EnableLB: Boolean = false, 82 EnableLoop: Boolean = true, 83 EnableSC: Boolean = true, 84 EnbaleTlbDebug: Boolean = false, 85 EnableClockGate: Boolean = true, 86 EnableJal: Boolean = false, 87 EnableFauFTB: Boolean = true, 88 UbtbGHRLength: Int = 4, 89 // HistoryLength: Int = 512, 90 EnableGHistDiff: Boolean = true, 91 EnableCommitGHistDiff: Boolean = true, 92 UbtbSize: Int = 256, 93 FtbSize: Int = 2048, 94 RasSize: Int = 16, 95 RasSpecSize: Int = 32, 96 RasCtrSize: Int = 3, 97 CacheLineSize: Int = 512, 98 FtbWays: Int = 4, 99 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 100 // Sets Hist Tag 101 Seq(( 4096, 8, 8), 102 ( 4096, 13, 8), 103 ( 4096, 32, 8), 104 ( 4096, 119, 8)), 105 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 106 // Sets Hist Tag 107 Seq(( 256, 4, 9), 108 ( 256, 8, 9), 109 ( 512, 13, 9), 110 ( 512, 16, 9), 111 ( 512, 32, 9)), 112 SCNRows: Int = 512, 113 SCNTables: Int = 4, 114 SCCtrBits: Int = 6, 115 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 116 numBr: Int = 2, 117 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 118 (resp_in: BranchPredictionResp, p: Parameters) => { 119 val ftb = Module(new FTB()(p)) 120 val uftb = Module(new FauFTB()(p)) 121 val tage = Module(new Tage_SC()(p)) 122 val ras = Module(new RAS()(p)) 123 val ittage = Module(new ITTage()(p)) 124 val preds = Seq(uftb, tage, ftb, ittage, ras) 125 preds.map(_.io := DontCare) 126 127 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 128 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 129 130 uftb.io.in.bits.resp_in(0) := resp_in 131 tage.io.in.bits.resp_in(0) := uftb.io.out 132 ftb.io.in.bits.resp_in(0) := tage.io.out 133 ittage.io.in.bits.resp_in(0) := ftb.io.out 134 ras.io.in.bits.resp_in(0) := ittage.io.out 135 136 (preds, ras.io.out) 137 }, 138 ICacheForceMetaECCError: Boolean = false, 139 ICacheForceDataECCError: Boolean = false, 140 IBufSize: Int = 48, 141 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 142 DecodeWidth: Int = 6, 143 RenameWidth: Int = 6, 144 CommitWidth: Int = 8, 145 RobCommitWidth: Int = 8, 146 RabCommitWidth: Int = 6, 147 MaxUopSize: Int = 65, 148 EnableRenameSnapshot: Boolean = true, 149 RenameSnapshotNum: Int = 4, 150 FtqSize: Int = 64, 151 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 152 IntLogicRegs: Int = 32, 153 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 154 VecLogicRegs: Int = 32 + 15, // 15: tmp 155 V0LogicRegs: Int = 1, // V0 156 VlLogicRegs: Int = 1, // Vl 157 V0_IDX: Int = 0, 158 Vl_IDX: Int = 0, 159 NRPhyRegs: Int = 192, 160 VirtualLoadQueueSize: Int = 72, 161 LoadQueueRARSize: Int = 72, 162 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 163 RollbackGroupSize: Int = 8, 164 LoadQueueReplaySize: Int = 72, 165 LoadUncacheBufferSize: Int = 20, 166 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 167 StoreQueueSize: Int = 64, 168 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 169 StoreQueueForwardWithMask: Boolean = true, 170 VlsQueueSize: Int = 8, 171 RobSize: Int = 160, 172 RabSize: Int = 256, 173 VTypeBufferSize: Int = 64, // used to reorder vtype 174 IssueQueueSize: Int = 24, 175 IssueQueueCompEntrySize: Int = 16, 176 dpParams: DispatchParameters = DispatchParameters( 177 IntDqSize = 16, 178 FpDqSize = 16, 179 LsDqSize = 18, 180 IntDqDeqWidth = 8, 181 FpDqDeqWidth = 6, 182 VecDqDeqWidth = 6, 183 LsDqDeqWidth = 6, 184 ), 185 intPreg: PregParams = IntPregParams( 186 numEntries = 224, 187 numRead = None, 188 numWrite = None, 189 ), 190 fpPreg: PregParams = FpPregParams( 191 numEntries = 192, 192 numRead = None, 193 numWrite = None, 194 ), 195 vfPreg: VfPregParams = VfPregParams( 196 numEntries = 128, 197 numRead = None, 198 numWrite = None, 199 ), 200 v0Preg: V0PregParams = V0PregParams( 201 numEntries = 22, 202 numRead = None, 203 numWrite = None, 204 ), 205 vlPreg: VlPregParams = VlPregParams( 206 numEntries = 32, 207 numRead = None, 208 numWrite = None, 209 ), 210 IntRegCacheSize: Int = 16, 211 MemRegCacheSize: Int = 12, 212 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 213 IfuRedirectNum: Int = 1, 214 LoadPipelineWidth: Int = 3, 215 StorePipelineWidth: Int = 2, 216 VecLoadPipelineWidth: Int = 2, 217 VecStorePipelineWidth: Int = 2, 218 VecMemSrcInWidth: Int = 2, 219 VecMemInstWbWidth: Int = 1, 220 VecMemDispatchWidth: Int = 1, 221 VecMemDispatchMaxNumber: Int = 16, 222 VecMemUnitStrideMaxFlowNum: Int = 2, 223 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 2, 2, 2, 2, 2), 224 StoreBufferSize: Int = 16, 225 StoreBufferThreshold: Int = 7, 226 EnsbufferWidth: Int = 2, 227 LoadDependencyWidth: Int = 2, 228 // ============ VLSU ============ 229 VlMergeBufferSize: Int = 16, 230 VsMergeBufferSize: Int = 16, 231 UopWritebackWidth: Int = 2, 232 VLUopWritebackWidth: Int = 2, 233 VSUopWritebackWidth: Int = 1, 234 VSegmentBufferSize: Int = 8, 235 // ============================== 236 UncacheBufferSize: Int = 4, 237 EnableLoadToLoadForward: Boolean = false, 238 EnableFastForward: Boolean = true, 239 EnableLdVioCheckAfterReset: Boolean = true, 240 EnableSoftPrefetchAfterReset: Boolean = true, 241 EnableCacheErrorAfterReset: Boolean = true, 242 EnableAccurateLoadError: Boolean = false, 243 EnableUncacheWriteOutstanding: Boolean = false, 244 EnableStorePrefetchAtIssue: Boolean = false, 245 EnableStorePrefetchAtCommit: Boolean = false, 246 EnableAtCommitMissTrigger: Boolean = true, 247 EnableStorePrefetchSMS: Boolean = false, 248 EnableStorePrefetchSPB: Boolean = false, 249 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 250 MMUVmidLen: Int = 14, 251 ReSelectLen: Int = 7, // load replay queue replay select counter len 252 iwpuParameters: WPUParameters = WPUParameters( 253 enWPU = false, 254 algoName = "mmru", 255 isICache = true, 256 ), 257 dwpuParameters: WPUParameters = WPUParameters( 258 enWPU = false, 259 algoName = "mmru", 260 enCfPred = false, 261 isICache = false, 262 ), 263 itlbParameters: TLBParameters = TLBParameters( 264 name = "itlb", 265 fetchi = true, 266 useDmode = false, 267 NWays = 48, 268 ), 269 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 270 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 271 ldtlbParameters: TLBParameters = TLBParameters( 272 name = "ldtlb", 273 NWays = 48, 274 outReplace = false, 275 partialStaticPMP = true, 276 outsideRecvFlush = true, 277 saveLevel = true, 278 lgMaxSize = 4 279 ), 280 sttlbParameters: TLBParameters = TLBParameters( 281 name = "sttlb", 282 NWays = 48, 283 outReplace = false, 284 partialStaticPMP = true, 285 outsideRecvFlush = true, 286 saveLevel = true, 287 lgMaxSize = 4 288 ), 289 hytlbParameters: TLBParameters = TLBParameters( 290 name = "hytlb", 291 NWays = 48, 292 outReplace = false, 293 partialStaticPMP = true, 294 outsideRecvFlush = true, 295 saveLevel = true, 296 lgMaxSize = 4 297 ), 298 pftlbParameters: TLBParameters = TLBParameters( 299 name = "pftlb", 300 NWays = 48, 301 outReplace = false, 302 partialStaticPMP = true, 303 outsideRecvFlush = true, 304 saveLevel = true, 305 lgMaxSize = 4 306 ), 307 l2ToL1tlbParameters: TLBParameters = TLBParameters( 308 name = "l2tlb", 309 NWays = 48, 310 outReplace = false, 311 partialStaticPMP = true, 312 outsideRecvFlush = true, 313 saveLevel = true 314 ), 315 refillBothTlb: Boolean = false, 316 btlbParameters: TLBParameters = TLBParameters( 317 name = "btlb", 318 NWays = 48, 319 ), 320 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 321 NumPerfCounters: Int = 16, 322 icacheParameters: ICacheParameters = ICacheParameters( 323 tagECC = Some("parity"), 324 dataECC = Some("parity"), 325 replacer = Some("setplru"), 326 ), 327 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 328 tagECC = Some("secded"), 329 dataECC = Some("secded"), 330 replacer = Some("setplru"), 331 nMissEntries = 16, 332 nProbeEntries = 8, 333 nReleaseEntries = 18, 334 nMaxPrefetchEntry = 6, 335 )), 336 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 337 name = "l2", 338 ways = 8, 339 sets = 1024, // default 512KB L2 340 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 341 coupledL2.prefetch.TPParameters()), 342 )), 343 L2NBanks: Int = 1, 344 usePTWRepeater: Boolean = false, 345 softTLB: Boolean = false, // dpi-c l1tlb debug only 346 softPTW: Boolean = false, // dpi-c l2tlb debug only 347 softPTWDelay: Int = 1 348){ 349 def vlWidth = log2Up(VLEN) + 1 350 351 /** 352 * the minimum element length of vector elements 353 */ 354 val minVecElen: Int = 8 355 356 /** 357 * the maximum number of elements in vector register 358 */ 359 val maxElemPerVreg: Int = VLEN / minVecElen 360 361 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 362 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 363 364 val RegCacheSize = IntRegCacheSize + MemRegCacheSize 365 val RegCacheIdxWidth = log2Up(RegCacheSize) 366 367 val intSchdParams = { 368 implicit val schdType: SchedulerType = IntScheduler() 369 SchdBlockParams(Seq( 370 IssueBlockParams(Seq( 371 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 372 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1))), true, 2), 373 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 374 IssueBlockParams(Seq( 375 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 376 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1))), true, 2), 377 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 378 IssueBlockParams(Seq( 379 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 380 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = 0, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 381 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 382 IssueBlockParams(Seq( 383 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 384 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 385 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 386 ), 387 numPregs = intPreg.numEntries, 388 numDeqOutside = 0, 389 schdType = schdType, 390 rfDataWidth = intPreg.dataCfg.dataWidth, 391 numUopIn = dpParams.IntDqDeqWidth, 392 ) 393 } 394 395 val fpSchdParams = { 396 implicit val schdType: SchedulerType = FpScheduler() 397 SchdBlockParams(Seq( 398 IssueBlockParams(Seq( 399 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 400 ), numEntries = 18, numEnq = 2, numComp = 16), 401 IssueBlockParams(Seq( 402 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 403 ), numEntries = 18, numEnq = 2, numComp = 16), 404 IssueBlockParams(Seq( 405 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 406 ), numEntries = 18, numEnq = 2, numComp = 16), 407 IssueBlockParams(Seq( 408 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 409 ), numEntries = 18, numEnq = 2, numComp = 16), 410 IssueBlockParams(Seq( 411 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 412 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 413 ), numEntries = 18, numEnq = 2, numComp = 16), 414 ), 415 numPregs = fpPreg.numEntries, 416 numDeqOutside = 0, 417 schdType = schdType, 418 rfDataWidth = fpPreg.dataCfg.dataWidth, 419 numUopIn = dpParams.VecDqDeqWidth, 420 ) 421 } 422 423 val vfSchdParams = { 424 implicit val schdType: SchedulerType = VfScheduler() 425 SchdBlockParams(Seq( 426 IssueBlockParams(Seq( 427 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 428 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = 1, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 429 ), numEntries = 16, numEnq = 2, numComp = 14), 430 IssueBlockParams(Seq( 431 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 432 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 433 ), numEntries = 16, numEnq = 2, numComp = 14), 434 IssueBlockParams(Seq( 435 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 436 ), numEntries = 10, numEnq = 2, numComp = 8), 437 ), 438 numPregs = vfPreg.numEntries, 439 numDeqOutside = 0, 440 schdType = schdType, 441 rfDataWidth = vfPreg.dataCfg.dataWidth, 442 numUopIn = dpParams.VecDqDeqWidth, 443 ) 444 } 445 446 val memSchdParams = { 447 implicit val schdType: SchedulerType = MemScheduler() 448 val rfDataWidth = 64 449 450 SchdBlockParams(Seq( 451 IssueBlockParams(Seq( 452 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))), 453 ), numEntries = 16, numEnq = 2, numComp = 14), 454 IssueBlockParams(Seq( 455 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))), 456 ), numEntries = 16, numEnq = 2, numComp = 14), 457 IssueBlockParams(Seq( 458 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(8, 0))), true, 2), 459 ), numEntries = 16, numEnq = 2, numComp = 14), 460 IssueBlockParams(Seq( 461 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(9, 0))), true, 2), 462 ), numEntries = 16, numEnq = 2, numComp = 14), 463 IssueBlockParams(Seq( 464 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(10, 0))), true, 2), 465 ), numEntries = 16, numEnq = 2, numComp = 14), 466 IssueBlockParams(Seq( 467 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 468 ), numEntries = 16, numEnq = 2, numComp = 14), 469 IssueBlockParams(Seq( 470 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 471 ), numEntries = 16, numEnq = 2, numComp = 14), 472 IssueBlockParams(Seq( 473 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(12, 0)))), 474 ), numEntries = 16, numEnq = 2, numComp = 14), 475 IssueBlockParams(Seq( 476 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(13, 0)))), 477 ), numEntries = 16, numEnq = 2, numComp = 14), 478 ), 479 numPregs = intPreg.numEntries max vfPreg.numEntries, 480 numDeqOutside = 0, 481 schdType = schdType, 482 rfDataWidth = rfDataWidth, 483 numUopIn = dpParams.LsDqDeqWidth, 484 ) 485 } 486 487 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 488 489 def iqWakeUpParams = { 490 Seq( 491 WakeUpConfig( 492 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 493 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 494 ), 495 // TODO: add load -> fp slow wakeup 496 WakeUpConfig( 497 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 498 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 499 ), 500 WakeUpConfig( 501 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 502 Seq("STD0", "STD1") 503 ), 504// WakeUpConfig( 505// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 506// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") 507// ), 508 ).flatten 509 } 510 511 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 512 513 val backendParams: BackendParams = backend.BackendParams( 514 Map( 515 IntScheduler() -> intSchdParams, 516 FpScheduler() -> fpSchdParams, 517 VfScheduler() -> vfSchdParams, 518 MemScheduler() -> memSchdParams, 519 ), 520 Seq( 521 intPreg, 522 fpPreg, 523 vfPreg, 524 v0Preg, 525 vlPreg, 526 fakeIntPreg 527 ), 528 iqWakeUpParams, 529 ) 530} 531 532case object DebugOptionsKey extends Field[DebugOptions] 533 534case class DebugOptions 535( 536 FPGAPlatform: Boolean = false, 537 ResetGen: Boolean = false, 538 EnableDifftest: Boolean = false, 539 AlwaysBasicDiff: Boolean = true, 540 EnableDebug: Boolean = false, 541 EnablePerfDebug: Boolean = true, 542 UseDRAMSim: Boolean = false, 543 EnableConstantin: Boolean = false, 544 EnableChiselDB: Boolean = false, 545 AlwaysBasicDB: Boolean = true, 546 EnableRollingDB: Boolean = false 547) 548 549trait HasXSParameter { 550 551 implicit val p: Parameters 552 553 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 554 final val PageOffsetWidth = 12 555 def NodeIDWidth = p(SoCParamsKey).NodeIDWidth // NodeID width among NoC 556 557 def coreParams = p(XSCoreParamsKey) 558 def env = p(DebugOptionsKey) 559 560 def XLEN = coreParams.XLEN 561 def VLEN = coreParams.VLEN 562 def ELEN = coreParams.ELEN 563 def HSXLEN = coreParams.HSXLEN 564 val minFLen = 32 565 val fLen = 64 566 def hartIdLen = p(MaxHartIdBits) 567 val xLen = XLEN 568 569 def HasMExtension = coreParams.HasMExtension 570 def HasCExtension = coreParams.HasCExtension 571 def HasHExtension = coreParams.HasHExtension 572 def HasDiv = coreParams.HasDiv 573 def HasIcache = coreParams.HasICache 574 def HasDcache = coreParams.HasDCache 575 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 576 def GPAddrBits = coreParams.GPAddrBits 577 def VAddrBits = { 578 if(HasHExtension){ 579 coreParams.GPAddrBits 580 }else{ 581 coreParams.VAddrBits 582 } 583 } // VAddrBits is Virtual Memory addr bits 584 585 def VAddrMaxBits = coreParams.VAddrBits max coreParams.GPAddrBits 586 587 def AsidLength = coreParams.AsidLength 588 def VmidLength = coreParams.VmidLength 589 def ReSelectLen = coreParams.ReSelectLen 590 def AddrBytes = AddrBits / 8 // unused 591 def DataBits = XLEN 592 def DataBytes = DataBits / 8 593 def VDataBytes = VLEN / 8 594 def HasFPU = coreParams.HasFPU 595 def HasVPU = coreParams.HasVPU 596 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 597 def FetchWidth = coreParams.FetchWidth 598 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 599 def EnableBPU = coreParams.EnableBPU 600 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 601 def EnableRAS = coreParams.EnableRAS 602 def EnableLB = coreParams.EnableLB 603 def EnableLoop = coreParams.EnableLoop 604 def EnableSC = coreParams.EnableSC 605 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 606 def HistoryLength = coreParams.HistoryLength 607 def EnableGHistDiff = coreParams.EnableGHistDiff 608 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 609 def EnableClockGate = coreParams.EnableClockGate 610 def UbtbGHRLength = coreParams.UbtbGHRLength 611 def UbtbSize = coreParams.UbtbSize 612 def EnableFauFTB = coreParams.EnableFauFTB 613 def FtbSize = coreParams.FtbSize 614 def FtbWays = coreParams.FtbWays 615 def RasSize = coreParams.RasSize 616 def RasSpecSize = coreParams.RasSpecSize 617 def RasCtrSize = coreParams.RasCtrSize 618 619 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 620 coreParams.branchPredictor(resp_in, p) 621 } 622 def numBr = coreParams.numBr 623 def TageTableInfos = coreParams.TageTableInfos 624 def TageBanks = coreParams.numBr 625 def SCNRows = coreParams.SCNRows 626 def SCCtrBits = coreParams.SCCtrBits 627 def SCHistLens = coreParams.SCHistLens 628 def SCNTables = coreParams.SCNTables 629 630 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 631 case ((n, cb), h) => (n, cb, h) 632 } 633 def ITTageTableInfos = coreParams.ITTageTableInfos 634 type FoldedHistoryInfo = Tuple2[Int, Int] 635 def foldedGHistInfos = 636 (TageTableInfos.map{ case (nRows, h, t) => 637 if (h > 0) 638 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 639 else 640 Set[FoldedHistoryInfo]() 641 }.reduce(_++_).toSet ++ 642 SCTableInfos.map{ case (nRows, _, h) => 643 if (h > 0) 644 Set((h, min(log2Ceil(nRows/TageBanks), h))) 645 else 646 Set[FoldedHistoryInfo]() 647 }.reduce(_++_).toSet ++ 648 ITTageTableInfos.map{ case (nRows, h, t) => 649 if (h > 0) 650 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 651 else 652 Set[FoldedHistoryInfo]() 653 }.reduce(_++_) ++ 654 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 655 ).toList 656 657 658 659 def CacheLineSize = coreParams.CacheLineSize 660 def CacheLineHalfWord = CacheLineSize / 16 661 def ExtHistoryLength = HistoryLength + 64 662 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 663 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 664 def IBufSize = coreParams.IBufSize 665 def IBufNBank = coreParams.IBufNBank 666 def backendParams: BackendParams = coreParams.backendParams 667 def DecodeWidth = coreParams.DecodeWidth 668 def RenameWidth = coreParams.RenameWidth 669 def CommitWidth = coreParams.CommitWidth 670 def RobCommitWidth = coreParams.RobCommitWidth 671 def RabCommitWidth = coreParams.RabCommitWidth 672 def MaxUopSize = coreParams.MaxUopSize 673 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 674 def RenameSnapshotNum = coreParams.RenameSnapshotNum 675 def FtqSize = coreParams.FtqSize 676 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 677 def IntLogicRegs = coreParams.IntLogicRegs 678 def FpLogicRegs = coreParams.FpLogicRegs 679 def VecLogicRegs = coreParams.VecLogicRegs 680 def V0LogicRegs = coreParams.V0LogicRegs 681 def VlLogicRegs = coreParams.VlLogicRegs 682 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 683 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 684 def V0_IDX = coreParams.V0_IDX 685 def Vl_IDX = coreParams.Vl_IDX 686 def IntPhyRegs = coreParams.intPreg.numEntries 687 def FpPhyRegs = coreParams.fpPreg.numEntries 688 def VfPhyRegs = coreParams.vfPreg.numEntries 689 def V0PhyRegs = coreParams.v0Preg.numEntries 690 def VlPhyRegs = coreParams.vlPreg.numEntries 691 def MaxPhyPregs = IntPhyRegs max VfPhyRegs 692 def PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(FpPhyRegs) max log2Up(VfPhyRegs) 693 def RobSize = coreParams.RobSize 694 def RabSize = coreParams.RabSize 695 def VTypeBufferSize = coreParams.VTypeBufferSize 696 def IntRegCacheSize = coreParams.IntRegCacheSize 697 def MemRegCacheSize = coreParams.MemRegCacheSize 698 def RegCacheSize = coreParams.RegCacheSize 699 def RegCacheIdxWidth = coreParams.RegCacheIdxWidth 700 /** 701 * the minimum element length of vector elements 702 */ 703 def minVecElen: Int = coreParams.minVecElen 704 705 /** 706 * the maximum number of elements in vector register 707 */ 708 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 709 710 def IntRefCounterWidth = log2Ceil(RobSize) 711 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 712 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 713 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 714 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 715 def LoadQueueRARSize = coreParams.LoadQueueRARSize 716 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 717 def RollbackGroupSize = coreParams.RollbackGroupSize 718 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 719 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 720 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 721 def StoreQueueSize = coreParams.StoreQueueSize 722 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 723 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 724 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 725 def VlsQueueSize = coreParams.VlsQueueSize 726 def dpParams = coreParams.dpParams 727 728 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 729 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 730 731 def NumRedirect = backendParams.numRedirect 732 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 733 def FtqRedirectAheadNum = NumRedirect 734 def IfuRedirectNum = coreParams.IfuRedirectNum 735 def LoadPipelineWidth = coreParams.LoadPipelineWidth 736 def StorePipelineWidth = coreParams.StorePipelineWidth 737 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 738 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 739 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 740 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 741 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 742 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 743 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 744 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 745 def StoreBufferSize = coreParams.StoreBufferSize 746 def StoreBufferThreshold = coreParams.StoreBufferThreshold 747 def EnsbufferWidth = coreParams.EnsbufferWidth 748 def LoadDependencyWidth = coreParams.LoadDependencyWidth 749 def VlMergeBufferSize = coreParams.VlMergeBufferSize 750 def VsMergeBufferSize = coreParams.VsMergeBufferSize 751 def UopWritebackWidth = coreParams.UopWritebackWidth 752 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 753 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 754 def VSegmentBufferSize = coreParams.VSegmentBufferSize 755 def UncacheBufferSize = coreParams.UncacheBufferSize 756 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 757 def EnableFastForward = coreParams.EnableFastForward 758 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 759 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 760 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 761 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 762 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 763 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 764 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 765 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 766 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 767 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 768 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 769 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 770 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 771 def asidLen = coreParams.MMUAsidLen 772 def vmidLen = coreParams.MMUVmidLen 773 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 774 def refillBothTlb = coreParams.refillBothTlb 775 def iwpuParam = coreParams.iwpuParameters 776 def dwpuParam = coreParams.dwpuParameters 777 def itlbParams = coreParams.itlbParameters 778 def ldtlbParams = coreParams.ldtlbParameters 779 def sttlbParams = coreParams.sttlbParameters 780 def hytlbParams = coreParams.hytlbParameters 781 def pftlbParams = coreParams.pftlbParameters 782 def l2ToL1Params = coreParams.l2ToL1tlbParameters 783 def btlbParams = coreParams.btlbParameters 784 def l2tlbParams = coreParams.l2tlbParameters 785 def NumPerfCounters = coreParams.NumPerfCounters 786 787 def instBytes = if (HasCExtension) 2 else 4 788 def instOffsetBits = log2Ceil(instBytes) 789 790 def icacheParameters = coreParams.icacheParameters 791 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 792 793 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 794 // for constrained LR/SC loop 795 def LRSCCycles = 64 796 // for lr storm 797 def LRSCBackOff = 8 798 799 // cache hierarchy configurations 800 def l1BusDataWidth = 256 801 802 // load violation predict 803 def ResetTimeMax2Pow = 20 //1078576 804 def ResetTimeMin2Pow = 10 //1024 805 // wait table parameters 806 def WaitTableSize = 1024 807 def MemPredPCWidth = log2Up(WaitTableSize) 808 def LWTUse2BitCounter = true 809 // store set parameters 810 def SSITSize = WaitTableSize 811 def LFSTSize = 32 812 def SSIDWidth = log2Up(LFSTSize) 813 def LFSTWidth = 4 814 def StoreSetEnable = true // LWT will be disabled if SS is enabled 815 def LFSTEnable = true 816 817 def PCntIncrStep: Int = 6 818 def numPCntHc: Int = 25 819 def numPCntPtw: Int = 19 820 821 def numCSRPCntFrontend = 8 822 def numCSRPCntCtrl = 8 823 def numCSRPCntLsu = 8 824 def numCSRPCntHc = 5 825 def printEventCoding = true 826 827 // Parameters for Sdtrig extension 828 protected def TriggerNum = 4 829 protected def TriggerChainMaxLength = 2 830} 831