1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.{DCacheParameters, L1plusCacheParameters} 25import xiangshan.cache.prefetch._ 26import huancun.{CacheParameters, HCCacheParameters} 27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, ITTage, Tage_SC} 28import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30 31case object XSCoreParamsKey extends Field[XSCoreParameters] 32 33case class XSCoreParameters 34( 35 HasPrefetch: Boolean = false, 36 HartId: Int = 0, 37 XLEN: Int = 64, 38 HasMExtension: Boolean = true, 39 HasCExtension: Boolean = true, 40 HasDiv: Boolean = true, 41 HasICache: Boolean = true, 42 HasDCache: Boolean = true, 43 AddrBits: Int = 64, 44 VAddrBits: Int = 39, 45 PAddrBits: Int = 40, 46 HasFPU: Boolean = true, 47 FetchWidth: Int = 8, 48 EnableBPU: Boolean = true, 49 EnableBPD: Boolean = true, 50 EnableRAS: Boolean = true, 51 EnableLB: Boolean = false, 52 EnableLoop: Boolean = true, 53 EnableSC: Boolean = true, 54 EnbaleTlbDebug: Boolean = false, 55 EnableJal: Boolean = false, 56 EnableUBTB: Boolean = true, 57 HistoryLength: Int = 64, 58 PathHistoryLength: Int = 16, 59 BtbSize: Int = 2048, 60 JbtacSize: Int = 1024, 61 JbtacBanks: Int = 8, 62 RasSize: Int = 32, 63 CacheLineSize: Int = 512, 64 UBtbWays: Int = 16, 65 BtbWays: Int = 2, 66 branchPredictor: Function3[BranchPredictionResp, Parameters, Boolean, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 67 ((resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) => { 68 // val loop = Module(new LoopPredictor) 69 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 70 // else Module(new Tage) } 71 // else { Module(new FakeTage) }) 72 val ftb = Module(new FTB()(p)) 73 val ubtb = Module(new MicroBTB()(p)) 74 val bim = Module(new BIM()(p)) 75 val tage = if (enableSC) { Module(new Tage_SC()(p)) } else { Module(new Tage()(p)) } 76 val ras = Module(new RAS()(p)) 77 val ittage = Module(new ITTage()(p)) 78 // val tage = Module(new Tage()(p)) 79 // val fake = Module(new FakePredictor()(p)) 80 81 // val preds = Seq(loop, tage, btb, ubtb, bim) 82 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 83 preds.map(_.io := DontCare) 84 85 // ubtb.io.resp_in(0) := resp_in 86 // bim.io.resp_in(0) := ubtb.io.resp 87 // btb.io.resp_in(0) := bim.io.resp 88 // tage.io.resp_in(0) := btb.io.resp 89 // loop.io.resp_in(0) := tage.io.resp 90 bim.io.in.bits.resp_in(0) := resp_in 91 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 92 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 93 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 94 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 95 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 96 97 (preds, ras.io.out.resp) 98 }), 99 100 101 EnableL1plusPrefetcher: Boolean = true, 102 IBufSize: Int = 48, 103 DecodeWidth: Int = 6, 104 RenameWidth: Int = 6, 105 CommitWidth: Int = 6, 106 BrqSize: Int = 32, 107 FtqSize: Int = 64, 108 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 109 IssQueSize: Int = 16, 110 NRPhyRegs: Int = 160, 111 NRIntReadPorts: Int = 14, 112 NRIntWritePorts: Int = 8, 113 NRFpReadPorts: Int = 14, 114 NRFpWritePorts: Int = 8, 115 LoadQueueSize: Int = 64, 116 StoreQueueSize: Int = 48, 117 RoqSize: Int = 192, 118 EnableIntMoveElim: Boolean = true, 119 IntRefCounterWidth: Int = 2, 120 dpParams: DispatchParameters = DispatchParameters( 121 IntDqSize = 16, 122 FpDqSize = 16, 123 LsDqSize = 16, 124 IntDqDeqWidth = 4, 125 FpDqDeqWidth = 4, 126 LsDqDeqWidth = 4 127 ), 128 exuParameters: ExuParameters = ExuParameters( 129 JmpCnt = 1, 130 AluCnt = 4, 131 MulCnt = 0, 132 MduCnt = 2, 133 FmacCnt = 4, 134 FmiscCnt = 2, 135 FmiscDivSqrtCnt = 0, 136 LduCnt = 2, 137 StuCnt = 2 138 ), 139 LoadPipelineWidth: Int = 2, 140 StorePipelineWidth: Int = 2, 141 StoreBufferSize: Int = 16, 142 StoreBufferThreshold: Int = 7, 143 EnableFastForward: Boolean = true, 144 RefillSize: Int = 512, 145 itlbParameters: TLBParameters = TLBParameters( 146 name = "itlb", 147 fetchi = true, 148 useDmode = false, 149 sameCycle = true, 150 normalNWays = 32, 151 normalReplacer = Some("plru"), 152 superNWays = 4, 153 superReplacer = Some("plru"), 154 shouldBlock = true 155 ), 156 ldtlbParameters: TLBParameters = TLBParameters( 157 name = "ldtlb", 158 normalNSets = 128, 159 normalNWays = 1, 160 normalAssociative = "sa", 161 normalReplacer = Some("setplru"), 162 superNWays = 8, 163 normalAsVictim = true, 164 outReplace = true 165 ), 166 sttlbParameters: TLBParameters = TLBParameters( 167 name = "sttlb", 168 normalNSets = 128, 169 normalNWays = 1, 170 normalAssociative = "sa", 171 normalReplacer = Some("setplru"), 172 superNWays = 8, 173 normalAsVictim = true, 174 outReplace = true 175 ), 176 refillBothTlb: Boolean = false, 177 btlbParameters: TLBParameters = TLBParameters( 178 name = "btlb", 179 normalNSets = 1, 180 normalNWays = 64, 181 superNWays = 4, 182 ), 183 useBTlb: Boolean = false, 184 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 185 NumPerfCounters: Int = 16, 186 icacheParameters: ICacheParameters = ICacheParameters( 187 tagECC = Some("parity"), 188 dataECC = Some("parity"), 189 replacer = Some("setplru"), 190 nMissEntries = 2 191 ), 192 l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters( 193 tagECC = Some("secded"), 194 dataECC = Some("secded"), 195 replacer = Some("setplru"), 196 nMissEntries = 8 197 ), 198 dcacheParameters: DCacheParameters = DCacheParameters( 199 tagECC = Some("secded"), 200 dataECC = Some("secded"), 201 replacer = Some("setplru"), 202 nMissEntries = 16, 203 nProbeEntries = 16, 204 nReleaseEntries = 16, 205 nStoreReplayEntries = 16 206 ), 207 L2CacheParams: HCCacheParameters = HCCacheParameters( 208 name = "l2", 209 level = 2, 210 ways = 8, 211 sets = 1024, // default 512KB L2 212 prefetch = Some(huancun.prefetch.BOPParameters()) 213 ), 214 usePTWRepeater: Boolean = false, 215 useFakePTW: Boolean = false, 216 useFakeDCache: Boolean = false, 217 useFakeL1plusCache: Boolean = false, 218 useFakeL2Cache: Boolean = false 219){ 220 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 221 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) 222 223 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 224 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) ++ 225 Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 226 227 val fpExuConfigs = 228 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 229 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 230 231 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 232} 233 234case object DebugOptionsKey extends Field[DebugOptions] 235 236case class DebugOptions 237( 238 FPGAPlatform: Boolean = true, 239 EnableDebug: Boolean = true, 240 EnablePerfDebug: Boolean = true, 241 UseDRAMSim: Boolean = false 242) 243 244trait HasXSParameter { 245 246 implicit val p: Parameters 247 248 val coreParams = p(XSCoreParamsKey) 249 val env = p(DebugOptionsKey) 250 251 val XLEN = coreParams.XLEN 252 val hardId = coreParams.HartId 253 val minFLen = 32 254 val fLen = 64 255 def xLen = XLEN 256 257 val HasMExtension = coreParams.HasMExtension 258 val HasCExtension = coreParams.HasCExtension 259 val HasDiv = coreParams.HasDiv 260 val HasIcache = coreParams.HasICache 261 val HasDcache = coreParams.HasDCache 262 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 263 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 264 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 265 val AddrBytes = AddrBits / 8 // unused 266 val DataBits = XLEN 267 val DataBytes = DataBits / 8 268 val HasFPU = coreParams.HasFPU 269 val FetchWidth = coreParams.FetchWidth 270 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 271 val EnableBPU = coreParams.EnableBPU 272 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 273 val EnableRAS = coreParams.EnableRAS 274 val EnableLB = coreParams.EnableLB 275 val EnableLoop = coreParams.EnableLoop 276 val EnableSC = coreParams.EnableSC 277 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 278 val HistoryLength = coreParams.HistoryLength 279 val PathHistoryLength = coreParams.PathHistoryLength 280 val BtbSize = coreParams.BtbSize 281 // val BtbWays = 4 282 val BtbBanks = PredictWidth 283 // val BtbSets = BtbSize / BtbWays 284 val JbtacSize = coreParams.JbtacSize 285 val JbtacBanks = coreParams.JbtacBanks 286 val RasSize = coreParams.RasSize 287 288 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) = { 289 coreParams.branchPredictor(resp_in, p, enableSC) 290 } 291 292 val CacheLineSize = coreParams.CacheLineSize 293 val CacheLineHalfWord = CacheLineSize / 16 294 val ExtHistoryLength = HistoryLength + 64 295 val UBtbWays = coreParams.UBtbWays 296 val BtbWays = coreParams.BtbWays 297 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 298 val IBufSize = coreParams.IBufSize 299 val DecodeWidth = coreParams.DecodeWidth 300 val RenameWidth = coreParams.RenameWidth 301 val CommitWidth = coreParams.CommitWidth 302 val BrqSize = coreParams.BrqSize 303 val FtqSize = coreParams.FtqSize 304 val IssQueSize = coreParams.IssQueSize 305 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 306 val BrTagWidth = log2Up(BrqSize) 307 val NRPhyRegs = coreParams.NRPhyRegs 308 val PhyRegIdxWidth = log2Up(NRPhyRegs) 309 val RoqSize = coreParams.RoqSize 310 val EnableIntMoveElim = coreParams.EnableIntMoveElim 311 val IntRefCounterWidth = coreParams.IntRefCounterWidth 312 val StdFreeListSize = NRPhyRegs - 32 313 // val MEFreeListSize = NRPhyRegs - { if (IntRefCounterWidth > 0 && IntRefCounterWidth < 5) (32 / Math.pow(2, IntRefCounterWidth)).toInt else 1 } 314 val MEFreeListSize = NRPhyRegs 315 val LoadQueueSize = coreParams.LoadQueueSize 316 val StoreQueueSize = coreParams.StoreQueueSize 317 val dpParams = coreParams.dpParams 318 val exuParameters = coreParams.exuParameters 319 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 320 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 321 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 322 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 323 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 324 val LoadPipelineWidth = coreParams.LoadPipelineWidth 325 val StorePipelineWidth = coreParams.StorePipelineWidth 326 val StoreBufferSize = coreParams.StoreBufferSize 327 val StoreBufferThreshold = coreParams.StoreBufferThreshold 328 val EnableFastForward = coreParams.EnableFastForward 329 val RefillSize = coreParams.RefillSize 330 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 331 val refillBothTlb = coreParams.refillBothTlb 332 val useBTlb = coreParams.useBTlb 333 val itlbParams = coreParams.itlbParameters 334 val ldtlbParams = coreParams.ldtlbParameters 335 val sttlbParams = coreParams.sttlbParameters 336 val btlbParams = coreParams.btlbParameters 337 val l2tlbParams = coreParams.l2tlbParameters 338 val NumPerfCounters = coreParams.NumPerfCounters 339 340 val instBytes = if (HasCExtension) 2 else 4 341 val instOffsetBits = log2Ceil(instBytes) 342 343 val icacheParameters = coreParams.icacheParameters 344 val l1plusCacheParameters = coreParams.l1plusCacheParameters 345 val dcacheParameters = coreParams.dcacheParameters 346 347 val LRSCCycles = 100 348 349 350 // cache hierarchy configurations 351 val l1BusDataWidth = 256 352 353 val useFakeDCache = coreParams.useFakeDCache 354 val useFakePTW = coreParams.useFakePTW 355 val useFakeL1plusCache = coreParams.useFakeL1plusCache 356 // L2 configurations 357 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 358 val L1BusWidth = 256 359 val L2BlockSize = 64 360 361 // L3 configurations 362 val L2BusWidth = 256 363 364 // icache prefetcher 365 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 366 enable = true, 367 _type = "stream", 368 streamParams = StreamPrefetchParameters( 369 streamCnt = 2, 370 streamSize = 4, 371 ageWidth = 4, 372 blockBytes = l1plusCacheParameters.blockBytes, 373 reallocStreamOnMissInstantly = true, 374 cacheName = "icache" 375 ) 376 ) 377 378 // load violation predict 379 val ResetTimeMax2Pow = 20 //1078576 380 val ResetTimeMin2Pow = 10 //1024 381 // wait table parameters 382 val WaitTableSize = 1024 383 val MemPredPCWidth = log2Up(WaitTableSize) 384 val LWTUse2BitCounter = true 385 // store set parameters 386 val SSITSize = WaitTableSize 387 val LFSTSize = 32 388 val SSIDWidth = log2Up(LFSTSize) 389 val LFSTWidth = 4 390 val StoreSetEnable = true // LWT will be disabled if SS is enabled 391 392 val loadExuConfigs = coreParams.loadExuConfigs 393 val storeExuConfigs = coreParams.storeExuConfigs 394 395 val intExuConfigs = coreParams.intExuConfigs 396 397 val fpExuConfigs = coreParams.fpExuConfigs 398 399 val exuConfigs = coreParams.exuConfigs 400 401} 402