1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import huancun.{CacheParameters, HCCacheParameters} 27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, ITTage, Tage_SC} 28import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30 31case object XSCoreParamsKey extends Field[XSCoreParameters] 32 33case class XSCoreParameters 34( 35 HasPrefetch: Boolean = false, 36 HartId: Int = 0, 37 XLEN: Int = 64, 38 HasMExtension: Boolean = true, 39 HasCExtension: Boolean = true, 40 HasDiv: Boolean = true, 41 HasICache: Boolean = true, 42 HasDCache: Boolean = true, 43 AddrBits: Int = 64, 44 VAddrBits: Int = 39, 45 PAddrBits: Int = 40, 46 HasFPU: Boolean = true, 47 HasCustomCSRCacheOp: Boolean = true, 48 FetchWidth: Int = 8, 49 AsidLength: Int = 16, 50 EnableBPU: Boolean = true, 51 EnableBPD: Boolean = true, 52 EnableRAS: Boolean = true, 53 EnableLB: Boolean = false, 54 EnableLoop: Boolean = true, 55 EnableSC: Boolean = true, 56 EnbaleTlbDebug: Boolean = false, 57 EnableJal: Boolean = false, 58 EnableUBTB: Boolean = true, 59 HistoryLength: Int = 64, 60 PathHistoryLength: Int = 16, 61 BtbSize: Int = 2048, 62 JbtacSize: Int = 1024, 63 JbtacBanks: Int = 8, 64 RasSize: Int = 32, 65 CacheLineSize: Int = 512, 66 UBtbWays: Int = 16, 67 BtbWays: Int = 2, 68 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 69 ((resp_in: BranchPredictionResp, p: Parameters) => { 70 // val loop = Module(new LoopPredictor) 71 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 72 // else Module(new Tage) } 73 // else { Module(new FakeTage) }) 74 val ftb = Module(new FTB()(p)) 75 val ubtb = Module(new MicroBTB()(p)) 76 val bim = Module(new BIM()(p)) 77 val tage = Module(new Tage_SC()(p)) 78 val ras = Module(new RAS()(p)) 79 val ittage = Module(new ITTage()(p)) 80 // val tage = Module(new Tage()(p)) 81 // val fake = Module(new FakePredictor()(p)) 82 83 // val preds = Seq(loop, tage, btb, ubtb, bim) 84 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 85 preds.map(_.io := DontCare) 86 87 // ubtb.io.resp_in(0) := resp_in 88 // bim.io.resp_in(0) := ubtb.io.resp 89 // btb.io.resp_in(0) := bim.io.resp 90 // tage.io.resp_in(0) := btb.io.resp 91 // loop.io.resp_in(0) := tage.io.resp 92 bim.io.in.bits.resp_in(0) := resp_in 93 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 94 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 95 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 96 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 97 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 98 99 (preds, ras.io.out.resp) 100 }), 101 IBufSize: Int = 48, 102 DecodeWidth: Int = 6, 103 RenameWidth: Int = 6, 104 CommitWidth: Int = 6, 105 FtqSize: Int = 64, 106 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 107 IssQueSize: Int = 16, 108 NRPhyRegs: Int = 192, 109 NRIntReadPorts: Int = 14, 110 NRIntWritePorts: Int = 8, 111 NRFpReadPorts: Int = 14, 112 NRFpWritePorts: Int = 8, 113 LoadQueueSize: Int = 80, 114 StoreQueueSize: Int = 64, 115 RobSize: Int = 256, 116 dpParams: DispatchParameters = DispatchParameters( 117 IntDqSize = 16, 118 FpDqSize = 16, 119 LsDqSize = 16, 120 IntDqDeqWidth = 4, 121 FpDqDeqWidth = 4, 122 LsDqDeqWidth = 4 123 ), 124 exuParameters: ExuParameters = ExuParameters( 125 JmpCnt = 1, 126 AluCnt = 4, 127 MulCnt = 0, 128 MduCnt = 2, 129 FmacCnt = 4, 130 FmiscCnt = 2, 131 FmiscDivSqrtCnt = 0, 132 LduCnt = 2, 133 StuCnt = 2 134 ), 135 LoadPipelineWidth: Int = 2, 136 StorePipelineWidth: Int = 2, 137 StoreBufferSize: Int = 16, 138 StoreBufferThreshold: Int = 7, 139 EnableFastForward: Boolean = true, 140 EnableLdVioCheckAfterReset: Boolean = false, 141 RefillSize: Int = 512, 142 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 143 itlbParameters: TLBParameters = TLBParameters( 144 name = "itlb", 145 fetchi = true, 146 useDmode = false, 147 sameCycle = true, 148 normalNWays = 32, 149 normalReplacer = Some("plru"), 150 superNWays = 4, 151 superReplacer = Some("plru"), 152 shouldBlock = true 153 ), 154 ldtlbParameters: TLBParameters = TLBParameters( 155 name = "ldtlb", 156 normalNSets = 128, 157 normalNWays = 1, 158 normalAssociative = "sa", 159 normalReplacer = Some("setplru"), 160 superNWays = 8, 161 normalAsVictim = true, 162 outReplace = true 163 ), 164 sttlbParameters: TLBParameters = TLBParameters( 165 name = "sttlb", 166 normalNSets = 128, 167 normalNWays = 1, 168 normalAssociative = "sa", 169 normalReplacer = Some("setplru"), 170 superNWays = 8, 171 normalAsVictim = true, 172 outReplace = true 173 ), 174 refillBothTlb: Boolean = false, 175 btlbParameters: TLBParameters = TLBParameters( 176 name = "btlb", 177 normalNSets = 1, 178 normalNWays = 64, 179 superNWays = 4, 180 ), 181 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 182 NumPMP: Int = 16, // 0 or 16 or 64 183 NumPMA: Int = 16, 184 NumPerfCounters: Int = 16, 185 icacheParameters: ICacheParameters = ICacheParameters( 186 tagECC = Some("parity"), 187 dataECC = Some("parity"), 188 replacer = Some("setplru"), 189 nMissEntries = 2 190 ), 191 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 192 tagECC = Some("secded"), 193 dataECC = Some("secded"), 194 replacer = Some("setplru"), 195 nMissEntries = 16, 196 nProbeEntries = 16, 197 nReleaseEntries = 32 198 )), 199 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 200 name = "l2", 201 level = 2, 202 ways = 8, 203 sets = 1024, // default 512KB L2 204 prefetch = Some(huancun.prefetch.BOPParameters()) 205 )), 206 L2NBanks: Int = 1, 207 usePTWRepeater: Boolean = false, 208 softPTW: Boolean = false // dpi-c debug only 209){ 210 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 211 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 212 213 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 214 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 215 216 val fpExuConfigs = 217 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 218 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 219 220 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 221} 222 223case object DebugOptionsKey extends Field[DebugOptions] 224 225case class DebugOptions 226( 227 FPGAPlatform: Boolean = true, 228 EnableDebug: Boolean = true, 229 EnablePerfDebug: Boolean = true, 230 UseDRAMSim: Boolean = false 231) 232 233trait HasXSParameter { 234 235 implicit val p: Parameters 236 237 val coreParams = p(XSCoreParamsKey) 238 val env = p(DebugOptionsKey) 239 240 val XLEN = coreParams.XLEN 241 val hardId = coreParams.HartId 242 val minFLen = 32 243 val fLen = 64 244 def xLen = XLEN 245 246 val HasMExtension = coreParams.HasMExtension 247 val HasCExtension = coreParams.HasCExtension 248 val HasDiv = coreParams.HasDiv 249 val HasIcache = coreParams.HasICache 250 val HasDcache = coreParams.HasDCache 251 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 252 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 253 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 254 val AsidLength = coreParams.AsidLength 255 val AddrBytes = AddrBits / 8 // unused 256 val DataBits = XLEN 257 val DataBytes = DataBits / 8 258 val HasFPU = coreParams.HasFPU 259 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 260 val FetchWidth = coreParams.FetchWidth 261 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 262 val EnableBPU = coreParams.EnableBPU 263 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 264 val EnableRAS = coreParams.EnableRAS 265 val EnableLB = coreParams.EnableLB 266 val EnableLoop = coreParams.EnableLoop 267 val EnableSC = coreParams.EnableSC 268 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 269 val HistoryLength = coreParams.HistoryLength 270 val PathHistoryLength = coreParams.PathHistoryLength 271 val BtbSize = coreParams.BtbSize 272 // val BtbWays = 4 273 val BtbBanks = PredictWidth 274 // val BtbSets = BtbSize / BtbWays 275 val JbtacSize = coreParams.JbtacSize 276 val JbtacBanks = coreParams.JbtacBanks 277 val RasSize = coreParams.RasSize 278 279 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 280 coreParams.branchPredictor(resp_in, p) 281 } 282 283 val CacheLineSize = coreParams.CacheLineSize 284 val CacheLineHalfWord = CacheLineSize / 16 285 val ExtHistoryLength = HistoryLength + 64 286 val UBtbWays = coreParams.UBtbWays 287 val BtbWays = coreParams.BtbWays 288 val IBufSize = coreParams.IBufSize 289 val DecodeWidth = coreParams.DecodeWidth 290 val RenameWidth = coreParams.RenameWidth 291 val CommitWidth = coreParams.CommitWidth 292 val FtqSize = coreParams.FtqSize 293 val IssQueSize = coreParams.IssQueSize 294 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 295 val NRPhyRegs = coreParams.NRPhyRegs 296 val PhyRegIdxWidth = log2Up(NRPhyRegs) 297 val RobSize = coreParams.RobSize 298 val IntRefCounterWidth = log2Ceil(RobSize) 299 val StdFreeListSize = NRPhyRegs - 32 300 val MEFreeListSize = NRPhyRegs 301 val LoadQueueSize = coreParams.LoadQueueSize 302 val StoreQueueSize = coreParams.StoreQueueSize 303 val dpParams = coreParams.dpParams 304 val exuParameters = coreParams.exuParameters 305 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 306 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 307 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 308 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 309 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 310 val LoadPipelineWidth = coreParams.LoadPipelineWidth 311 val StorePipelineWidth = coreParams.StorePipelineWidth 312 val StoreBufferSize = coreParams.StoreBufferSize 313 val StoreBufferThreshold = coreParams.StoreBufferThreshold 314 val EnableFastForward = coreParams.EnableFastForward 315 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 316 val RefillSize = coreParams.RefillSize 317 val asidLen = coreParams.MMUAsidLen 318 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 319 val refillBothTlb = coreParams.refillBothTlb 320 val itlbParams = coreParams.itlbParameters 321 val ldtlbParams = coreParams.ldtlbParameters 322 val sttlbParams = coreParams.sttlbParameters 323 val btlbParams = coreParams.btlbParameters 324 val l2tlbParams = coreParams.l2tlbParameters 325 val NumPMP = coreParams.NumPMP 326 val NumPMA = coreParams.NumPMA 327 val PlatformGrain: Int = log2Up(coreParams.RefillSize/8) // set PlatformGrain to avoid itlb, dtlb, ptw size conflict 328 val NumPerfCounters = coreParams.NumPerfCounters 329 330 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 331 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 332 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 333 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 334 335 val instBytes = if (HasCExtension) 2 else 4 336 val instOffsetBits = log2Ceil(instBytes) 337 338 val icacheParameters = coreParams.icacheParameters 339 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 340 341 val LRSCCycles = 100 342 343 // cache hierarchy configurations 344 val l1BusDataWidth = 256 345 346 // load violation predict 347 val ResetTimeMax2Pow = 20 //1078576 348 val ResetTimeMin2Pow = 10 //1024 349 // wait table parameters 350 val WaitTableSize = 1024 351 val MemPredPCWidth = log2Up(WaitTableSize) 352 val LWTUse2BitCounter = true 353 // store set parameters 354 val SSITSize = WaitTableSize 355 val LFSTSize = 32 356 val SSIDWidth = log2Up(LFSTSize) 357 val LFSTWidth = 4 358 val StoreSetEnable = true // LWT will be disabled if SS is enabled 359 360 val loadExuConfigs = coreParams.loadExuConfigs 361 val storeExuConfigs = coreParams.storeExuConfigs 362 363 val intExuConfigs = coreParams.intExuConfigs 364 365 val fpExuConfigs = coreParams.fpExuConfigs 366 367 val exuConfigs = coreParams.exuConfigs 368 369 val PCntIncrStep: Int = 6 370 val numPCntHc: Int = 25 371 val numPCntPtw: Int = 19 372 373 val numCSRPCntFrontend = 8 374 val numCSRPCntCtrl = 8 375 val numCSRPCntLsu = 8 376 val numCSRPCntHc = 5 377 val print_perfcounter = false 378} 379