1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.{DCacheParameters, L1plusCacheParameters} 25import xiangshan.cache.prefetch._ 26import huancun.{CacheParameters, HCCacheParameters} 27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, ITTage, Tage_SC} 28import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30 31case object XSCoreParamsKey extends Field[XSCoreParameters] 32 33case class XSCoreParameters 34( 35 HasPrefetch: Boolean = false, 36 HartId: Int = 0, 37 XLEN: Int = 64, 38 HasMExtension: Boolean = true, 39 HasCExtension: Boolean = true, 40 HasDiv: Boolean = true, 41 HasICache: Boolean = true, 42 HasDCache: Boolean = true, 43 AddrBits: Int = 64, 44 VAddrBits: Int = 39, 45 PAddrBits: Int = 40, 46 HasFPU: Boolean = true, 47 FetchWidth: Int = 8, 48 EnableBPU: Boolean = true, 49 EnableBPD: Boolean = true, 50 EnableRAS: Boolean = true, 51 EnableLB: Boolean = false, 52 EnableLoop: Boolean = true, 53 EnableSC: Boolean = true, 54 EnbaleTlbDebug: Boolean = false, 55 EnableJal: Boolean = false, 56 EnableUBTB: Boolean = true, 57 HistoryLength: Int = 64, 58 PathHistoryLength: Int = 16, 59 BtbSize: Int = 2048, 60 JbtacSize: Int = 1024, 61 JbtacBanks: Int = 8, 62 RasSize: Int = 32, 63 CacheLineSize: Int = 512, 64 UBtbWays: Int = 16, 65 BtbWays: Int = 2, 66 branchPredictor: Function3[BranchPredictionResp, Parameters, Boolean, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 67 ((resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) => { 68 // val loop = Module(new LoopPredictor) 69 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 70 // else Module(new Tage) } 71 // else { Module(new FakeTage) }) 72 val ftb = Module(new FTB()(p)) 73 val ubtb = Module(new MicroBTB()(p)) 74 val bim = Module(new BIM()(p)) 75 val tage = if (enableSC) { Module(new Tage_SC()(p)) } else { Module(new Tage()(p)) } 76 val ras = Module(new RAS()(p)) 77 val ittage = Module(new ITTage()(p)) 78 // val tage = Module(new Tage()(p)) 79 // val fake = Module(new FakePredictor()(p)) 80 81 // val preds = Seq(loop, tage, btb, ubtb, bim) 82 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 83 preds.map(_.io := DontCare) 84 85 // ubtb.io.resp_in(0) := resp_in 86 // bim.io.resp_in(0) := ubtb.io.resp 87 // btb.io.resp_in(0) := bim.io.resp 88 // tage.io.resp_in(0) := btb.io.resp 89 // loop.io.resp_in(0) := tage.io.resp 90 bim.io.in.bits.resp_in(0) := resp_in 91 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 92 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 93 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 94 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 95 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 96 97 (preds, ras.io.out.resp) 98 }), 99 100 101 EnableL1plusPrefetcher: Boolean = true, 102 IBufSize: Int = 48, 103 DecodeWidth: Int = 6, 104 RenameWidth: Int = 6, 105 CommitWidth: Int = 6, 106 BrqSize: Int = 32, 107 FtqSize: Int = 64, 108 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 109 IssQueSize: Int = 16, 110 NRPhyRegs: Int = 160, 111 NRIntReadPorts: Int = 14, 112 NRIntWritePorts: Int = 8, 113 NRFpReadPorts: Int = 14, 114 NRFpWritePorts: Int = 8, 115 LoadQueueSize: Int = 64, 116 StoreQueueSize: Int = 48, 117 RoqSize: Int = 192, 118 EnableIntMoveElim: Boolean = true, 119 IntRefCounterWidth: Int = 2, 120 dpParams: DispatchParameters = DispatchParameters( 121 IntDqSize = 16, 122 FpDqSize = 16, 123 LsDqSize = 16, 124 IntDqDeqWidth = 4, 125 FpDqDeqWidth = 4, 126 LsDqDeqWidth = 4 127 ), 128 exuParameters: ExuParameters = ExuParameters( 129 JmpCnt = 1, 130 AluCnt = 4, 131 MulCnt = 0, 132 MduCnt = 2, 133 FmacCnt = 4, 134 FmiscCnt = 2, 135 FmiscDivSqrtCnt = 0, 136 LduCnt = 2, 137 StuCnt = 2 138 ), 139 LoadPipelineWidth: Int = 2, 140 StorePipelineWidth: Int = 2, 141 StoreBufferSize: Int = 16, 142 StoreBufferThreshold: Int = 7, 143 EnableFastForward: Boolean = true, 144 RefillSize: Int = 512, 145 itlbParameters: TLBParameters = TLBParameters( 146 name = "itlb", 147 fetchi = true, 148 useDmode = false, 149 sameCycle = true, 150 normalNWays = 32, 151 normalReplacer = Some("plru"), 152 superNWays = 4, 153 superReplacer = Some("plru"), 154 shouldBlock = true 155 ), 156 ldtlbParameters: TLBParameters = TLBParameters( 157 name = "ldtlb", 158 normalNSets = 128, 159 normalNWays = 1, 160 normalAssociative = "sa", 161 normalReplacer = Some("setplru"), 162 superNWays = 8, 163 normalAsVictim = true, 164 outReplace = true 165 ), 166 sttlbParameters: TLBParameters = TLBParameters( 167 name = "sttlb", 168 normalNSets = 128, 169 normalNWays = 1, 170 normalAssociative = "sa", 171 normalReplacer = Some("setplru"), 172 superNWays = 8, 173 normalAsVictim = true, 174 outReplace = true 175 ), 176 btlbParameters: TLBParameters = TLBParameters( 177 name = "btlb", 178 normalNSets = 1, 179 normalNWays = 64, 180 superNWays = 4, 181 ), 182 useBTlb: Boolean = false, 183 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 184 NumPerfCounters: Int = 16, 185 icacheParameters: ICacheParameters = ICacheParameters( 186 tagECC = Some("parity"), 187 dataECC = Some("parity"), 188 replacer = Some("setplru"), 189 nMissEntries = 2 190 ), 191 l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters( 192 tagECC = Some("secded"), 193 dataECC = Some("secded"), 194 replacer = Some("setplru"), 195 nMissEntries = 8 196 ), 197 dcacheParameters: DCacheParameters = DCacheParameters( 198 tagECC = Some("secded"), 199 dataECC = Some("secded"), 200 replacer = Some("setplru"), 201 nMissEntries = 16, 202 nProbeEntries = 16, 203 nReleaseEntries = 16, 204 nStoreReplayEntries = 16 205 ), 206 L2CacheParams: HCCacheParameters = HCCacheParameters( 207 name = "l2", 208 level = 2, 209 ways = 8, 210 sets = 1024, // default 512KB L2 211 prefetch = Some(huancun.prefetch.BOPParameters()) 212 ), 213 usePTWRepeater: Boolean = false, 214 useFakePTW: Boolean = false, 215 useFakeDCache: Boolean = false, 216 useFakeL1plusCache: Boolean = false, 217 useFakeL2Cache: Boolean = false 218){ 219 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 220 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) 221 222 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 223 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) ++ 224 Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 225 226 val fpExuConfigs = 227 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 228 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 229 230 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 231} 232 233case object DebugOptionsKey extends Field[DebugOptions] 234 235case class DebugOptions 236( 237 FPGAPlatform: Boolean = true, 238 EnableDebug: Boolean = true, 239 EnablePerfDebug: Boolean = true, 240 UseDRAMSim: Boolean = false 241) 242 243trait HasXSParameter { 244 245 implicit val p: Parameters 246 247 val coreParams = p(XSCoreParamsKey) 248 val env = p(DebugOptionsKey) 249 250 val XLEN = coreParams.XLEN 251 val hardId = coreParams.HartId 252 val minFLen = 32 253 val fLen = 64 254 def xLen = XLEN 255 256 val HasMExtension = coreParams.HasMExtension 257 val HasCExtension = coreParams.HasCExtension 258 val HasDiv = coreParams.HasDiv 259 val HasIcache = coreParams.HasICache 260 val HasDcache = coreParams.HasDCache 261 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 262 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 263 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 264 val AddrBytes = AddrBits / 8 // unused 265 val DataBits = XLEN 266 val DataBytes = DataBits / 8 267 val HasFPU = coreParams.HasFPU 268 val FetchWidth = coreParams.FetchWidth 269 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 270 val EnableBPU = coreParams.EnableBPU 271 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 272 val EnableRAS = coreParams.EnableRAS 273 val EnableLB = coreParams.EnableLB 274 val EnableLoop = coreParams.EnableLoop 275 val EnableSC = coreParams.EnableSC 276 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 277 val HistoryLength = coreParams.HistoryLength 278 val PathHistoryLength = coreParams.PathHistoryLength 279 val BtbSize = coreParams.BtbSize 280 // val BtbWays = 4 281 val BtbBanks = PredictWidth 282 // val BtbSets = BtbSize / BtbWays 283 val JbtacSize = coreParams.JbtacSize 284 val JbtacBanks = coreParams.JbtacBanks 285 val RasSize = coreParams.RasSize 286 287 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) = { 288 coreParams.branchPredictor(resp_in, p, enableSC) 289 } 290 291 val CacheLineSize = coreParams.CacheLineSize 292 val CacheLineHalfWord = CacheLineSize / 16 293 val ExtHistoryLength = HistoryLength + 64 294 val UBtbWays = coreParams.UBtbWays 295 val BtbWays = coreParams.BtbWays 296 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 297 val IBufSize = coreParams.IBufSize 298 val DecodeWidth = coreParams.DecodeWidth 299 val RenameWidth = coreParams.RenameWidth 300 val CommitWidth = coreParams.CommitWidth 301 val BrqSize = coreParams.BrqSize 302 val FtqSize = coreParams.FtqSize 303 val IssQueSize = coreParams.IssQueSize 304 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 305 val BrTagWidth = log2Up(BrqSize) 306 val NRPhyRegs = coreParams.NRPhyRegs 307 val PhyRegIdxWidth = log2Up(NRPhyRegs) 308 val RoqSize = coreParams.RoqSize 309 val EnableIntMoveElim = coreParams.EnableIntMoveElim 310 val IntRefCounterWidth = coreParams.IntRefCounterWidth 311 val StdFreeListSize = NRPhyRegs - 32 312 // val MEFreeListSize = NRPhyRegs - { if (IntRefCounterWidth > 0 && IntRefCounterWidth < 5) (32 / Math.pow(2, IntRefCounterWidth)).toInt else 1 } 313 val MEFreeListSize = NRPhyRegs 314 val LoadQueueSize = coreParams.LoadQueueSize 315 val StoreQueueSize = coreParams.StoreQueueSize 316 val dpParams = coreParams.dpParams 317 val exuParameters = coreParams.exuParameters 318 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 319 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 320 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 321 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 322 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 323 val LoadPipelineWidth = coreParams.LoadPipelineWidth 324 val StorePipelineWidth = coreParams.StorePipelineWidth 325 val StoreBufferSize = coreParams.StoreBufferSize 326 val StoreBufferThreshold = coreParams.StoreBufferThreshold 327 val EnableFastForward = coreParams.EnableFastForward 328 val RefillSize = coreParams.RefillSize 329 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 330 val useBTlb = coreParams.useBTlb 331 val itlbParams = coreParams.itlbParameters 332 val ldtlbParams = coreParams.ldtlbParameters 333 val sttlbParams = coreParams.sttlbParameters 334 val btlbParams = coreParams.btlbParameters 335 val l2tlbParams = coreParams.l2tlbParameters 336 val NumPerfCounters = coreParams.NumPerfCounters 337 338 val instBytes = if (HasCExtension) 2 else 4 339 val instOffsetBits = log2Ceil(instBytes) 340 341 val icacheParameters = coreParams.icacheParameters 342 val l1plusCacheParameters = coreParams.l1plusCacheParameters 343 val dcacheParameters = coreParams.dcacheParameters 344 345 val LRSCCycles = 100 346 347 348 // cache hierarchy configurations 349 val l1BusDataWidth = 256 350 351 val useFakeDCache = coreParams.useFakeDCache 352 val useFakePTW = coreParams.useFakePTW 353 val useFakeL1plusCache = coreParams.useFakeL1plusCache 354 // L2 configurations 355 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 356 val L1BusWidth = 256 357 val L2BlockSize = 64 358 359 // L3 configurations 360 val L2BusWidth = 256 361 362 // icache prefetcher 363 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 364 enable = true, 365 _type = "stream", 366 streamParams = StreamPrefetchParameters( 367 streamCnt = 2, 368 streamSize = 4, 369 ageWidth = 4, 370 blockBytes = l1plusCacheParameters.blockBytes, 371 reallocStreamOnMissInstantly = true, 372 cacheName = "icache" 373 ) 374 ) 375 376 // load violation predict 377 val ResetTimeMax2Pow = 20 //1078576 378 val ResetTimeMin2Pow = 10 //1024 379 // wait table parameters 380 val WaitTableSize = 1024 381 val MemPredPCWidth = log2Up(WaitTableSize) 382 val LWTUse2BitCounter = true 383 // store set parameters 384 val SSITSize = WaitTableSize 385 val LFSTSize = 32 386 val SSIDWidth = log2Up(LFSTSize) 387 val LFSTWidth = 4 388 val StoreSetEnable = true // LWT will be disabled if SS is enabled 389 390 val loadExuConfigs = coreParams.loadExuConfigs 391 val storeExuConfigs = coreParams.storeExuConfigs 392 393 val intExuConfigs = coreParams.intExuConfigs 394 395 val fpExuConfigs = coreParams.fpExuConfigs 396 397 val exuConfigs = coreParams.exuConfigs 398 399} 400