1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import coupledL2.tl2chi._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.{max, min, pow} 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 PAddrBitsMax: Int = 56, // The bits of physical address from Sv39/Sv48/Sv57 virtual address translation. 72 VAddrBitsSv39: Int = 39, 73 GPAddrBitsSv39x4: Int = 41, 74 VAddrBitsSv48: Int = 48, 75 GPAddrBitsSv48x4: Int = 50, 76 HasFPU: Boolean = true, 77 HasVPU: Boolean = true, 78 HasCustomCSRCacheOp: Boolean = true, 79 FetchWidth: Int = 8, 80 AsidLength: Int = 16, 81 VmidLength: Int = 14, 82 EnableBPU: Boolean = true, 83 EnableBPD: Boolean = true, 84 EnableRAS: Boolean = true, 85 EnableLB: Boolean = false, 86 EnableLoop: Boolean = true, 87 EnableSC: Boolean = true, 88 EnbaleTlbDebug: Boolean = false, 89 EnableClockGate: Boolean = true, 90 EnableJal: Boolean = false, 91 EnableFauFTB: Boolean = true, 92 EnableSv48: Boolean = true, 93 UbtbGHRLength: Int = 4, 94 // HistoryLength: Int = 512, 95 EnableGHistDiff: Boolean = true, 96 EnableCommitGHistDiff: Boolean = true, 97 UbtbSize: Int = 256, 98 FtbSize: Int = 2048, 99 FtbWays: Int = 4, 100 FtbTagLength: Int = 20, 101 RasSize: Int = 16, 102 RasSpecSize: Int = 32, 103 RasCtrSize: Int = 3, 104 CacheLineSize: Int = 512, 105 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 106 // Sets Hist Tag 107 Seq(( 4096, 8, 8), 108 ( 4096, 13, 8), 109 ( 4096, 32, 8), 110 ( 4096, 119, 8)), 111 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 112 // Sets Hist Tag 113 Seq(( 256, 4, 9), 114 ( 256, 8, 9), 115 ( 512, 13, 9), 116 ( 512, 16, 9), 117 ( 512, 32, 9)), 118 SCNRows: Int = 512, 119 SCNTables: Int = 4, 120 SCCtrBits: Int = 6, 121 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 122 numBr: Int = 2, 123 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 124 (resp_in: BranchPredictionResp, p: Parameters) => { 125 val ftb = Module(new FTB()(p)) 126 val uftb = Module(new FauFTB()(p)) 127 val tage = Module(new Tage_SC()(p)) 128 val ras = Module(new RAS()(p)) 129 val ittage = Module(new ITTage()(p)) 130 val preds = Seq(uftb, tage, ftb, ittage, ras) 131 preds.map(_.io := DontCare) 132 133 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 134 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 135 136 uftb.io.in.bits.resp_in(0) := resp_in 137 tage.io.in.bits.resp_in(0) := uftb.io.out 138 ftb.io.in.bits.resp_in(0) := tage.io.out 139 ittage.io.in.bits.resp_in(0) := ftb.io.out 140 ras.io.in.bits.resp_in(0) := ittage.io.out 141 142 (preds, ras.io.out) 143 }, 144 ICacheForceMetaECCError: Boolean = false, 145 ICacheForceDataECCError: Boolean = false, 146 IBufSize: Int = 48, 147 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 148 DecodeWidth: Int = 6, 149 RenameWidth: Int = 6, 150 CommitWidth: Int = 8, 151 RobCommitWidth: Int = 8, 152 RabCommitWidth: Int = 6, 153 MaxUopSize: Int = 65, 154 EnableRenameSnapshot: Boolean = true, 155 RenameSnapshotNum: Int = 4, 156 FtqSize: Int = 64, 157 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 158 IntLogicRegs: Int = 32, 159 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 160 VecLogicRegs: Int = 32 + 15, // 15: tmp 161 V0LogicRegs: Int = 1, // V0 162 VlLogicRegs: Int = 1, // Vl 163 V0_IDX: Int = 0, 164 Vl_IDX: Int = 0, 165 NRPhyRegs: Int = 192, 166 VirtualLoadQueueSize: Int = 72, 167 LoadQueueRARSize: Int = 72, 168 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 169 RollbackGroupSize: Int = 8, 170 LoadQueueReplaySize: Int = 72, 171 LoadUncacheBufferSize: Int = 20, 172 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 173 StoreQueueSize: Int = 64, 174 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 175 StoreQueueForwardWithMask: Boolean = true, 176 VlsQueueSize: Int = 8, 177 RobSize: Int = 160, 178 RabSize: Int = 256, 179 VTypeBufferSize: Int = 64, // used to reorder vtype 180 IssueQueueSize: Int = 24, 181 IssueQueueCompEntrySize: Int = 16, 182 dpParams: DispatchParameters = DispatchParameters( 183 IntDqSize = 16, 184 FpDqSize = 16, 185 LsDqSize = 18, 186 IntDqDeqWidth = 8, 187 FpDqDeqWidth = 6, 188 VecDqDeqWidth = 6, 189 LsDqDeqWidth = 6, 190 ), 191 intPreg: PregParams = IntPregParams( 192 numEntries = 224, 193 numRead = None, 194 numWrite = None, 195 ), 196 fpPreg: PregParams = FpPregParams( 197 numEntries = 192, 198 numRead = None, 199 numWrite = None, 200 ), 201 vfPreg: VfPregParams = VfPregParams( 202 numEntries = 128, 203 numRead = None, 204 numWrite = None, 205 ), 206 v0Preg: V0PregParams = V0PregParams( 207 numEntries = 22, 208 numRead = None, 209 numWrite = None, 210 ), 211 vlPreg: VlPregParams = VlPregParams( 212 numEntries = 32, 213 numRead = None, 214 numWrite = None, 215 ), 216 IntRegCacheSize: Int = 16, 217 MemRegCacheSize: Int = 12, 218 intSchdVlWbPort: Int = 0, 219 vfSchdVlWbPort: Int = 1, 220 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 221 IfuRedirectNum: Int = 1, 222 LoadPipelineWidth: Int = 3, 223 StorePipelineWidth: Int = 2, 224 VecLoadPipelineWidth: Int = 2, 225 VecStorePipelineWidth: Int = 2, 226 VecMemSrcInWidth: Int = 2, 227 VecMemInstWbWidth: Int = 1, 228 VecMemDispatchWidth: Int = 1, 229 VecMemDispatchMaxNumber: Int = 16, 230 VecMemUnitStrideMaxFlowNum: Int = 2, 231 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 2, 2, 2, 2, 2), 232 StoreBufferSize: Int = 16, 233 StoreBufferThreshold: Int = 7, 234 EnsbufferWidth: Int = 2, 235 LoadDependencyWidth: Int = 2, 236 // ============ VLSU ============ 237 VlMergeBufferSize: Int = 16, 238 VsMergeBufferSize: Int = 16, 239 UopWritebackWidth: Int = 2, 240 VLUopWritebackWidth: Int = 2, 241 VSUopWritebackWidth: Int = 1, 242 VSegmentBufferSize: Int = 8, 243 VFOFBufferSize: Int = 8, 244 VLFOFWritebackWidth: Int = 1, 245 // ============================== 246 UncacheBufferSize: Int = 4, 247 EnableLoadToLoadForward: Boolean = false, 248 EnableFastForward: Boolean = true, 249 EnableLdVioCheckAfterReset: Boolean = true, 250 EnableSoftPrefetchAfterReset: Boolean = true, 251 EnableCacheErrorAfterReset: Boolean = true, 252 EnableAccurateLoadError: Boolean = false, 253 EnableUncacheWriteOutstanding: Boolean = false, 254 EnableHardwareStoreMisalign: Boolean = true, 255 EnableHardwareLoadMisalign: Boolean = true, 256 EnableStorePrefetchAtIssue: Boolean = false, 257 EnableStorePrefetchAtCommit: Boolean = false, 258 EnableAtCommitMissTrigger: Boolean = true, 259 EnableStorePrefetchSMS: Boolean = false, 260 EnableStorePrefetchSPB: Boolean = false, 261 HasCMO: Boolean = true, 262 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 263 MMUVmidLen: Int = 14, 264 ReSelectLen: Int = 7, // load replay queue replay select counter len 265 iwpuParameters: WPUParameters = WPUParameters( 266 enWPU = false, 267 algoName = "mmru", 268 isICache = true, 269 ), 270 dwpuParameters: WPUParameters = WPUParameters( 271 enWPU = false, 272 algoName = "mmru", 273 enCfPred = false, 274 isICache = false, 275 ), 276 itlbParameters: TLBParameters = TLBParameters( 277 name = "itlb", 278 fetchi = true, 279 useDmode = false, 280 NWays = 48, 281 ), 282 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 283 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 284 ldtlbParameters: TLBParameters = TLBParameters( 285 name = "ldtlb", 286 NWays = 48, 287 outReplace = false, 288 partialStaticPMP = true, 289 outsideRecvFlush = true, 290 saveLevel = false, 291 lgMaxSize = 4 292 ), 293 sttlbParameters: TLBParameters = TLBParameters( 294 name = "sttlb", 295 NWays = 48, 296 outReplace = false, 297 partialStaticPMP = true, 298 outsideRecvFlush = true, 299 saveLevel = false, 300 lgMaxSize = 4 301 ), 302 hytlbParameters: TLBParameters = TLBParameters( 303 name = "hytlb", 304 NWays = 48, 305 outReplace = false, 306 partialStaticPMP = true, 307 outsideRecvFlush = true, 308 saveLevel = false, 309 lgMaxSize = 4 310 ), 311 pftlbParameters: TLBParameters = TLBParameters( 312 name = "pftlb", 313 NWays = 48, 314 outReplace = false, 315 partialStaticPMP = true, 316 outsideRecvFlush = true, 317 saveLevel = false, 318 lgMaxSize = 4 319 ), 320 l2ToL1tlbParameters: TLBParameters = TLBParameters( 321 name = "l2tlb", 322 NWays = 48, 323 outReplace = false, 324 partialStaticPMP = true, 325 outsideRecvFlush = true, 326 saveLevel = false 327 ), 328 refillBothTlb: Boolean = false, 329 btlbParameters: TLBParameters = TLBParameters( 330 name = "btlb", 331 NWays = 48, 332 ), 333 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 334 NumPerfCounters: Int = 16, 335 icacheParameters: ICacheParameters = ICacheParameters( 336 tagECC = Some("parity"), 337 dataECC = Some("parity"), 338 replacer = Some("setplru"), 339 ), 340 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 341 tagECC = Some("secded"), 342 dataECC = Some("secded"), 343 replacer = Some("setplru"), 344 nMissEntries = 16, 345 nProbeEntries = 8, 346 nReleaseEntries = 18, 347 nMaxPrefetchEntry = 6, 348 enableTagEcc = true, 349 enableDataEcc = true 350 )), 351 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 352 name = "l2", 353 ways = 8, 354 sets = 1024, // default 512KB L2 355 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 356 coupledL2.prefetch.TPParameters()), 357 )), 358 L2NBanks: Int = 1, 359 usePTWRepeater: Boolean = false, 360 softTLB: Boolean = false, // dpi-c l1tlb debug only 361 softPTW: Boolean = false, // dpi-c l2tlb debug only 362 softPTWDelay: Int = 1 363){ 364 def ISABase = "rv64i" 365 def ISAExtensions = Seq( 366 // single letter extensions, in canonical order 367 "i", "m", "a", "f", "d", "c", /* "b", */ "v", "h", 368 // multi-letter extensions, sorted alphanumerically 369 "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", 370 "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", 371 "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", 372 "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", 373 "sv48", "svade", "svbare", "svinval", "svpbmt", "za64rs", "zba", "zbb", "zbc", "zbkb", "zbkc", 374 "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", 375 "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", 376 "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", 377 "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b" 378 ) 379 380 def vlWidth = log2Up(VLEN) + 1 381 382 /** 383 * the minimum element length of vector elements 384 */ 385 val minVecElen: Int = 8 386 387 /** 388 * the maximum number of elements in vector register 389 */ 390 val maxElemPerVreg: Int = VLEN / minVecElen 391 392 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 393 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 394 395 val RegCacheSize = IntRegCacheSize + MemRegCacheSize 396 val RegCacheIdxWidth = log2Up(RegCacheSize) 397 398 val intSchdParams = { 399 implicit val schdType: SchedulerType = IntScheduler() 400 SchdBlockParams(Seq( 401 IssueBlockParams(Seq( 402 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 403 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1))), true, 2), 404 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 405 IssueBlockParams(Seq( 406 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 407 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1))), true, 2), 408 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 409 IssueBlockParams(Seq( 410 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 411 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = intSchdVlWbPort, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 412 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 413 IssueBlockParams(Seq( 414 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 415 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 416 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 417 ), 418 numPregs = intPreg.numEntries, 419 numDeqOutside = 0, 420 schdType = schdType, 421 rfDataWidth = intPreg.dataCfg.dataWidth, 422 numUopIn = dpParams.IntDqDeqWidth, 423 ) 424 } 425 426 val fpSchdParams = { 427 implicit val schdType: SchedulerType = FpScheduler() 428 SchdBlockParams(Seq( 429 IssueBlockParams(Seq( 430 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 431 ), numEntries = 18, numEnq = 2, numComp = 16), 432 IssueBlockParams(Seq( 433 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 434 ), numEntries = 18, numEnq = 2, numComp = 16), 435 IssueBlockParams(Seq( 436 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 437 ), numEntries = 18, numEnq = 2, numComp = 16), 438 IssueBlockParams(Seq( 439 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 440 ), numEntries = 18, numEnq = 2, numComp = 16), 441 IssueBlockParams(Seq( 442 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 443 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 444 ), numEntries = 18, numEnq = 2, numComp = 16), 445 ), 446 numPregs = fpPreg.numEntries, 447 numDeqOutside = 0, 448 schdType = schdType, 449 rfDataWidth = fpPreg.dataCfg.dataWidth, 450 numUopIn = dpParams.FpDqDeqWidth, 451 ) 452 } 453 454 val vfSchdParams = { 455 implicit val schdType: SchedulerType = VfScheduler() 456 SchdBlockParams(Seq( 457 IssueBlockParams(Seq( 458 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 459 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = vfSchdVlWbPort, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 460 ), numEntries = 16, numEnq = 2, numComp = 14), 461 IssueBlockParams(Seq( 462 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 463 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 464 ), numEntries = 16, numEnq = 2, numComp = 14), 465 IssueBlockParams(Seq( 466 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 467 ), numEntries = 10, numEnq = 2, numComp = 8), 468 ), 469 numPregs = vfPreg.numEntries, 470 numDeqOutside = 0, 471 schdType = schdType, 472 rfDataWidth = vfPreg.dataCfg.dataWidth, 473 numUopIn = dpParams.VecDqDeqWidth, 474 ) 475 } 476 477 val memSchdParams = { 478 implicit val schdType: SchedulerType = MemScheduler() 479 val rfDataWidth = 64 480 481 SchdBlockParams(Seq( 482 IssueBlockParams(Seq( 483 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))), 484 ), numEntries = 16, numEnq = 1, numComp = 15), 485 IssueBlockParams(Seq( 486 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))), 487 ), numEntries = 16, numEnq = 1, numComp = 15), 488 IssueBlockParams(Seq( 489 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(8, 0))), true, 2), 490 ), numEntries = 16, numEnq = 1, numComp = 15), 491 IssueBlockParams(Seq( 492 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(9, 0))), true, 2), 493 ), numEntries = 16, numEnq = 1, numComp = 15), 494 IssueBlockParams(Seq( 495 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(10, 0))), true, 2), 496 ), numEntries = 16, numEnq = 1, numComp = 15), 497 IssueBlockParams(Seq( 498 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0), VlWB(port = 2, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 499 ), numEntries = 16, numEnq = 1, numComp = 15), 500 IssueBlockParams(Seq( 501 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0), VlWB(port = 3, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 502 ), numEntries = 16, numEnq = 1, numComp = 15), 503 IssueBlockParams(Seq( 504 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(12, 0)))), 505 ), numEntries = 16, numEnq = 1, numComp = 15), 506 IssueBlockParams(Seq( 507 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(13, 0)))), 508 ), numEntries = 16, numEnq = 1, numComp = 15), 509 ), 510 numPregs = intPreg.numEntries max vfPreg.numEntries, 511 numDeqOutside = 0, 512 schdType = schdType, 513 rfDataWidth = rfDataWidth, 514 numUopIn = dpParams.LsDqDeqWidth, 515 ) 516 } 517 518 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 519 520 def iqWakeUpParams = { 521 Seq( 522 WakeUpConfig( 523 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 524 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 525 ), 526 // TODO: add load -> fp slow wakeup 527 WakeUpConfig( 528 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 529 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 530 ), 531 WakeUpConfig( 532 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 533 Seq("STD0", "STD1") 534 ), 535// WakeUpConfig( 536// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 537// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") 538// ), 539 ).flatten 540 } 541 542 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 543 544 val backendParams: BackendParams = backend.BackendParams( 545 Map( 546 IntScheduler() -> intSchdParams, 547 FpScheduler() -> fpSchdParams, 548 VfScheduler() -> vfSchdParams, 549 MemScheduler() -> memSchdParams, 550 ), 551 Seq( 552 intPreg, 553 fpPreg, 554 vfPreg, 555 v0Preg, 556 vlPreg, 557 fakeIntPreg 558 ), 559 iqWakeUpParams, 560 ) 561 562 // Parameters for trace extension. 563 // Trace parameters is useful for XSTOP. 564 val TraceGroupNum = 3 // Width to Encoder 565} 566 567case object DebugOptionsKey extends Field[DebugOptions] 568 569case class DebugOptions 570( 571 FPGAPlatform: Boolean = false, 572 ResetGen: Boolean = false, 573 EnableDifftest: Boolean = false, 574 AlwaysBasicDiff: Boolean = true, 575 EnableDebug: Boolean = false, 576 EnablePerfDebug: Boolean = true, 577 UseDRAMSim: Boolean = false, 578 EnableConstantin: Boolean = false, 579 EnableChiselDB: Boolean = false, 580 AlwaysBasicDB: Boolean = true, 581 EnableRollingDB: Boolean = false 582) 583 584trait HasXSParameter { 585 586 implicit val p: Parameters 587 588 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 589 def PmemRanges = p(SoCParamsKey).PmemRanges 590 def PmemLowBounds = PmemRanges.unzip._1 591 def PmemHighBounds = PmemRanges.unzip._2 592 final val PageOffsetWidth = 12 593 def NodeIDWidth = p(SoCParamsKey).NodeIDWidthList(p(CHIIssue)) // NodeID width among NoC 594 595 def coreParams = p(XSCoreParamsKey) 596 def env = p(DebugOptionsKey) 597 598 def ISABase = coreParams.ISABase 599 def ISAExtensions = coreParams.ISAExtensions 600 def XLEN = coreParams.XLEN 601 def VLEN = coreParams.VLEN 602 def ELEN = coreParams.ELEN 603 def HSXLEN = coreParams.HSXLEN 604 val minFLen = 32 605 val fLen = 64 606 def hartIdLen = p(MaxHartIdBits) 607 val xLen = XLEN 608 609 def HasMExtension = coreParams.HasMExtension 610 def HasCExtension = coreParams.HasCExtension 611 def HasHExtension = coreParams.HasHExtension 612 def EnableSv48 = coreParams.EnableSv48 613 def HasDiv = coreParams.HasDiv 614 def HasIcache = coreParams.HasICache 615 def HasDcache = coreParams.HasDCache 616 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 617 def PAddrBitsMax = coreParams.PAddrBitsMax 618 def GPAddrBitsSv39x4 = coreParams.GPAddrBitsSv39x4 619 def GPAddrBitsSv48x4 = coreParams.GPAddrBitsSv48x4 620 def GPAddrBits = { 621 if (EnableSv48) 622 coreParams.GPAddrBitsSv48x4 623 else 624 coreParams.GPAddrBitsSv39x4 625 } 626 def VAddrBits = { 627 if (HasHExtension) { 628 if (EnableSv48) 629 coreParams.GPAddrBitsSv48x4 630 else 631 coreParams.GPAddrBitsSv39x4 632 } else { 633 if (EnableSv48) 634 coreParams.VAddrBitsSv48 635 else 636 coreParams.VAddrBitsSv39 637 } 638 } // VAddrBits is Virtual Memory addr bits 639 640 def VAddrMaxBits = { 641 if(EnableSv48) { 642 coreParams.VAddrBitsSv48 max coreParams.GPAddrBitsSv48x4 643 } else { 644 coreParams.VAddrBitsSv39 max coreParams.GPAddrBitsSv39x4 645 } 646 } 647 648 def AsidLength = coreParams.AsidLength 649 def VmidLength = coreParams.VmidLength 650 def ReSelectLen = coreParams.ReSelectLen 651 def AddrBytes = AddrBits / 8 // unused 652 def DataBits = XLEN 653 def DataBytes = DataBits / 8 654 def QuadWordBits = DataBits * 2 655 def QuadWordBytes = QuadWordBits / 8 656 def VDataBytes = VLEN / 8 657 def HasFPU = coreParams.HasFPU 658 def HasVPU = coreParams.HasVPU 659 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 660 def FetchWidth = coreParams.FetchWidth 661 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 662 def EnableBPU = coreParams.EnableBPU 663 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 664 def EnableRAS = coreParams.EnableRAS 665 def EnableLB = coreParams.EnableLB 666 def EnableLoop = coreParams.EnableLoop 667 def EnableSC = coreParams.EnableSC 668 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 669 def HistoryLength = coreParams.HistoryLength 670 def EnableGHistDiff = coreParams.EnableGHistDiff 671 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 672 def EnableClockGate = coreParams.EnableClockGate 673 def UbtbGHRLength = coreParams.UbtbGHRLength 674 def UbtbSize = coreParams.UbtbSize 675 def EnableFauFTB = coreParams.EnableFauFTB 676 def FtbSize = coreParams.FtbSize 677 def FtbWays = coreParams.FtbWays 678 def FtbTagLength = coreParams.FtbTagLength 679 def RasSize = coreParams.RasSize 680 def RasSpecSize = coreParams.RasSpecSize 681 def RasCtrSize = coreParams.RasCtrSize 682 683 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 684 coreParams.branchPredictor(resp_in, p) 685 } 686 def numBr = coreParams.numBr 687 def TageTableInfos = coreParams.TageTableInfos 688 def TageBanks = coreParams.numBr 689 def SCNRows = coreParams.SCNRows 690 def SCCtrBits = coreParams.SCCtrBits 691 def SCHistLens = coreParams.SCHistLens 692 def SCNTables = coreParams.SCNTables 693 694 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 695 case ((n, cb), h) => (n, cb, h) 696 } 697 def ITTageTableInfos = coreParams.ITTageTableInfos 698 type FoldedHistoryInfo = Tuple2[Int, Int] 699 def foldedGHistInfos = 700 (TageTableInfos.map{ case (nRows, h, t) => 701 if (h > 0) 702 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 703 else 704 Set[FoldedHistoryInfo]() 705 }.reduce(_++_).toSet ++ 706 SCTableInfos.map{ case (nRows, _, h) => 707 if (h > 0) 708 Set((h, min(log2Ceil(nRows/TageBanks), h))) 709 else 710 Set[FoldedHistoryInfo]() 711 }.reduce(_++_).toSet ++ 712 ITTageTableInfos.map{ case (nRows, h, t) => 713 if (h > 0) 714 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 715 else 716 Set[FoldedHistoryInfo]() 717 }.reduce(_++_) ++ 718 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 719 ).toList 720 721 722 723 def CacheLineSize = coreParams.CacheLineSize 724 def CacheLineHalfWord = CacheLineSize / 16 725 def ExtHistoryLength = HistoryLength + 64 726 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 727 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 728 def IBufSize = coreParams.IBufSize 729 def IBufNBank = coreParams.IBufNBank 730 def backendParams: BackendParams = coreParams.backendParams 731 def DecodeWidth = coreParams.DecodeWidth 732 def RenameWidth = coreParams.RenameWidth 733 def CommitWidth = coreParams.CommitWidth 734 def RobCommitWidth = coreParams.RobCommitWidth 735 def RabCommitWidth = coreParams.RabCommitWidth 736 def MaxUopSize = coreParams.MaxUopSize 737 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 738 def RenameSnapshotNum = coreParams.RenameSnapshotNum 739 def FtqSize = coreParams.FtqSize 740 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 741 def IntLogicRegs = coreParams.IntLogicRegs 742 def FpLogicRegs = coreParams.FpLogicRegs 743 def VecLogicRegs = coreParams.VecLogicRegs 744 def V0LogicRegs = coreParams.V0LogicRegs 745 def VlLogicRegs = coreParams.VlLogicRegs 746 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 747 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 748 def V0_IDX = coreParams.V0_IDX 749 def Vl_IDX = coreParams.Vl_IDX 750 def IntPhyRegs = coreParams.intPreg.numEntries 751 def FpPhyRegs = coreParams.fpPreg.numEntries 752 def VfPhyRegs = coreParams.vfPreg.numEntries 753 def V0PhyRegs = coreParams.v0Preg.numEntries 754 def VlPhyRegs = coreParams.vlPreg.numEntries 755 def MaxPhyRegs = Seq(IntPhyRegs, FpPhyRegs, VfPhyRegs, V0PhyRegs, VlPhyRegs).max 756 def IntPhyRegIdxWidth = log2Up(IntPhyRegs) 757 def FpPhyRegIdxWidth = log2Up(FpPhyRegs) 758 def VfPhyRegIdxWidth = log2Up(VfPhyRegs) 759 def V0PhyRegIdxWidth = log2Up(V0PhyRegs) 760 def VlPhyRegIdxWidth = log2Up(VlPhyRegs) 761 def PhyRegIdxWidth = Seq(IntPhyRegIdxWidth, FpPhyRegIdxWidth, VfPhyRegIdxWidth, V0PhyRegIdxWidth, VlPhyRegIdxWidth).max 762 def RobSize = coreParams.RobSize 763 def RabSize = coreParams.RabSize 764 def VTypeBufferSize = coreParams.VTypeBufferSize 765 def IntRegCacheSize = coreParams.IntRegCacheSize 766 def MemRegCacheSize = coreParams.MemRegCacheSize 767 def RegCacheSize = coreParams.RegCacheSize 768 def RegCacheIdxWidth = coreParams.RegCacheIdxWidth 769 /** 770 * the minimum element length of vector elements 771 */ 772 def minVecElen: Int = coreParams.minVecElen 773 774 /** 775 * the maximum number of elements in vector register 776 */ 777 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 778 779 def IntRefCounterWidth = log2Ceil(RobSize) 780 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 781 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 782 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 783 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 784 def LoadQueueRARSize = coreParams.LoadQueueRARSize 785 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 786 def RollbackGroupSize = coreParams.RollbackGroupSize 787 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 788 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 789 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 790 def StoreQueueSize = coreParams.StoreQueueSize 791 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 792 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 793 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 794 def VlsQueueSize = coreParams.VlsQueueSize 795 def dpParams = coreParams.dpParams 796 797 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 798 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 799 800 def NumRedirect = backendParams.numRedirect 801 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 802 def FtqRedirectAheadNum = NumRedirect 803 def IfuRedirectNum = coreParams.IfuRedirectNum 804 def LoadPipelineWidth = coreParams.LoadPipelineWidth 805 def StorePipelineWidth = coreParams.StorePipelineWidth 806 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 807 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 808 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 809 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 810 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 811 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 812 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 813 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 814 def StoreBufferSize = coreParams.StoreBufferSize 815 def StoreBufferThreshold = coreParams.StoreBufferThreshold 816 def EnsbufferWidth = coreParams.EnsbufferWidth 817 def LoadDependencyWidth = coreParams.LoadDependencyWidth 818 def VlMergeBufferSize = coreParams.VlMergeBufferSize 819 def VsMergeBufferSize = coreParams.VsMergeBufferSize 820 def UopWritebackWidth = coreParams.UopWritebackWidth 821 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 822 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 823 def VSegmentBufferSize = coreParams.VSegmentBufferSize 824 def VFOFBufferSize = coreParams.VFOFBufferSize 825 def UncacheBufferSize = coreParams.UncacheBufferSize 826 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 827 def EnableFastForward = coreParams.EnableFastForward 828 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 829 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 830 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 831 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 832 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 833 def EnableHardwareStoreMisalign = coreParams.EnableHardwareStoreMisalign 834 def EnableHardwareLoadMisalign = coreParams.EnableHardwareLoadMisalign 835 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 836 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 837 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 838 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 839 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 840 def HasCMO = coreParams.HasCMO && p(EnableCHI) 841 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 842 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 843 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 844 def asidLen = coreParams.MMUAsidLen 845 def vmidLen = coreParams.MMUVmidLen 846 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 847 def refillBothTlb = coreParams.refillBothTlb 848 def iwpuParam = coreParams.iwpuParameters 849 def dwpuParam = coreParams.dwpuParameters 850 def itlbParams = coreParams.itlbParameters 851 def ldtlbParams = coreParams.ldtlbParameters 852 def sttlbParams = coreParams.sttlbParameters 853 def hytlbParams = coreParams.hytlbParameters 854 def pftlbParams = coreParams.pftlbParameters 855 def l2ToL1Params = coreParams.l2ToL1tlbParameters 856 def btlbParams = coreParams.btlbParameters 857 def l2tlbParams = coreParams.l2tlbParameters 858 def NumPerfCounters = coreParams.NumPerfCounters 859 860 def instBytes = if (HasCExtension) 2 else 4 861 def instOffsetBits = log2Ceil(instBytes) 862 863 def icacheParameters = coreParams.icacheParameters 864 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 865 866 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 867 // for constrained LR/SC loop 868 def LRSCCycles = 64 869 // for lr storm 870 def LRSCBackOff = 8 871 872 // cache hierarchy configurations 873 def l1BusDataWidth = 256 874 875 // load violation predict 876 def ResetTimeMax2Pow = 20 //1078576 877 def ResetTimeMin2Pow = 10 //1024 878 // wait table parameters 879 def WaitTableSize = 1024 880 def MemPredPCWidth = log2Up(WaitTableSize) 881 def LWTUse2BitCounter = true 882 // store set parameters 883 def SSITSize = WaitTableSize 884 def LFSTSize = 32 885 def SSIDWidth = log2Up(LFSTSize) 886 def LFSTWidth = 4 887 def StoreSetEnable = true // LWT will be disabled if SS is enabled 888 def LFSTEnable = true 889 890 def PCntIncrStep: Int = 6 891 def numPCntHc: Int = 12 892 def numPCntPtw: Int = 19 893 894 def numCSRPCntFrontend = 8 895 def numCSRPCntCtrl = 8 896 def numCSRPCntLsu = 8 897 def numCSRPCntHc = 5 898 def printEventCoding = true 899 def printCriticalError = false 900 def maxCommitStuck = pow(2, 21).toInt 901 902 // Vector load exception 903 def maxMergeNumPerCycle = 4 904 905 // Parameters for Sdtrig extension 906 protected def TriggerNum = 4 907 protected def TriggerChainMaxLength = 2 908 909 // Parameters for Trace extension 910 def TraceGroupNum = coreParams.TraceGroupNum 911} 912