1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import xiangshan.cache.wpu.WPUParameters 34import coupledL2._ 35import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 36 37import scala.math.min 38 39case object XSTileKey extends Field[Seq[XSCoreParameters]] 40 41case object XSCoreParamsKey extends Field[XSCoreParameters] 42 43case class XSCoreParameters 44( 45 HasPrefetch: Boolean = false, 46 HartId: Int = 0, 47 XLEN: Int = 64, 48 VLEN: Int = 128, 49 HasMExtension: Boolean = true, 50 HasCExtension: Boolean = true, 51 HasDiv: Boolean = true, 52 HasICache: Boolean = true, 53 HasDCache: Boolean = true, 54 AddrBits: Int = 64, 55 VAddrBits: Int = 39, 56 HasFPU: Boolean = true, 57 HasCustomCSRCacheOp: Boolean = true, 58 FetchWidth: Int = 8, 59 AsidLength: Int = 16, 60 EnableBPU: Boolean = true, 61 EnableBPD: Boolean = true, 62 EnableRAS: Boolean = true, 63 EnableLB: Boolean = false, 64 EnableLoop: Boolean = true, 65 EnableSC: Boolean = true, 66 EnbaleTlbDebug: Boolean = false, 67 EnableJal: Boolean = false, 68 EnableFauFTB: Boolean = true, 69 UbtbGHRLength: Int = 4, 70 // HistoryLength: Int = 512, 71 EnableGHistDiff: Boolean = true, 72 EnableCommitGHistDiff: Boolean = true, 73 UbtbSize: Int = 256, 74 FtbSize: Int = 2048, 75 RasSize: Int = 16, 76 RasSpecSize: Int = 32, 77 RasCtrSize: Int = 8, 78 CacheLineSize: Int = 512, 79 FtbWays: Int = 4, 80 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 81 // Sets Hist Tag 82 // Seq(( 2048, 2, 8), 83 // ( 2048, 9, 8), 84 // ( 2048, 13, 8), 85 // ( 2048, 20, 8), 86 // ( 2048, 26, 8), 87 // ( 2048, 44, 8), 88 // ( 2048, 73, 8), 89 // ( 2048, 256, 8)), 90 Seq(( 4096, 8, 8), 91 ( 4096, 13, 8), 92 ( 4096, 32, 8), 93 ( 4096, 119, 8)), 94 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 95 // Sets Hist Tag 96 Seq(( 256, 4, 9), 97 ( 256, 8, 9), 98 ( 512, 13, 9), 99 ( 512, 16, 9), 100 ( 512, 32, 9)), 101 SCNRows: Int = 512, 102 SCNTables: Int = 4, 103 SCCtrBits: Int = 6, 104 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 105 numBr: Int = 2, 106 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 107 ((resp_in: BranchPredictionResp, p: Parameters) => { 108 val ftb = Module(new FTB()(p)) 109 val ubtb =Module(new FauFTB()(p)) 110 // val bim = Module(new BIM()(p)) 111 val tage = Module(new Tage_SC()(p)) 112 val ras = Module(new RAS()(p)) 113 val ittage = Module(new ITTage()(p)) 114 val preds = Seq(ubtb, tage, ftb, ittage, ras) 115 preds.map(_.io := DontCare) 116 117 // ubtb.io.resp_in(0) := resp_in 118 // bim.io.resp_in(0) := ubtb.io.resp 119 // btb.io.resp_in(0) := bim.io.resp 120 // tage.io.resp_in(0) := btb.io.resp 121 // loop.io.resp_in(0) := tage.io.resp 122 ubtb.io.in.bits.resp_in(0) := resp_in 123 tage.io.in.bits.resp_in(0) := ubtb.io.out 124 ftb.io.in.bits.resp_in(0) := tage.io.out 125 ittage.io.in.bits.resp_in(0) := ftb.io.out 126 ras.io.in.bits.resp_in(0) := ittage.io.out 127 128 (preds, ras.io.out) 129 }), 130 ICacheECCForceError: Boolean = false, 131 IBufSize: Int = 48, 132 DecodeWidth: Int = 6, 133 RenameWidth: Int = 6, 134 CommitWidth: Int = 6, 135 EnableRenameSnapshot: Boolean = true, 136 RenameSnapshotNum: Int = 4, 137 FtqSize: Int = 64, 138 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 139 IssQueSize: Int = 16, 140 NRPhyRegs: Int = 192, 141 VirtualLoadQueueSize: Int = 80, 142 LoadQueueRARSize: Int = 80, 143 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 144 RollbackGroupSize: Int = 8, 145 LoadQueueReplaySize: Int = 72, 146 LoadUncacheBufferSize: Int = 20, 147 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 148 StoreQueueSize: Int = 64, 149 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 150 StoreQueueForwardWithMask: Boolean = true, 151 VlsQueueSize: Int = 8, 152 RobSize: Int = 256, 153 dpParams: DispatchParameters = DispatchParameters( 154 IntDqSize = 16, 155 FpDqSize = 16, 156 LsDqSize = 16, 157 IntDqDeqWidth = 4, 158 FpDqDeqWidth = 4, 159 LsDqDeqWidth = 4 160 ), 161 exuParameters: ExuParameters = ExuParameters( 162 JmpCnt = 1, 163 AluCnt = 4, 164 MulCnt = 0, 165 MduCnt = 2, 166 FmacCnt = 4, 167 FmiscCnt = 2, 168 FmiscDivSqrtCnt = 0, 169 LduCnt = 2, 170 StuCnt = 2 171 ), 172 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 173 LoadPipelineWidth: Int = 2, 174 StorePipelineWidth: Int = 2, 175 VecMemSrcInWidth: Int = 2, 176 VecMemInstWbWidth: Int = 1, 177 VecMemDispatchWidth: Int = 1, 178 StoreBufferSize: Int = 16, 179 StoreBufferThreshold: Int = 7, 180 EnsbufferWidth: Int = 2, 181 UncacheBufferSize: Int = 4, 182 EnableLoadToLoadForward: Boolean = true, 183 EnableFastForward: Boolean = true, 184 EnableLdVioCheckAfterReset: Boolean = true, 185 EnableSoftPrefetchAfterReset: Boolean = true, 186 EnableCacheErrorAfterReset: Boolean = true, 187 EnableAccurateLoadError: Boolean = true, 188 EnableUncacheWriteOutstanding: Boolean = false, 189 EnableStorePrefetchAtIssue: Boolean = false, 190 EnableStorePrefetchAtCommit: Boolean = false, 191 EnableAtCommitMissTrigger: Boolean = true, 192 EnableStorePrefetchSMS: Boolean = false, 193 EnableStorePrefetchSPB: Boolean = false, 194 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 195 ReSelectLen: Int = 7, // load replay queue replay select counter len 196 iwpuParameters: WPUParameters = WPUParameters( 197 enWPU = false, 198 algoName = "mmru", 199 isICache = true, 200 ), 201 dwpuParameters: WPUParameters = WPUParameters( 202 enWPU = false, 203 algoName = "mmru", 204 enCfPred = false, 205 isICache = false, 206 ), 207 itlbParameters: TLBParameters = TLBParameters( 208 name = "itlb", 209 fetchi = true, 210 useDmode = false, 211 NWays = 48, 212 ), 213 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 214 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 215 ldtlbParameters: TLBParameters = TLBParameters( 216 name = "ldtlb", 217 NWays = 48, 218 outReplace = false, 219 partialStaticPMP = true, 220 outsideRecvFlush = true, 221 saveLevel = true 222 ), 223 sttlbParameters: TLBParameters = TLBParameters( 224 name = "sttlb", 225 NWays = 48, 226 outReplace = false, 227 partialStaticPMP = true, 228 outsideRecvFlush = true, 229 saveLevel = true 230 ), 231 pftlbParameters: TLBParameters = TLBParameters( 232 name = "pftlb", 233 NWays = 48, 234 outReplace = false, 235 partialStaticPMP = true, 236 outsideRecvFlush = true, 237 saveLevel = true 238 ), 239 refillBothTlb: Boolean = false, 240 btlbParameters: TLBParameters = TLBParameters( 241 name = "btlb", 242 NWays = 48, 243 ), 244 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 245 NumPerfCounters: Int = 16, 246 icacheParameters: ICacheParameters = ICacheParameters( 247 tagECC = Some("parity"), 248 dataECC = Some("parity"), 249 replacer = Some("setplru"), 250 nMissEntries = 2, 251 nProbeEntries = 2, 252 nPrefetchEntries = 12, 253 nPrefBufferEntries = 32, 254 ), 255 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 256 tagECC = Some("secded"), 257 dataECC = Some("secded"), 258 replacer = Some("setplru"), 259 nMissEntries = 16, 260 nProbeEntries = 8, 261 nReleaseEntries = 18, 262 nMaxPrefetchEntry = 6, 263 )), 264 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 265 name = "l2", 266 ways = 8, 267 sets = 1024, // default 512KB L2 268 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 269 )), 270 L2NBanks: Int = 1, 271 usePTWRepeater: Boolean = false, 272 softTLB: Boolean = false, // dpi-c l1tlb debug only 273 softPTW: Boolean = false, // dpi-c l2tlb debug only 274 softPTWDelay: Int = 1 275){ 276 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 277 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 278 279 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 280 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 281 282 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 283 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 284 285 val fpExuConfigs = 286 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 287 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 288 289 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 290} 291 292case object DebugOptionsKey extends Field[DebugOptions] 293 294case class DebugOptions 295( 296 FPGAPlatform: Boolean = false, 297 EnableDifftest: Boolean = false, 298 AlwaysBasicDiff: Boolean = true, 299 EnableDebug: Boolean = false, 300 EnablePerfDebug: Boolean = true, 301 UseDRAMSim: Boolean = false, 302 EnableConstantin: Boolean = false, 303 EnableChiselDB: Boolean = false, 304 AlwaysBasicDB: Boolean = true, 305 EnableRollingDB: Boolean = false 306) 307 308trait HasXSParameter { 309 310 implicit val p: Parameters 311 312 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 313 314 val coreParams = p(XSCoreParamsKey) 315 val env = p(DebugOptionsKey) 316 317 val XLEN = coreParams.XLEN 318 val VLEN = coreParams.VLEN 319 val minFLen = 32 320 val fLen = 64 321 def xLen = XLEN 322 323 val HasMExtension = coreParams.HasMExtension 324 val HasCExtension = coreParams.HasCExtension 325 val HasDiv = coreParams.HasDiv 326 val HasIcache = coreParams.HasICache 327 val HasDcache = coreParams.HasDCache 328 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 329 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 330 val AsidLength = coreParams.AsidLength 331 val ReSelectLen = coreParams.ReSelectLen 332 val AddrBytes = AddrBits / 8 // unused 333 val DataBits = XLEN 334 val DataBytes = DataBits / 8 335 val VDataBytes = VLEN / 8 336 val HasFPU = coreParams.HasFPU 337 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 338 val FetchWidth = coreParams.FetchWidth 339 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 340 val EnableBPU = coreParams.EnableBPU 341 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 342 val EnableRAS = coreParams.EnableRAS 343 val EnableLB = coreParams.EnableLB 344 val EnableLoop = coreParams.EnableLoop 345 val EnableSC = coreParams.EnableSC 346 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 347 val HistoryLength = coreParams.HistoryLength 348 val EnableGHistDiff = coreParams.EnableGHistDiff 349 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 350 val UbtbGHRLength = coreParams.UbtbGHRLength 351 val UbtbSize = coreParams.UbtbSize 352 val EnableFauFTB = coreParams.EnableFauFTB 353 val FtbSize = coreParams.FtbSize 354 val FtbWays = coreParams.FtbWays 355 val RasSize = coreParams.RasSize 356 val RasSpecSize = coreParams.RasSpecSize 357 val RasCtrSize = coreParams.RasCtrSize 358 359 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 360 coreParams.branchPredictor(resp_in, p) 361 } 362 val numBr = coreParams.numBr 363 val TageTableInfos = coreParams.TageTableInfos 364 val TageBanks = coreParams.numBr 365 val SCNRows = coreParams.SCNRows 366 val SCCtrBits = coreParams.SCCtrBits 367 val SCHistLens = coreParams.SCHistLens 368 val SCNTables = coreParams.SCNTables 369 370 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 371 case ((n, cb), h) => (n, cb, h) 372 } 373 val ITTageTableInfos = coreParams.ITTageTableInfos 374 type FoldedHistoryInfo = Tuple2[Int, Int] 375 val foldedGHistInfos = 376 (TageTableInfos.map{ case (nRows, h, t) => 377 if (h > 0) 378 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 379 else 380 Set[FoldedHistoryInfo]() 381 }.reduce(_++_).toSet ++ 382 SCTableInfos.map{ case (nRows, _, h) => 383 if (h > 0) 384 Set((h, min(log2Ceil(nRows/TageBanks), h))) 385 else 386 Set[FoldedHistoryInfo]() 387 }.reduce(_++_).toSet ++ 388 ITTageTableInfos.map{ case (nRows, h, t) => 389 if (h > 0) 390 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 391 else 392 Set[FoldedHistoryInfo]() 393 }.reduce(_++_) ++ 394 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 395 ).toList 396 397 398 399 val CacheLineSize = coreParams.CacheLineSize 400 val CacheLineHalfWord = CacheLineSize / 16 401 val ExtHistoryLength = HistoryLength + 64 402 val ICacheECCForceError = coreParams.ICacheECCForceError 403 val IBufSize = coreParams.IBufSize 404 val DecodeWidth = coreParams.DecodeWidth 405 val RenameWidth = coreParams.RenameWidth 406 val CommitWidth = coreParams.CommitWidth 407 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 408 val RenameSnapshotNum = coreParams.RenameSnapshotNum 409 val FtqSize = coreParams.FtqSize 410 val IssQueSize = coreParams.IssQueSize 411 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 412 val NRPhyRegs = coreParams.NRPhyRegs 413 val PhyRegIdxWidth = log2Up(NRPhyRegs) 414 val RobSize = coreParams.RobSize 415 val IntRefCounterWidth = log2Ceil(RobSize) 416 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 417 val LoadQueueRARSize = coreParams.LoadQueueRARSize 418 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 419 val RollbackGroupSize = coreParams.RollbackGroupSize 420 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 421 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 422 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 423 val StoreQueueSize = coreParams.StoreQueueSize 424 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 425 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 426 val VlsQueueSize = coreParams.VlsQueueSize 427 val dpParams = coreParams.dpParams 428 val exuParameters = coreParams.exuParameters 429 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 430 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 431 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 432 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 433 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 434 val NumRedirect = exuParameters.JmpCnt + exuParameters.AluCnt 435 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 436 val LoadPipelineWidth = coreParams.LoadPipelineWidth 437 val StorePipelineWidth = coreParams.StorePipelineWidth 438 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 439 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 440 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 441 val StoreBufferSize = coreParams.StoreBufferSize 442 val StoreBufferThreshold = coreParams.StoreBufferThreshold 443 val EnsbufferWidth = coreParams.EnsbufferWidth 444 val UncacheBufferSize = coreParams.UncacheBufferSize 445 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 446 val EnableFastForward = coreParams.EnableFastForward 447 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 448 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 449 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 450 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 451 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 452 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 453 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 454 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 455 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 456 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 457 val asidLen = coreParams.MMUAsidLen 458 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 459 val refillBothTlb = coreParams.refillBothTlb 460 val iwpuParam = coreParams.iwpuParameters 461 val dwpuParam = coreParams.dwpuParameters 462 val itlbParams = coreParams.itlbParameters 463 val ldtlbParams = coreParams.ldtlbParameters 464 val sttlbParams = coreParams.sttlbParameters 465 val pftlbParams = coreParams.pftlbParameters 466 val btlbParams = coreParams.btlbParameters 467 val l2tlbParams = coreParams.l2tlbParameters 468 val NumPerfCounters = coreParams.NumPerfCounters 469 470 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 471 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 472 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 473 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 474 475 val instBytes = if (HasCExtension) 2 else 4 476 val instOffsetBits = log2Ceil(instBytes) 477 478 val icacheParameters = coreParams.icacheParameters 479 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 480 481 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 482 // for constrained LR/SC loop 483 val LRSCCycles = 64 484 // for lr storm 485 val LRSCBackOff = 8 486 487 // cache hierarchy configurations 488 val l1BusDataWidth = 256 489 490 // load violation predict 491 val ResetTimeMax2Pow = 20 //1078576 492 val ResetTimeMin2Pow = 10 //1024 493 // wait table parameters 494 val WaitTableSize = 1024 495 val MemPredPCWidth = log2Up(WaitTableSize) 496 val LWTUse2BitCounter = true 497 // store set parameters 498 val SSITSize = WaitTableSize 499 val LFSTSize = 32 500 val SSIDWidth = log2Up(LFSTSize) 501 val LFSTWidth = 4 502 val StoreSetEnable = true // LWT will be disabled if SS is enabled 503 val LFSTEnable = false 504 val loadExuConfigs = coreParams.loadExuConfigs 505 val storeExuConfigs = coreParams.storeExuConfigs 506 507 val intExuConfigs = coreParams.intExuConfigs 508 509 val fpExuConfigs = coreParams.fpExuConfigs 510 511 val exuConfigs = coreParams.exuConfigs 512 513 val PCntIncrStep: Int = 6 514 val numPCntHc: Int = 25 515 val numPCntPtw: Int = 19 516 517 val numCSRPCntFrontend = 8 518 val numCSRPCntCtrl = 8 519 val numCSRPCntLsu = 8 520 val numCSRPCntHc = 5 521} 522