1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import freechips.rocketchip.tile.MaxHartIdBits 42import system.SoCParamsKey 43import huancun._ 44import huancun.debug._ 45import xiangshan.cache.wpu.WPUParameters 46import coupledL2._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.min 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBits: Int = 39, 72 GPAddrBits: Int = 41, 73 HasFPU: Boolean = true, 74 HasVPU: Boolean = true, 75 HasCustomCSRCacheOp: Boolean = true, 76 FetchWidth: Int = 8, 77 AsidLength: Int = 16, 78 VmidLength: Int = 14, 79 EnableBPU: Boolean = true, 80 EnableBPD: Boolean = true, 81 EnableRAS: Boolean = true, 82 EnableLB: Boolean = false, 83 EnableLoop: Boolean = true, 84 EnableSC: Boolean = true, 85 EnbaleTlbDebug: Boolean = false, 86 EnableClockGate: Boolean = true, 87 EnableJal: Boolean = false, 88 EnableFauFTB: Boolean = true, 89 UbtbGHRLength: Int = 4, 90 // HistoryLength: Int = 512, 91 EnableGHistDiff: Boolean = true, 92 EnableCommitGHistDiff: Boolean = true, 93 UbtbSize: Int = 256, 94 FtbSize: Int = 2048, 95 RasSize: Int = 16, 96 RasSpecSize: Int = 32, 97 RasCtrSize: Int = 3, 98 CacheLineSize: Int = 512, 99 FtbWays: Int = 4, 100 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 101 // Sets Hist Tag 102 Seq(( 4096, 8, 8), 103 ( 4096, 13, 8), 104 ( 4096, 32, 8), 105 ( 4096, 119, 8)), 106 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 107 // Sets Hist Tag 108 Seq(( 256, 4, 9), 109 ( 256, 8, 9), 110 ( 512, 13, 9), 111 ( 512, 16, 9), 112 ( 512, 32, 9)), 113 SCNRows: Int = 512, 114 SCNTables: Int = 4, 115 SCCtrBits: Int = 6, 116 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 117 numBr: Int = 2, 118 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 119 (resp_in: BranchPredictionResp, p: Parameters) => { 120 val ftb = Module(new FTB()(p)) 121 val uftb = Module(new FauFTB()(p)) 122 val tage = Module(new Tage_SC()(p)) 123 val ras = Module(new RAS()(p)) 124 val ittage = Module(new ITTage()(p)) 125 val preds = Seq(uftb, tage, ftb, ittage, ras) 126 preds.map(_.io := DontCare) 127 128 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 129 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 130 131 uftb.io.in.bits.resp_in(0) := resp_in 132 tage.io.in.bits.resp_in(0) := uftb.io.out 133 ftb.io.in.bits.resp_in(0) := tage.io.out 134 ittage.io.in.bits.resp_in(0) := ftb.io.out 135 ras.io.in.bits.resp_in(0) := ittage.io.out 136 137 (preds, ras.io.out) 138 }, 139 ICacheECCForceError: Boolean = false, 140 IBufSize: Int = 48, 141 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 142 DecodeWidth: Int = 6, 143 RenameWidth: Int = 6, 144 CommitWidth: Int = 8, 145 RobCommitWidth: Int = 8, 146 RabCommitWidth: Int = 6, 147 MaxUopSize: Int = 65, 148 EnableRenameSnapshot: Boolean = true, 149 RenameSnapshotNum: Int = 4, 150 FtqSize: Int = 64, 151 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 152 IntLogicRegs: Int = 32, 153 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 154 VecLogicRegs: Int = 32 + 15, // 15: tmp 155 V0LogicRegs: Int = 1, // V0 156 VlLogicRegs: Int = 1, // Vl 157 V0_IDX: Int = 0, 158 Vl_IDX: Int = 0, 159 NRPhyRegs: Int = 192, 160 VirtualLoadQueueSize: Int = 72, 161 LoadQueueRARSize: Int = 72, 162 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 163 RollbackGroupSize: Int = 8, 164 LoadQueueReplaySize: Int = 72, 165 LoadUncacheBufferSize: Int = 20, 166 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 167 StoreQueueSize: Int = 64, 168 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 169 StoreQueueForwardWithMask: Boolean = true, 170 VlsQueueSize: Int = 8, 171 RobSize: Int = 160, 172 RabSize: Int = 256, 173 VTypeBufferSize: Int = 64, // used to reorder vtype 174 IssueQueueSize: Int = 24, 175 IssueQueueCompEntrySize: Int = 16, 176 dpParams: DispatchParameters = DispatchParameters( 177 IntDqSize = 16, 178 FpDqSize = 16, 179 LsDqSize = 18, 180 IntDqDeqWidth = 8, 181 FpDqDeqWidth = 6, 182 VecDqDeqWidth = 6, 183 LsDqDeqWidth = 6, 184 ), 185 intPreg: PregParams = IntPregParams( 186 numEntries = 224, 187 numRead = None, 188 numWrite = None, 189 ), 190 fpPreg: PregParams = FpPregParams( 191 numEntries = 192, 192 numRead = None, 193 numWrite = None, 194 ), 195 vfPreg: VfPregParams = VfPregParams( 196 numEntries = 128, 197 numRead = None, 198 numWrite = None, 199 ), 200 v0Preg: V0PregParams = V0PregParams( 201 numEntries = 22, 202 numRead = None, 203 numWrite = None, 204 ), 205 vlPreg: VlPregParams = VlPregParams( 206 numEntries = 32, 207 numRead = None, 208 numWrite = None, 209 ), 210 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 211 LoadPipelineWidth: Int = 3, 212 StorePipelineWidth: Int = 2, 213 VecLoadPipelineWidth: Int = 2, 214 VecStorePipelineWidth: Int = 2, 215 VecMemSrcInWidth: Int = 2, 216 VecMemInstWbWidth: Int = 1, 217 VecMemDispatchWidth: Int = 1, 218 VecMemDispatchMaxNumber: Int = 16, 219 StoreBufferSize: Int = 16, 220 StoreBufferThreshold: Int = 7, 221 EnsbufferWidth: Int = 2, 222 LoadDependencyWidth: Int = 2, 223 // ============ VLSU ============ 224 VlMergeBufferSize: Int = 16, 225 VsMergeBufferSize: Int = 16, 226 UopWritebackWidth: Int = 2, 227 VLUopWritebackWidth: Int = 2, 228 VSUopWritebackWidth: Int = 1, 229 VSegmentBufferSize: Int = 8, 230 // ============================== 231 UncacheBufferSize: Int = 4, 232 EnableLoadToLoadForward: Boolean = false, 233 EnableFastForward: Boolean = true, 234 EnableLdVioCheckAfterReset: Boolean = true, 235 EnableSoftPrefetchAfterReset: Boolean = true, 236 EnableCacheErrorAfterReset: Boolean = true, 237 EnableAccurateLoadError: Boolean = false, 238 EnableUncacheWriteOutstanding: Boolean = false, 239 EnableStorePrefetchAtIssue: Boolean = false, 240 EnableStorePrefetchAtCommit: Boolean = false, 241 EnableAtCommitMissTrigger: Boolean = true, 242 EnableStorePrefetchSMS: Boolean = false, 243 EnableStorePrefetchSPB: Boolean = false, 244 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 245 MMUVmidLen: Int = 14, 246 ReSelectLen: Int = 7, // load replay queue replay select counter len 247 iwpuParameters: WPUParameters = WPUParameters( 248 enWPU = false, 249 algoName = "mmru", 250 isICache = true, 251 ), 252 dwpuParameters: WPUParameters = WPUParameters( 253 enWPU = false, 254 algoName = "mmru", 255 enCfPred = false, 256 isICache = false, 257 ), 258 itlbParameters: TLBParameters = TLBParameters( 259 name = "itlb", 260 fetchi = true, 261 useDmode = false, 262 NWays = 48, 263 ), 264 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 265 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 266 ldtlbParameters: TLBParameters = TLBParameters( 267 name = "ldtlb", 268 NWays = 48, 269 outReplace = false, 270 partialStaticPMP = true, 271 outsideRecvFlush = true, 272 saveLevel = true, 273 lgMaxSize = 4 274 ), 275 sttlbParameters: TLBParameters = TLBParameters( 276 name = "sttlb", 277 NWays = 48, 278 outReplace = false, 279 partialStaticPMP = true, 280 outsideRecvFlush = true, 281 saveLevel = true, 282 lgMaxSize = 4 283 ), 284 hytlbParameters: TLBParameters = TLBParameters( 285 name = "hytlb", 286 NWays = 48, 287 outReplace = false, 288 partialStaticPMP = true, 289 outsideRecvFlush = true, 290 saveLevel = true, 291 lgMaxSize = 4 292 ), 293 pftlbParameters: TLBParameters = TLBParameters( 294 name = "pftlb", 295 NWays = 48, 296 outReplace = false, 297 partialStaticPMP = true, 298 outsideRecvFlush = true, 299 saveLevel = true, 300 lgMaxSize = 4 301 ), 302 l2ToL1tlbParameters: TLBParameters = TLBParameters( 303 name = "l2tlb", 304 NWays = 48, 305 outReplace = false, 306 partialStaticPMP = true, 307 outsideRecvFlush = true, 308 saveLevel = true 309 ), 310 refillBothTlb: Boolean = false, 311 btlbParameters: TLBParameters = TLBParameters( 312 name = "btlb", 313 NWays = 48, 314 ), 315 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 316 NumPerfCounters: Int = 16, 317 icacheParameters: ICacheParameters = ICacheParameters( 318 tagECC = Some("parity"), 319 dataECC = Some("parity"), 320 replacer = Some("setplru"), 321 nMissEntries = 2, 322 nProbeEntries = 2, 323 nPrefetchEntries = 12, 324 nPrefBufferEntries = 32, 325 ), 326 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 327 tagECC = Some("secded"), 328 dataECC = Some("secded"), 329 replacer = Some("setplru"), 330 nMissEntries = 16, 331 nProbeEntries = 8, 332 nReleaseEntries = 18, 333 nMaxPrefetchEntry = 6, 334 )), 335 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 336 name = "l2", 337 ways = 8, 338 sets = 1024, // default 512KB L2 339 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 340 coupledL2.prefetch.TPParameters()), 341 )), 342 L2NBanks: Int = 1, 343 usePTWRepeater: Boolean = false, 344 softTLB: Boolean = false, // dpi-c l1tlb debug only 345 softPTW: Boolean = false, // dpi-c l2tlb debug only 346 softPTWDelay: Int = 1 347){ 348 def vlWidth = log2Up(VLEN) + 1 349 350 /** 351 * the minimum element length of vector elements 352 */ 353 val minVecElen: Int = 8 354 355 /** 356 * the maximum number of elements in vector register 357 */ 358 val maxElemPerVreg: Int = VLEN / minVecElen 359 360 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 361 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 362 363 val intSchdParams = { 364 implicit val schdType: SchedulerType = IntScheduler() 365 SchdBlockParams(Seq( 366 IssueBlockParams(Seq( 367 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 368 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(1, 1))), true, 2), 369 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 370 IssueBlockParams(Seq( 371 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 372 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(3, 1))), true, 2), 373 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 374 IssueBlockParams(Seq( 375 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 376 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = 0, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(5, 1)))), 377 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 378 IssueBlockParams(Seq( 379 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 380 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(7, 1)))), 381 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 382 ), 383 numPregs = intPreg.numEntries, 384 numDeqOutside = 0, 385 schdType = schdType, 386 rfDataWidth = intPreg.dataCfg.dataWidth, 387 numUopIn = dpParams.IntDqDeqWidth, 388 ) 389 } 390 391 val fpSchdParams = { 392 implicit val schdType: SchedulerType = FpScheduler() 393 SchdBlockParams(Seq( 394 IssueBlockParams(Seq( 395 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 396 ), numEntries = 18, numEnq = 2, numComp = 16), 397 IssueBlockParams(Seq( 398 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 399 ), numEntries = 18, numEnq = 2, numComp = 16), 400 IssueBlockParams(Seq( 401 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 402 ), numEntries = 18, numEnq = 2, numComp = 16), 403 IssueBlockParams(Seq( 404 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 405 ), numEntries = 18, numEnq = 2, numComp = 16), 406 IssueBlockParams(Seq( 407 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 408 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 409 ), numEntries = 18, numEnq = 2, numComp = 16), 410 ), 411 numPregs = fpPreg.numEntries, 412 numDeqOutside = 0, 413 schdType = schdType, 414 rfDataWidth = fpPreg.dataCfg.dataWidth, 415 numUopIn = dpParams.VecDqDeqWidth, 416 ) 417 } 418 419 val vfSchdParams = { 420 implicit val schdType: SchedulerType = VfScheduler() 421 SchdBlockParams(Seq( 422 IssueBlockParams(Seq( 423 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 424 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = 1, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 425 ), numEntries = 16, numEnq = 2, numComp = 14), 426 IssueBlockParams(Seq( 427 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 428 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 429 ), numEntries = 16, numEnq = 2, numComp = 14), 430 IssueBlockParams(Seq( 431 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 432 ), numEntries = 10, numEnq = 2, numComp = 8), 433 ), 434 numPregs = vfPreg.numEntries, 435 numDeqOutside = 0, 436 schdType = schdType, 437 rfDataWidth = vfPreg.dataCfg.dataWidth, 438 numUopIn = dpParams.VecDqDeqWidth, 439 ) 440 } 441 442 val memSchdParams = { 443 implicit val schdType: SchedulerType = MemScheduler() 444 val rfDataWidth = 64 445 446 SchdBlockParams(Seq( 447 IssueBlockParams(Seq( 448 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(11, 1)))), 449 ), numEntries = 16, numEnq = 2, numComp = 14), 450 IssueBlockParams(Seq( 451 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(8, 1)))), 452 ), numEntries = 16, numEnq = 2, numComp = 14), 453 IssueBlockParams(Seq( 454 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 455 ), numEntries = 16, numEnq = 2, numComp = 14), 456 IssueBlockParams(Seq( 457 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 458 ), numEntries = 16, numEnq = 2, numComp = 14), 459 IssueBlockParams(Seq( 460 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 461 ), numEntries = 16, numEnq = 2, numComp = 14), 462 IssueBlockParams(Seq( 463 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 464 ), numEntries = 16, numEnq = 2, numComp = 14), 465 IssueBlockParams(Seq( 466 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 467 ), numEntries = 16, numEnq = 2, numComp = 14), 468 IssueBlockParams(Seq( 469 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(10, 1), FpRD(12, 0)))), 470 ), numEntries = 16, numEnq = 2, numComp = 14), 471 IssueBlockParams(Seq( 472 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(11, 1), FpRD(13, 0)))), 473 ), numEntries = 16, numEnq = 2, numComp = 14), 474 ), 475 numPregs = intPreg.numEntries max vfPreg.numEntries, 476 numDeqOutside = 0, 477 schdType = schdType, 478 rfDataWidth = rfDataWidth, 479 numUopIn = dpParams.LsDqDeqWidth, 480 ) 481 } 482 483 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 484 485 def iqWakeUpParams = { 486 Seq( 487 WakeUpConfig( 488 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 489 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 490 ), 491 WakeUpConfig( 492 Seq("FEX0", "FEX1", "FEX2", "FEX3", "LDU0", "LDU1", "LDU2") -> 493 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 494 ), 495 WakeUpConfig( 496 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 497 Seq("STD0", "STD1") 498 ), 499 WakeUpConfig( 500 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 501 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "VFEX4") 502 ), 503 ).flatten 504 } 505 506 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 507 508 val backendParams: BackendParams = backend.BackendParams( 509 Map( 510 IntScheduler() -> intSchdParams, 511 FpScheduler() -> fpSchdParams, 512 VfScheduler() -> vfSchdParams, 513 MemScheduler() -> memSchdParams, 514 ), 515 Seq( 516 intPreg, 517 fpPreg, 518 vfPreg, 519 v0Preg, 520 vlPreg, 521 fakeIntPreg 522 ), 523 iqWakeUpParams, 524 ) 525} 526 527case object DebugOptionsKey extends Field[DebugOptions] 528 529case class DebugOptions 530( 531 FPGAPlatform: Boolean = false, 532 ResetGen: Boolean = false, 533 EnableDifftest: Boolean = false, 534 AlwaysBasicDiff: Boolean = true, 535 EnableDebug: Boolean = false, 536 EnablePerfDebug: Boolean = true, 537 UseDRAMSim: Boolean = false, 538 EnableConstantin: Boolean = false, 539 EnableChiselDB: Boolean = false, 540 AlwaysBasicDB: Boolean = true, 541 EnableTopDown: Boolean = false, 542 EnableRollingDB: Boolean = false 543) 544 545trait HasXSParameter { 546 547 implicit val p: Parameters 548 549 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 550 def NodeIDWidth = p(SoCParamsKey).NodeIDWidth // NodeID width among NoC 551 552 def coreParams = p(XSCoreParamsKey) 553 def env = p(DebugOptionsKey) 554 555 def XLEN = coreParams.XLEN 556 def VLEN = coreParams.VLEN 557 def ELEN = coreParams.ELEN 558 def HSXLEN = coreParams.HSXLEN 559 val minFLen = 32 560 val fLen = 64 561 def hartIdLen = p(MaxHartIdBits) 562 val xLen = XLEN 563 564 def HasMExtension = coreParams.HasMExtension 565 def HasCExtension = coreParams.HasCExtension 566 def HasHExtension = coreParams.HasHExtension 567 def HasDiv = coreParams.HasDiv 568 def HasIcache = coreParams.HasICache 569 def HasDcache = coreParams.HasDCache 570 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 571 def GPAddrBits = coreParams.GPAddrBits 572 def VAddrBits = { 573 if(HasHExtension){ 574 coreParams.GPAddrBits 575 }else{ 576 coreParams.VAddrBits 577 } 578 } // VAddrBits is Virtual Memory addr bits 579 580 def AsidLength = coreParams.AsidLength 581 def VmidLength = coreParams.VmidLength 582 def ReSelectLen = coreParams.ReSelectLen 583 def AddrBytes = AddrBits / 8 // unused 584 def DataBits = XLEN 585 def DataBytes = DataBits / 8 586 def VDataBytes = VLEN / 8 587 def HasFPU = coreParams.HasFPU 588 def HasVPU = coreParams.HasVPU 589 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 590 def FetchWidth = coreParams.FetchWidth 591 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 592 def EnableBPU = coreParams.EnableBPU 593 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 594 def EnableRAS = coreParams.EnableRAS 595 def EnableLB = coreParams.EnableLB 596 def EnableLoop = coreParams.EnableLoop 597 def EnableSC = coreParams.EnableSC 598 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 599 def HistoryLength = coreParams.HistoryLength 600 def EnableGHistDiff = coreParams.EnableGHistDiff 601 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 602 def EnableClockGate = coreParams.EnableClockGate 603 def UbtbGHRLength = coreParams.UbtbGHRLength 604 def UbtbSize = coreParams.UbtbSize 605 def EnableFauFTB = coreParams.EnableFauFTB 606 def FtbSize = coreParams.FtbSize 607 def FtbWays = coreParams.FtbWays 608 def RasSize = coreParams.RasSize 609 def RasSpecSize = coreParams.RasSpecSize 610 def RasCtrSize = coreParams.RasCtrSize 611 612 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 613 coreParams.branchPredictor(resp_in, p) 614 } 615 def numBr = coreParams.numBr 616 def TageTableInfos = coreParams.TageTableInfos 617 def TageBanks = coreParams.numBr 618 def SCNRows = coreParams.SCNRows 619 def SCCtrBits = coreParams.SCCtrBits 620 def SCHistLens = coreParams.SCHistLens 621 def SCNTables = coreParams.SCNTables 622 623 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 624 case ((n, cb), h) => (n, cb, h) 625 } 626 def ITTageTableInfos = coreParams.ITTageTableInfos 627 type FoldedHistoryInfo = Tuple2[Int, Int] 628 def foldedGHistInfos = 629 (TageTableInfos.map{ case (nRows, h, t) => 630 if (h > 0) 631 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 632 else 633 Set[FoldedHistoryInfo]() 634 }.reduce(_++_).toSet ++ 635 SCTableInfos.map{ case (nRows, _, h) => 636 if (h > 0) 637 Set((h, min(log2Ceil(nRows/TageBanks), h))) 638 else 639 Set[FoldedHistoryInfo]() 640 }.reduce(_++_).toSet ++ 641 ITTageTableInfos.map{ case (nRows, h, t) => 642 if (h > 0) 643 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 644 else 645 Set[FoldedHistoryInfo]() 646 }.reduce(_++_) ++ 647 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 648 ).toList 649 650 651 652 def CacheLineSize = coreParams.CacheLineSize 653 def CacheLineHalfWord = CacheLineSize / 16 654 def ExtHistoryLength = HistoryLength + 64 655 def ICacheECCForceError = coreParams.ICacheECCForceError 656 def IBufSize = coreParams.IBufSize 657 def IBufNBank = coreParams.IBufNBank 658 def backendParams: BackendParams = coreParams.backendParams 659 def DecodeWidth = coreParams.DecodeWidth 660 def RenameWidth = coreParams.RenameWidth 661 def CommitWidth = coreParams.CommitWidth 662 def RobCommitWidth = coreParams.RobCommitWidth 663 def RabCommitWidth = coreParams.RabCommitWidth 664 def MaxUopSize = coreParams.MaxUopSize 665 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 666 def RenameSnapshotNum = coreParams.RenameSnapshotNum 667 def FtqSize = coreParams.FtqSize 668 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 669 def IntLogicRegs = coreParams.IntLogicRegs 670 def FpLogicRegs = coreParams.FpLogicRegs 671 def VecLogicRegs = coreParams.VecLogicRegs 672 def V0LogicRegs = coreParams.V0LogicRegs 673 def VlLogicRegs = coreParams.VlLogicRegs 674 def V0_IDX = coreParams.V0_IDX 675 def Vl_IDX = coreParams.Vl_IDX 676 def IntPhyRegs = coreParams.intPreg.numEntries 677 def FpPhyRegs = coreParams.fpPreg.numEntries 678 def VfPhyRegs = coreParams.vfPreg.numEntries 679 def V0PhyRegs = coreParams.v0Preg.numEntries 680 def VlPhyRegs = coreParams.vlPreg.numEntries 681 def MaxPhyPregs = IntPhyRegs max VfPhyRegs 682 def PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(FpPhyRegs) max log2Up(VfPhyRegs) 683 def RobSize = coreParams.RobSize 684 def RabSize = coreParams.RabSize 685 def VTypeBufferSize = coreParams.VTypeBufferSize 686 /** 687 * the minimum element length of vector elements 688 */ 689 def minVecElen: Int = coreParams.minVecElen 690 691 /** 692 * the maximum number of elements in vector register 693 */ 694 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 695 696 def IntRefCounterWidth = log2Ceil(RobSize) 697 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 698 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 699 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 700 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 701 def LoadQueueRARSize = coreParams.LoadQueueRARSize 702 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 703 def RollbackGroupSize = coreParams.RollbackGroupSize 704 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 705 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 706 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 707 def StoreQueueSize = coreParams.StoreQueueSize 708 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 709 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 710 def VlsQueueSize = coreParams.VlsQueueSize 711 def dpParams = coreParams.dpParams 712 713 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 714 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 715 716 def NumRedirect = backendParams.numRedirect 717 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 718 def FtqRedirectAheadNum = NumRedirect 719 def LoadPipelineWidth = coreParams.LoadPipelineWidth 720 def StorePipelineWidth = coreParams.StorePipelineWidth 721 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 722 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 723 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 724 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 725 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 726 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 727 def StoreBufferSize = coreParams.StoreBufferSize 728 def StoreBufferThreshold = coreParams.StoreBufferThreshold 729 def EnsbufferWidth = coreParams.EnsbufferWidth 730 def LoadDependencyWidth = coreParams.LoadDependencyWidth 731 def VlMergeBufferSize = coreParams.VlMergeBufferSize 732 def VsMergeBufferSize = coreParams.VsMergeBufferSize 733 def UopWritebackWidth = coreParams.UopWritebackWidth 734 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 735 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 736 def VSegmentBufferSize = coreParams.VSegmentBufferSize 737 def UncacheBufferSize = coreParams.UncacheBufferSize 738 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 739 def EnableFastForward = coreParams.EnableFastForward 740 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 741 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 742 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 743 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 744 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 745 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 746 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 747 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 748 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 749 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 750 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 751 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 752 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 753 def asidLen = coreParams.MMUAsidLen 754 def vmidLen = coreParams.MMUVmidLen 755 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 756 def refillBothTlb = coreParams.refillBothTlb 757 def iwpuParam = coreParams.iwpuParameters 758 def dwpuParam = coreParams.dwpuParameters 759 def itlbParams = coreParams.itlbParameters 760 def ldtlbParams = coreParams.ldtlbParameters 761 def sttlbParams = coreParams.sttlbParameters 762 def hytlbParams = coreParams.hytlbParameters 763 def pftlbParams = coreParams.pftlbParameters 764 def l2ToL1Params = coreParams.l2ToL1tlbParameters 765 def btlbParams = coreParams.btlbParameters 766 def l2tlbParams = coreParams.l2tlbParameters 767 def NumPerfCounters = coreParams.NumPerfCounters 768 769 def instBytes = if (HasCExtension) 2 else 4 770 def instOffsetBits = log2Ceil(instBytes) 771 772 def icacheParameters = coreParams.icacheParameters 773 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 774 775 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 776 // for constrained LR/SC loop 777 def LRSCCycles = 64 778 // for lr storm 779 def LRSCBackOff = 8 780 781 // cache hierarchy configurations 782 def l1BusDataWidth = 256 783 784 // load violation predict 785 def ResetTimeMax2Pow = 20 //1078576 786 def ResetTimeMin2Pow = 10 //1024 787 // wait table parameters 788 def WaitTableSize = 1024 789 def MemPredPCWidth = log2Up(WaitTableSize) 790 def LWTUse2BitCounter = true 791 // store set parameters 792 def SSITSize = WaitTableSize 793 def LFSTSize = 32 794 def SSIDWidth = log2Up(LFSTSize) 795 def LFSTWidth = 4 796 def StoreSetEnable = true // LWT will be disabled if SS is enabled 797 def LFSTEnable = true 798 799 def PCntIncrStep: Int = 6 800 def numPCntHc: Int = 25 801 def numPCntPtw: Int = 19 802 803 def numCSRPCntFrontend = 8 804 def numCSRPCntCtrl = 8 805 def numCSRPCntLsu = 8 806 def numCSRPCntHc = 5 807 def printEventCoding = true 808 809 // Parameters for Sdtrig extension 810 protected def TriggerNum = 4 811 protected def TriggerChainMaxLength = 2 812} 813