1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, MicroBTB, RAS, Tage, ITTage, Tage_SC} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasCustomCSRCacheOp: Boolean = true, 53 FetchWidth: Int = 8, 54 AsidLength: Int = 16, 55 EnableBPU: Boolean = true, 56 EnableBPD: Boolean = true, 57 EnableRAS: Boolean = true, 58 EnableLB: Boolean = false, 59 EnableLoop: Boolean = true, 60 EnableSC: Boolean = true, 61 EnbaleTlbDebug: Boolean = false, 62 EnableJal: Boolean = false, 63 EnableUBTB: Boolean = true, 64 UbtbGHRLength: Int = 4, 65 // HistoryLength: Int = 512, 66 EnableGHistDiff: Boolean = true, 67 UbtbSize: Int = 256, 68 FtbSize: Int = 2048, 69 RasSize: Int = 32, 70 CacheLineSize: Int = 512, 71 FtbWays: Int = 4, 72 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 73 // Sets Hist Tag 74 // Seq(( 2048, 2, 8), 75 // ( 2048, 9, 8), 76 // ( 2048, 13, 8), 77 // ( 2048, 20, 8), 78 // ( 2048, 26, 8), 79 // ( 2048, 44, 8), 80 // ( 2048, 73, 8), 81 // ( 2048, 256, 8)), 82 Seq(( 4096, 8, 8), 83 ( 4096, 13, 8), 84 ( 4096, 32, 8), 85 ( 4096, 119, 8)), 86 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 87 // Sets Hist Tag 88 Seq(( 256, 4, 9), 89 ( 256, 8, 9), 90 ( 512, 13, 9), 91 ( 512, 16, 9), 92 ( 512, 32, 9)), 93 SCNRows: Int = 512, 94 SCNTables: Int = 4, 95 SCCtrBits: Int = 6, 96 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 97 numBr: Int = 2, 98 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 99 ((resp_in: BranchPredictionResp, p: Parameters) => { 100 // val loop = Module(new LoopPredictor) 101 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 102 // else Module(new Tage) } 103 // else { Module(new FakeTage) }) 104 val ftb = Module(new FTB()(p)) 105 val ubtb = Module(new MicroBTB()(p)) 106 // val bim = Module(new BIM()(p)) 107 val tage = Module(new Tage_SC()(p)) 108 val ras = Module(new RAS()(p)) 109 val ittage = Module(new ITTage()(p)) 110 // val tage = Module(new Tage()(p)) 111 // val fake = Module(new FakePredictor()(p)) 112 113 // val preds = Seq(loop, tage, btb, ubtb, bim) 114 val preds = Seq(ubtb, tage, ftb, ittage, ras) 115 preds.map(_.io := DontCare) 116 117 // ubtb.io.resp_in(0) := resp_in 118 // bim.io.resp_in(0) := ubtb.io.resp 119 // btb.io.resp_in(0) := bim.io.resp 120 // tage.io.resp_in(0) := btb.io.resp 121 // loop.io.resp_in(0) := tage.io.resp 122 ubtb.io.in.bits.resp_in(0) := resp_in 123 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 124 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 125 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 126 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 127 128 (preds, ras.io.out.resp) 129 }), 130 IBufSize: Int = 48, 131 DecodeWidth: Int = 6, 132 RenameWidth: Int = 6, 133 CommitWidth: Int = 6, 134 FtqSize: Int = 64, 135 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 136 IssQueSize: Int = 16, 137 NRPhyRegs: Int = 192, 138 LoadQueueSize: Int = 80, 139 StoreQueueSize: Int = 64, 140 RobSize: Int = 256, 141 dpParams: DispatchParameters = DispatchParameters( 142 IntDqSize = 16, 143 FpDqSize = 16, 144 LsDqSize = 16, 145 IntDqDeqWidth = 4, 146 FpDqDeqWidth = 4, 147 LsDqDeqWidth = 4 148 ), 149 exuParameters: ExuParameters = ExuParameters( 150 JmpCnt = 1, 151 AluCnt = 4, 152 MulCnt = 0, 153 MduCnt = 2, 154 FmacCnt = 4, 155 FmiscCnt = 2, 156 FmiscDivSqrtCnt = 0, 157 LduCnt = 2, 158 StuCnt = 2 159 ), 160 LoadPipelineWidth: Int = 2, 161 StorePipelineWidth: Int = 2, 162 StoreBufferSize: Int = 16, 163 StoreBufferThreshold: Int = 7, 164 EnsbufferWidth: Int = 2, 165 EnableLoadToLoadForward: Boolean = false, 166 EnableFastForward: Boolean = false, 167 EnableLdVioCheckAfterReset: Boolean = true, 168 EnableSoftPrefetchAfterReset: Boolean = true, 169 EnableCacheErrorAfterReset: Boolean = true, 170 RefillSize: Int = 512, 171 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 172 itlbParameters: TLBParameters = TLBParameters( 173 name = "itlb", 174 fetchi = true, 175 useDmode = false, 176 sameCycle = false, 177 missSameCycle = true, 178 normalNWays = 32, 179 normalReplacer = Some("plru"), 180 superNWays = 4, 181 superReplacer = Some("plru"), 182 shouldBlock = true 183 ), 184 ldtlbParameters: TLBParameters = TLBParameters( 185 name = "ldtlb", 186 normalNSets = 128, 187 normalNWays = 1, 188 normalAssociative = "sa", 189 normalReplacer = Some("setplru"), 190 superNWays = 8, 191 normalAsVictim = true, 192 outReplace = true, 193 partialStaticPMP = true, 194 saveLevel = true 195 ), 196 sttlbParameters: TLBParameters = TLBParameters( 197 name = "sttlb", 198 normalNSets = 128, 199 normalNWays = 1, 200 normalAssociative = "sa", 201 normalReplacer = Some("setplru"), 202 superNWays = 8, 203 normalAsVictim = true, 204 outReplace = true, 205 partialStaticPMP = true, 206 saveLevel = true 207 ), 208 refillBothTlb: Boolean = false, 209 btlbParameters: TLBParameters = TLBParameters( 210 name = "btlb", 211 normalNSets = 1, 212 normalNWays = 64, 213 superNWays = 4, 214 ), 215 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 216 NumPerfCounters: Int = 16, 217 icacheParameters: ICacheParameters = ICacheParameters( 218 tagECC = Some("parity"), 219 dataECC = Some("parity"), 220 replacer = Some("setplru"), 221 nMissEntries = 2, 222 nProbeEntries = 2, 223 nPrefetchEntries = 2, 224 hasPrefetch = true, 225 ), 226 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 227 tagECC = Some("secded"), 228 dataECC = Some("secded"), 229 replacer = Some("setplru"), 230 nMissEntries = 16, 231 nProbeEntries = 8, 232 nReleaseEntries = 18 233 )), 234 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 235 name = "l2", 236 level = 2, 237 ways = 8, 238 sets = 1024, // default 512KB L2 239 prefetch = Some(huancun.prefetch.BOPParameters()) 240 )), 241 L2NBanks: Int = 1, 242 usePTWRepeater: Boolean = false, 243 softPTW: Boolean = false // dpi-c debug only 244){ 245 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 246 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 247 248 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 249 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 250 251 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 252 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 253 254 val fpExuConfigs = 255 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 256 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 257 258 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 259} 260 261case object DebugOptionsKey extends Field[DebugOptions] 262 263case class DebugOptions 264( 265 FPGAPlatform: Boolean = false, 266 EnableDifftest: Boolean = false, 267 AlwaysBasicDiff: Boolean = true, 268 EnableDebug: Boolean = false, 269 EnablePerfDebug: Boolean = true, 270 UseDRAMSim: Boolean = false 271) 272 273trait HasXSParameter { 274 275 implicit val p: Parameters 276 277 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 278 279 val coreParams = p(XSCoreParamsKey) 280 val env = p(DebugOptionsKey) 281 282 val XLEN = coreParams.XLEN 283 val minFLen = 32 284 val fLen = 64 285 def xLen = XLEN 286 287 val HasMExtension = coreParams.HasMExtension 288 val HasCExtension = coreParams.HasCExtension 289 val HasDiv = coreParams.HasDiv 290 val HasIcache = coreParams.HasICache 291 val HasDcache = coreParams.HasDCache 292 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 293 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 294 val AsidLength = coreParams.AsidLength 295 val AddrBytes = AddrBits / 8 // unused 296 val DataBits = XLEN 297 val DataBytes = DataBits / 8 298 val HasFPU = coreParams.HasFPU 299 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 300 val FetchWidth = coreParams.FetchWidth 301 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 302 val EnableBPU = coreParams.EnableBPU 303 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 304 val EnableRAS = coreParams.EnableRAS 305 val EnableLB = coreParams.EnableLB 306 val EnableLoop = coreParams.EnableLoop 307 val EnableSC = coreParams.EnableSC 308 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 309 val HistoryLength = coreParams.HistoryLength 310 val EnableGHistDiff = coreParams.EnableGHistDiff 311 val UbtbGHRLength = coreParams.UbtbGHRLength 312 val UbtbSize = coreParams.UbtbSize 313 val FtbSize = coreParams.FtbSize 314 val FtbWays = coreParams.FtbWays 315 val RasSize = coreParams.RasSize 316 317 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 318 coreParams.branchPredictor(resp_in, p) 319 } 320 val numBr = coreParams.numBr 321 val TageTableInfos = coreParams.TageTableInfos 322 val TageBanks = coreParams.numBr 323 val SCNRows = coreParams.SCNRows 324 val SCCtrBits = coreParams.SCCtrBits 325 val SCHistLens = coreParams.SCHistLens 326 val SCNTables = coreParams.SCNTables 327 328 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 329 case ((n, cb), h) => (n, cb, h) 330 } 331 val ITTageTableInfos = coreParams.ITTageTableInfos 332 type FoldedHistoryInfo = Tuple2[Int, Int] 333 val foldedGHistInfos = 334 (TageTableInfos.map{ case (nRows, h, t) => 335 if (h > 0) 336 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 337 else 338 Set[FoldedHistoryInfo]() 339 }.reduce(_++_).toSet ++ 340 SCTableInfos.map{ case (nRows, _, h) => 341 if (h > 0) 342 Set((h, min(log2Ceil(nRows/TageBanks), h))) 343 else 344 Set[FoldedHistoryInfo]() 345 }.reduce(_++_).toSet ++ 346 ITTageTableInfos.map{ case (nRows, h, t) => 347 if (h > 0) 348 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 349 else 350 Set[FoldedHistoryInfo]() 351 }.reduce(_++_) ++ 352 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 353 ).toList 354 355 356 357 val CacheLineSize = coreParams.CacheLineSize 358 val CacheLineHalfWord = CacheLineSize / 16 359 val ExtHistoryLength = HistoryLength + 64 360 val IBufSize = coreParams.IBufSize 361 val DecodeWidth = coreParams.DecodeWidth 362 val RenameWidth = coreParams.RenameWidth 363 val CommitWidth = coreParams.CommitWidth 364 val FtqSize = coreParams.FtqSize 365 val IssQueSize = coreParams.IssQueSize 366 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 367 val NRPhyRegs = coreParams.NRPhyRegs 368 val PhyRegIdxWidth = log2Up(NRPhyRegs) 369 val RobSize = coreParams.RobSize 370 val IntRefCounterWidth = log2Ceil(RobSize) 371 val LoadQueueSize = coreParams.LoadQueueSize 372 val StoreQueueSize = coreParams.StoreQueueSize 373 val dpParams = coreParams.dpParams 374 val exuParameters = coreParams.exuParameters 375 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 376 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 377 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 378 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 379 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 380 val LoadPipelineWidth = coreParams.LoadPipelineWidth 381 val StorePipelineWidth = coreParams.StorePipelineWidth 382 val StoreBufferSize = coreParams.StoreBufferSize 383 val StoreBufferThreshold = coreParams.StoreBufferThreshold 384 val EnsbufferWidth = coreParams.EnsbufferWidth 385 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 386 val EnableFastForward = coreParams.EnableFastForward 387 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 388 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 389 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 390 val RefillSize = coreParams.RefillSize 391 val asidLen = coreParams.MMUAsidLen 392 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 393 val refillBothTlb = coreParams.refillBothTlb 394 val itlbParams = coreParams.itlbParameters 395 val ldtlbParams = coreParams.ldtlbParameters 396 val sttlbParams = coreParams.sttlbParameters 397 val btlbParams = coreParams.btlbParameters 398 val l2tlbParams = coreParams.l2tlbParameters 399 val NumPerfCounters = coreParams.NumPerfCounters 400 401 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 402 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 403 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 404 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 405 406 val instBytes = if (HasCExtension) 2 else 4 407 val instOffsetBits = log2Ceil(instBytes) 408 409 val icacheParameters = coreParams.icacheParameters 410 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 411 412 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 413 // for constrained LR/SC loop 414 val LRSCCycles = 64 415 // for lr storm 416 val LRSCBackOff = 8 417 418 // cache hierarchy configurations 419 val l1BusDataWidth = 256 420 421 // load violation predict 422 val ResetTimeMax2Pow = 20 //1078576 423 val ResetTimeMin2Pow = 10 //1024 424 // wait table parameters 425 val WaitTableSize = 1024 426 val MemPredPCWidth = log2Up(WaitTableSize) 427 val LWTUse2BitCounter = true 428 // store set parameters 429 val SSITSize = WaitTableSize 430 val LFSTSize = 32 431 val SSIDWidth = log2Up(LFSTSize) 432 val LFSTWidth = 4 433 val StoreSetEnable = true // LWT will be disabled if SS is enabled 434 435 val loadExuConfigs = coreParams.loadExuConfigs 436 val storeExuConfigs = coreParams.storeExuConfigs 437 438 val intExuConfigs = coreParams.intExuConfigs 439 440 val fpExuConfigs = coreParams.fpExuConfigs 441 442 val exuConfigs = coreParams.exuConfigs 443 444 val PCntIncrStep: Int = 6 445 val numPCntHc: Int = 25 446 val numPCntPtw: Int = 19 447 448 val numCSRPCntFrontend = 8 449 val numCSRPCntCtrl = 8 450 val numCSRPCntLsu = 8 451 val numCSRPCntHc = 5 452} 453