1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import huancun.{CacheParameters, HCCacheParameters} 27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, ITTage, Tage_SC} 28import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import scala.math.min 32 33case object XSTileKey extends Field[Seq[XSCoreParameters]] 34 35case object XSCoreParamsKey extends Field[XSCoreParameters] 36 37case class XSCoreParameters 38( 39 HasPrefetch: Boolean = false, 40 HartId: Int = 0, 41 XLEN: Int = 64, 42 HasMExtension: Boolean = true, 43 HasCExtension: Boolean = true, 44 HasDiv: Boolean = true, 45 HasICache: Boolean = true, 46 HasDCache: Boolean = true, 47 AddrBits: Int = 64, 48 VAddrBits: Int = 39, 49 HasFPU: Boolean = true, 50 HasCustomCSRCacheOp: Boolean = true, 51 FetchWidth: Int = 8, 52 AsidLength: Int = 16, 53 EnableBPU: Boolean = true, 54 EnableBPD: Boolean = true, 55 EnableRAS: Boolean = true, 56 EnableLB: Boolean = false, 57 EnableLoop: Boolean = true, 58 EnableSC: Boolean = true, 59 EnbaleTlbDebug: Boolean = false, 60 EnableJal: Boolean = false, 61 EnableUBTB: Boolean = true, 62 HistoryLength: Int = 256, 63 PathHistoryLength: Int = 16, 64 BtbSize: Int = 2048, 65 JbtacSize: Int = 1024, 66 JbtacBanks: Int = 8, 67 RasSize: Int = 32, 68 CacheLineSize: Int = 512, 69 UBtbWays: Int = 16, 70 BtbWays: Int = 2, 71 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 72 // Sets Hist Tag 73 Seq(( 128*8, 2, 7), 74 ( 128*8, 4, 7), 75 ( 256*8, 8, 8), 76 ( 256*8, 16, 8), 77 ( 128*8, 32, 9), 78 ( 128*8, 65, 9)), 79 TageBanks: Int = 2, 80 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 81 // Sets Hist Tag 82 Seq(( 512, 0, 0), 83 ( 256, 4, 8), 84 ( 256, 8, 8), 85 ( 512, 12, 8), 86 ( 512, 16, 8), 87 ( 512, 32, 8)), 88 SCNRows: Int = 1024, 89 SCNTables: Int = 6, 90 SCCtrBits: Int = 6, 91 numBr: Int = 2, 92 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 93 ((resp_in: BranchPredictionResp, p: Parameters) => { 94 // val loop = Module(new LoopPredictor) 95 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 96 // else Module(new Tage) } 97 // else { Module(new FakeTage) }) 98 val ftb = Module(new FTB()(p)) 99 val ubtb = Module(new MicroBTB()(p)) 100 val bim = Module(new BIM()(p)) 101 val tage = Module(new Tage_SC()(p)) 102 val ras = Module(new RAS()(p)) 103 val ittage = Module(new ITTage()(p)) 104 // val tage = Module(new Tage()(p)) 105 // val fake = Module(new FakePredictor()(p)) 106 107 // val preds = Seq(loop, tage, btb, ubtb, bim) 108 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 109 preds.map(_.io := DontCare) 110 111 // ubtb.io.resp_in(0) := resp_in 112 // bim.io.resp_in(0) := ubtb.io.resp 113 // btb.io.resp_in(0) := bim.io.resp 114 // tage.io.resp_in(0) := btb.io.resp 115 // loop.io.resp_in(0) := tage.io.resp 116 bim.io.in.bits.resp_in(0) := resp_in 117 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 118 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 119 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 120 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 121 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 122 123 (preds, ras.io.out.resp) 124 }), 125 IBufSize: Int = 48, 126 DecodeWidth: Int = 6, 127 RenameWidth: Int = 6, 128 CommitWidth: Int = 6, 129 FtqSize: Int = 64, 130 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 131 IssQueSize: Int = 16, 132 NRPhyRegs: Int = 192, 133 NRIntReadPorts: Int = 14, 134 NRIntWritePorts: Int = 8, 135 NRFpReadPorts: Int = 14, 136 NRFpWritePorts: Int = 8, 137 LoadQueueSize: Int = 80, 138 StoreQueueSize: Int = 64, 139 RobSize: Int = 256, 140 dpParams: DispatchParameters = DispatchParameters( 141 IntDqSize = 16, 142 FpDqSize = 16, 143 LsDqSize = 16, 144 IntDqDeqWidth = 4, 145 FpDqDeqWidth = 4, 146 LsDqDeqWidth = 4 147 ), 148 exuParameters: ExuParameters = ExuParameters( 149 JmpCnt = 1, 150 AluCnt = 4, 151 MulCnt = 0, 152 MduCnt = 2, 153 FmacCnt = 4, 154 FmiscCnt = 2, 155 FmiscDivSqrtCnt = 0, 156 LduCnt = 2, 157 StuCnt = 2 158 ), 159 LoadPipelineWidth: Int = 2, 160 StorePipelineWidth: Int = 2, 161 StoreBufferSize: Int = 16, 162 StoreBufferThreshold: Int = 7, 163 EnableFastForward: Boolean = true, 164 EnableLdVioCheckAfterReset: Boolean = true, 165 RefillSize: Int = 512, 166 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 167 itlbParameters: TLBParameters = TLBParameters( 168 name = "itlb", 169 fetchi = true, 170 useDmode = false, 171 sameCycle = true, 172 normalNWays = 32, 173 normalReplacer = Some("plru"), 174 superNWays = 4, 175 superReplacer = Some("plru"), 176 shouldBlock = true 177 ), 178 ldtlbParameters: TLBParameters = TLBParameters( 179 name = "ldtlb", 180 normalNSets = 128, 181 normalNWays = 1, 182 normalAssociative = "sa", 183 normalReplacer = Some("setplru"), 184 superNWays = 8, 185 normalAsVictim = true, 186 outReplace = true, 187 saveLevel = true 188 ), 189 sttlbParameters: TLBParameters = TLBParameters( 190 name = "sttlb", 191 normalNSets = 128, 192 normalNWays = 1, 193 normalAssociative = "sa", 194 normalReplacer = Some("setplru"), 195 superNWays = 8, 196 normalAsVictim = true, 197 outReplace = true, 198 saveLevel = true 199 ), 200 refillBothTlb: Boolean = false, 201 btlbParameters: TLBParameters = TLBParameters( 202 name = "btlb", 203 normalNSets = 1, 204 normalNWays = 64, 205 superNWays = 4, 206 ), 207 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 208 NumPMP: Int = 16, // 0 or 16 or 64 209 NumPMA: Int = 16, 210 NumPerfCounters: Int = 16, 211 icacheParameters: ICacheParameters = ICacheParameters( 212 tagECC = Some("parity"), 213 dataECC = Some("parity"), 214 replacer = Some("setplru"), 215 nMissEntries = 2 216 ), 217 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 218 tagECC = Some("secded"), 219 dataECC = Some("secded"), 220 replacer = Some("setplru"), 221 nMissEntries = 16, 222 nProbeEntries = 8, 223 nReleaseEntries = 18 224 )), 225 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 226 name = "l2", 227 level = 2, 228 ways = 8, 229 sets = 1024, // default 512KB L2 230 prefetch = Some(huancun.prefetch.BOPParameters()) 231 )), 232 L2NBanks: Int = 1, 233 usePTWRepeater: Boolean = false, 234 softPTW: Boolean = false // dpi-c debug only 235){ 236 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 237 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 238 239 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 240 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 241 242 val fpExuConfigs = 243 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 244 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 245 246 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 247} 248 249case object DebugOptionsKey extends Field[DebugOptions] 250 251case class DebugOptions 252( 253 FPGAPlatform: Boolean = false, 254 EnableDifftest: Boolean = false, 255 AlwaysBasicDiff: Boolean = true, 256 EnableDebug: Boolean = false, 257 EnablePerfDebug: Boolean = true, 258 UseDRAMSim: Boolean = false 259) 260 261trait HasXSParameter { 262 263 implicit val p: Parameters 264 265 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 266 267 val coreParams = p(XSCoreParamsKey) 268 val env = p(DebugOptionsKey) 269 270 val XLEN = coreParams.XLEN 271 val minFLen = 32 272 val fLen = 64 273 def xLen = XLEN 274 275 val HasMExtension = coreParams.HasMExtension 276 val HasCExtension = coreParams.HasCExtension 277 val HasDiv = coreParams.HasDiv 278 val HasIcache = coreParams.HasICache 279 val HasDcache = coreParams.HasDCache 280 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 281 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 282 val AsidLength = coreParams.AsidLength 283 val AddrBytes = AddrBits / 8 // unused 284 val DataBits = XLEN 285 val DataBytes = DataBits / 8 286 val HasFPU = coreParams.HasFPU 287 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 288 val FetchWidth = coreParams.FetchWidth 289 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 290 val EnableBPU = coreParams.EnableBPU 291 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 292 val EnableRAS = coreParams.EnableRAS 293 val EnableLB = coreParams.EnableLB 294 val EnableLoop = coreParams.EnableLoop 295 val EnableSC = coreParams.EnableSC 296 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 297 val HistoryLength = coreParams.HistoryLength 298 val PathHistoryLength = coreParams.PathHistoryLength 299 val BtbSize = coreParams.BtbSize 300 // val BtbWays = 4 301 val BtbBanks = PredictWidth 302 // val BtbSets = BtbSize / BtbWays 303 val JbtacSize = coreParams.JbtacSize 304 val JbtacBanks = coreParams.JbtacBanks 305 val RasSize = coreParams.RasSize 306 307 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 308 coreParams.branchPredictor(resp_in, p) 309 } 310 val numBr = coreParams.numBr 311 val TageTableInfos = coreParams.TageTableInfos 312 313 314 val BankTageTableInfos = (0 until numBr).map(i => 315 TageTableInfos.map{ case (s, h, t) => (s/(1 << i), h, t) } 316 ) 317 val TageBanks = coreParams.TageBanks 318 val SCNRows = coreParams.SCNRows 319 val SCCtrBits = coreParams.SCCtrBits 320 val BankSCHistLens = BankTageTableInfos.map(info => 0 :: info.map{ case (_,h,_) => h}.toList) 321 val BankSCNTables = Seq.fill(numBr)(coreParams.SCNTables) 322 323 val BankSCTableInfos = (BankSCNTables zip BankSCHistLens).map { 324 case (ntable, histlens) => 325 Seq.fill(ntable)((SCNRows, SCCtrBits)) zip histlens map {case ((n, cb), h) => (n, cb, h)} 326 } 327 val ITTageTableInfos = coreParams.ITTageTableInfos 328 type FoldedHistoryInfo = Tuple2[Int, Int] 329 val foldedGHistInfos = 330 (BankTageTableInfos.flatMap(_.map{ case (nRows, h, t) => 331 if (h > 0) 332 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 333 else 334 Set[FoldedHistoryInfo]() 335 }.reduce(_++_)).toSet ++ 336 BankSCTableInfos.flatMap(_.map{ case (nRows, _, h) => 337 if (h > 0) 338 Set((h, min(log2Ceil(nRows/TageBanks), h))) 339 else 340 Set[FoldedHistoryInfo]() 341 }.reduce(_++_)).toSet ++ 342 ITTageTableInfos.map{ case (nRows, h, t) => 343 if (h > 0) 344 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 345 else 346 Set[FoldedHistoryInfo]() 347 }.reduce(_++_)).toList 348 349 val CacheLineSize = coreParams.CacheLineSize 350 val CacheLineHalfWord = CacheLineSize / 16 351 val ExtHistoryLength = HistoryLength + 64 352 val UBtbWays = coreParams.UBtbWays 353 val BtbWays = coreParams.BtbWays 354 val IBufSize = coreParams.IBufSize 355 val DecodeWidth = coreParams.DecodeWidth 356 val RenameWidth = coreParams.RenameWidth 357 val CommitWidth = coreParams.CommitWidth 358 val FtqSize = coreParams.FtqSize 359 val IssQueSize = coreParams.IssQueSize 360 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 361 val NRPhyRegs = coreParams.NRPhyRegs 362 val PhyRegIdxWidth = log2Up(NRPhyRegs) 363 val RobSize = coreParams.RobSize 364 val IntRefCounterWidth = log2Ceil(RobSize) 365 val StdFreeListSize = NRPhyRegs - 32 366 val MEFreeListSize = NRPhyRegs 367 val LoadQueueSize = coreParams.LoadQueueSize 368 val StoreQueueSize = coreParams.StoreQueueSize 369 val dpParams = coreParams.dpParams 370 val exuParameters = coreParams.exuParameters 371 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 372 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 373 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 374 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 375 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 376 val LoadPipelineWidth = coreParams.LoadPipelineWidth 377 val StorePipelineWidth = coreParams.StorePipelineWidth 378 val StoreBufferSize = coreParams.StoreBufferSize 379 val StoreBufferThreshold = coreParams.StoreBufferThreshold 380 val EnableFastForward = coreParams.EnableFastForward 381 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 382 val RefillSize = coreParams.RefillSize 383 val asidLen = coreParams.MMUAsidLen 384 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 385 val refillBothTlb = coreParams.refillBothTlb 386 val itlbParams = coreParams.itlbParameters 387 val ldtlbParams = coreParams.ldtlbParameters 388 val sttlbParams = coreParams.sttlbParameters 389 val btlbParams = coreParams.btlbParameters 390 val l2tlbParams = coreParams.l2tlbParameters 391 val NumPMP = coreParams.NumPMP 392 val NumPMA = coreParams.NumPMA 393 val PlatformGrain: Int = log2Up(coreParams.RefillSize/8) // set PlatformGrain to avoid itlb, dtlb, ptw size conflict 394 val NumPerfCounters = coreParams.NumPerfCounters 395 396 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 397 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 398 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 399 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 400 401 val instBytes = if (HasCExtension) 2 else 4 402 val instOffsetBits = log2Ceil(instBytes) 403 404 val icacheParameters = coreParams.icacheParameters 405 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 406 407 val LRSCCycles = 100 408 409 // cache hierarchy configurations 410 val l1BusDataWidth = 256 411 412 // load violation predict 413 val ResetTimeMax2Pow = 20 //1078576 414 val ResetTimeMin2Pow = 10 //1024 415 // wait table parameters 416 val WaitTableSize = 1024 417 val MemPredPCWidth = log2Up(WaitTableSize) 418 val LWTUse2BitCounter = true 419 // store set parameters 420 val SSITSize = WaitTableSize 421 val LFSTSize = 32 422 val SSIDWidth = log2Up(LFSTSize) 423 val LFSTWidth = 4 424 val StoreSetEnable = true // LWT will be disabled if SS is enabled 425 426 val loadExuConfigs = coreParams.loadExuConfigs 427 val storeExuConfigs = coreParams.storeExuConfigs 428 429 val intExuConfigs = coreParams.intExuConfigs 430 431 val fpExuConfigs = coreParams.fpExuConfigs 432 433 val exuConfigs = coreParams.exuConfigs 434 435 val PCntIncrStep: Int = 6 436 val numPCntHc: Int = 25 437 val numPCntPtw: Int = 19 438 439 val numCSRPCntFrontend = 8 440 val numCSRPCntCtrl = 8 441 val numCSRPCntLsu = 8 442 val numCSRPCntHc = 5 443 val print_perfcounter = false 444} 445