1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import coupledL2.tl2chi._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.{max, min, pow} 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 PAddrBitsMax: Int = 56, // The bits of physical address from Sv39/Sv48/Sv57 virtual address translation. 72 VAddrBitsSv39: Int = 39, 73 GPAddrBitsSv39x4: Int = 41, 74 VAddrBitsSv48: Int = 48, 75 GPAddrBitsSv48x4: Int = 50, 76 HasFPU: Boolean = true, 77 HasVPU: Boolean = true, 78 HasCustomCSRCacheOp: Boolean = true, 79 FetchWidth: Int = 8, 80 AsidLength: Int = 16, 81 VmidLength: Int = 14, 82 EnableBPU: Boolean = true, 83 EnableBPD: Boolean = true, 84 EnableRAS: Boolean = true, 85 EnableLB: Boolean = false, 86 EnableLoop: Boolean = true, 87 EnableSC: Boolean = true, 88 EnbaleTlbDebug: Boolean = false, 89 EnableClockGate: Boolean = true, 90 EnableJal: Boolean = false, 91 EnableFauFTB: Boolean = true, 92 EnableSv48: Boolean = true, 93 UbtbGHRLength: Int = 4, 94 // HistoryLength: Int = 512, 95 EnableGHistDiff: Boolean = true, 96 EnableCommitGHistDiff: Boolean = true, 97 UbtbSize: Int = 256, 98 FtbSize: Int = 2048, 99 FtbWays: Int = 4, 100 FtbTagLength: Int = 20, 101 RasSize: Int = 16, 102 RasSpecSize: Int = 32, 103 RasCtrSize: Int = 3, 104 CacheLineSize: Int = 512, 105 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 106 // Sets Hist Tag 107 Seq(( 4096, 8, 8), 108 ( 4096, 13, 8), 109 ( 4096, 32, 8), 110 ( 4096, 119, 8)), 111 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 112 // Sets Hist Tag 113 Seq(( 256, 4, 9), 114 ( 256, 8, 9), 115 ( 512, 13, 9), 116 ( 512, 16, 9), 117 ( 512, 32, 9)), 118 SCNRows: Int = 512, 119 SCNTables: Int = 4, 120 SCCtrBits: Int = 6, 121 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 122 numBr: Int = 2, 123 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 124 (resp_in: BranchPredictionResp, p: Parameters) => { 125 val ftb = Module(new FTB()(p)) 126 val uftb = Module(new FauFTB()(p)) 127 val tage = Module(new Tage_SC()(p)) 128 val ras = Module(new RAS()(p)) 129 val ittage = Module(new ITTage()(p)) 130 val preds = Seq(uftb, tage, ftb, ittage, ras) 131 preds.map(_.io := DontCare) 132 133 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 134 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 135 136 uftb.io.in.bits.resp_in(0) := resp_in 137 tage.io.in.bits.resp_in(0) := uftb.io.out 138 ftb.io.in.bits.resp_in(0) := tage.io.out 139 ittage.io.in.bits.resp_in(0) := ftb.io.out 140 ras.io.in.bits.resp_in(0) := ittage.io.out 141 142 (preds, ras.io.out) 143 }, 144 ICacheForceMetaECCError: Boolean = false, 145 ICacheForceDataECCError: Boolean = false, 146 IBufSize: Int = 48, 147 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 148 DecodeWidth: Int = 6, 149 RenameWidth: Int = 6, 150 CommitWidth: Int = 8, 151 RobCommitWidth: Int = 8, 152 RabCommitWidth: Int = 6, 153 MaxUopSize: Int = 65, 154 EnableRenameSnapshot: Boolean = true, 155 RenameSnapshotNum: Int = 4, 156 FtqSize: Int = 64, 157 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 158 IntLogicRegs: Int = 32, 159 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 160 VecLogicRegs: Int = 32 + 15, // 15: tmp 161 V0LogicRegs: Int = 1, // V0 162 VlLogicRegs: Int = 1, // Vl 163 V0_IDX: Int = 0, 164 Vl_IDX: Int = 0, 165 NRPhyRegs: Int = 192, 166 VirtualLoadQueueSize: Int = 72, 167 LoadQueueRARSize: Int = 72, 168 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 169 RollbackGroupSize: Int = 8, 170 LoadQueueReplaySize: Int = 72, 171 LoadUncacheBufferSize: Int = 20, 172 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 173 StoreQueueSize: Int = 64, 174 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 175 StoreQueueForwardWithMask: Boolean = true, 176 VlsQueueSize: Int = 8, 177 RobSize: Int = 160, 178 RabSize: Int = 256, 179 VTypeBufferSize: Int = 64, // used to reorder vtype 180 IssueQueueSize: Int = 24, 181 IssueQueueCompEntrySize: Int = 16, 182 dpParams: DispatchParameters = DispatchParameters( 183 IntDqSize = 16, 184 FpDqSize = 16, 185 LsDqSize = 18, 186 IntDqDeqWidth = 8, 187 FpDqDeqWidth = 6, 188 VecDqDeqWidth = 6, 189 LsDqDeqWidth = 6, 190 ), 191 intPreg: PregParams = IntPregParams( 192 numEntries = 224, 193 numRead = None, 194 numWrite = None, 195 ), 196 fpPreg: PregParams = FpPregParams( 197 numEntries = 192, 198 numRead = None, 199 numWrite = None, 200 ), 201 vfPreg: VfPregParams = VfPregParams( 202 numEntries = 128, 203 numRead = None, 204 numWrite = None, 205 ), 206 v0Preg: V0PregParams = V0PregParams( 207 numEntries = 22, 208 numRead = None, 209 numWrite = None, 210 ), 211 vlPreg: VlPregParams = VlPregParams( 212 numEntries = 32, 213 numRead = None, 214 numWrite = None, 215 ), 216 IntRegCacheSize: Int = 16, 217 MemRegCacheSize: Int = 12, 218 intSchdVlWbPort: Int = 0, 219 vfSchdVlWbPort: Int = 1, 220 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 221 IfuRedirectNum: Int = 1, 222 LoadPipelineWidth: Int = 3, 223 StorePipelineWidth: Int = 2, 224 VecLoadPipelineWidth: Int = 2, 225 VecStorePipelineWidth: Int = 2, 226 VecMemSrcInWidth: Int = 2, 227 VecMemInstWbWidth: Int = 1, 228 VecMemDispatchWidth: Int = 1, 229 VecMemDispatchMaxNumber: Int = 16, 230 VecMemUnitStrideMaxFlowNum: Int = 2, 231 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 2, 2, 2, 2, 2), 232 StoreBufferSize: Int = 16, 233 StoreBufferThreshold: Int = 7, 234 EnsbufferWidth: Int = 2, 235 LoadDependencyWidth: Int = 2, 236 // ============ VLSU ============ 237 VlMergeBufferSize: Int = 16, 238 VsMergeBufferSize: Int = 16, 239 UopWritebackWidth: Int = 2, 240 VLUopWritebackWidth: Int = 2, 241 VSUopWritebackWidth: Int = 1, 242 VSegmentBufferSize: Int = 8, 243 VFOFBufferSize: Int = 8, 244 VLFOFWritebackWidth: Int = 1, 245 // ============================== 246 UncacheBufferSize: Int = 4, 247 EnableLoadToLoadForward: Boolean = false, 248 EnableFastForward: Boolean = true, 249 EnableLdVioCheckAfterReset: Boolean = true, 250 EnableSoftPrefetchAfterReset: Boolean = true, 251 EnableCacheErrorAfterReset: Boolean = true, 252 EnableAccurateLoadError: Boolean = false, 253 EnableUncacheWriteOutstanding: Boolean = false, 254 EnableHardwareStoreMisalign: Boolean = true, 255 EnableHardwareLoadMisalign: Boolean = true, 256 EnableStorePrefetchAtIssue: Boolean = false, 257 EnableStorePrefetchAtCommit: Boolean = false, 258 EnableAtCommitMissTrigger: Boolean = true, 259 EnableStorePrefetchSMS: Boolean = false, 260 EnableStorePrefetchSPB: Boolean = false, 261 HasCMO: Boolean = true, 262 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 263 MMUVmidLen: Int = 14, 264 ReSelectLen: Int = 7, // load replay queue replay select counter len 265 iwpuParameters: WPUParameters = WPUParameters( 266 enWPU = false, 267 algoName = "mmru", 268 isICache = true, 269 ), 270 dwpuParameters: WPUParameters = WPUParameters( 271 enWPU = false, 272 algoName = "mmru", 273 enCfPred = false, 274 isICache = false, 275 ), 276 itlbParameters: TLBParameters = TLBParameters( 277 name = "itlb", 278 fetchi = true, 279 useDmode = false, 280 NWays = 48, 281 ), 282 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 283 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 284 ldtlbParameters: TLBParameters = TLBParameters( 285 name = "ldtlb", 286 NWays = 48, 287 outReplace = false, 288 partialStaticPMP = true, 289 outsideRecvFlush = true, 290 saveLevel = false, 291 lgMaxSize = 4 292 ), 293 sttlbParameters: TLBParameters = TLBParameters( 294 name = "sttlb", 295 NWays = 48, 296 outReplace = false, 297 partialStaticPMP = true, 298 outsideRecvFlush = true, 299 saveLevel = false, 300 lgMaxSize = 4 301 ), 302 hytlbParameters: TLBParameters = TLBParameters( 303 name = "hytlb", 304 NWays = 48, 305 outReplace = false, 306 partialStaticPMP = true, 307 outsideRecvFlush = true, 308 saveLevel = false, 309 lgMaxSize = 4 310 ), 311 pftlbParameters: TLBParameters = TLBParameters( 312 name = "pftlb", 313 NWays = 48, 314 outReplace = false, 315 partialStaticPMP = true, 316 outsideRecvFlush = true, 317 saveLevel = false, 318 lgMaxSize = 4 319 ), 320 l2ToL1tlbParameters: TLBParameters = TLBParameters( 321 name = "l2tlb", 322 NWays = 48, 323 outReplace = false, 324 partialStaticPMP = true, 325 outsideRecvFlush = true, 326 saveLevel = false 327 ), 328 refillBothTlb: Boolean = false, 329 btlbParameters: TLBParameters = TLBParameters( 330 name = "btlb", 331 NWays = 48, 332 ), 333 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 334 NumPerfCounters: Int = 16, 335 icacheParameters: ICacheParameters = ICacheParameters( 336 tagECC = Some("parity"), 337 dataECC = Some("parity"), 338 replacer = Some("setplru"), 339 ), 340 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 341 tagECC = Some("secded"), 342 dataECC = Some("secded"), 343 replacer = Some("setplru"), 344 nMissEntries = 16, 345 nProbeEntries = 8, 346 nReleaseEntries = 18, 347 nMaxPrefetchEntry = 6, 348 )), 349 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 350 name = "l2", 351 ways = 8, 352 sets = 1024, // default 512KB L2 353 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 354 coupledL2.prefetch.TPParameters()), 355 )), 356 L2NBanks: Int = 1, 357 usePTWRepeater: Boolean = false, 358 softTLB: Boolean = false, // dpi-c l1tlb debug only 359 softPTW: Boolean = false, // dpi-c l2tlb debug only 360 softPTWDelay: Int = 1 361){ 362 def vlWidth = log2Up(VLEN) + 1 363 364 /** 365 * the minimum element length of vector elements 366 */ 367 val minVecElen: Int = 8 368 369 /** 370 * the maximum number of elements in vector register 371 */ 372 val maxElemPerVreg: Int = VLEN / minVecElen 373 374 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 375 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 376 377 val RegCacheSize = IntRegCacheSize + MemRegCacheSize 378 val RegCacheIdxWidth = log2Up(RegCacheSize) 379 380 val intSchdParams = { 381 implicit val schdType: SchedulerType = IntScheduler() 382 SchdBlockParams(Seq( 383 IssueBlockParams(Seq( 384 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 385 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1))), true, 2), 386 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 387 IssueBlockParams(Seq( 388 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 389 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1))), true, 2), 390 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 391 IssueBlockParams(Seq( 392 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 393 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = intSchdVlWbPort, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 394 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 395 IssueBlockParams(Seq( 396 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 397 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 398 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 399 ), 400 numPregs = intPreg.numEntries, 401 numDeqOutside = 0, 402 schdType = schdType, 403 rfDataWidth = intPreg.dataCfg.dataWidth, 404 numUopIn = dpParams.IntDqDeqWidth, 405 ) 406 } 407 408 val fpSchdParams = { 409 implicit val schdType: SchedulerType = FpScheduler() 410 SchdBlockParams(Seq( 411 IssueBlockParams(Seq( 412 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 413 ), numEntries = 18, numEnq = 2, numComp = 16), 414 IssueBlockParams(Seq( 415 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 416 ), numEntries = 18, numEnq = 2, numComp = 16), 417 IssueBlockParams(Seq( 418 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 419 ), numEntries = 18, numEnq = 2, numComp = 16), 420 IssueBlockParams(Seq( 421 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 422 ), numEntries = 18, numEnq = 2, numComp = 16), 423 IssueBlockParams(Seq( 424 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 425 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 426 ), numEntries = 18, numEnq = 2, numComp = 16), 427 ), 428 numPregs = fpPreg.numEntries, 429 numDeqOutside = 0, 430 schdType = schdType, 431 rfDataWidth = fpPreg.dataCfg.dataWidth, 432 numUopIn = dpParams.FpDqDeqWidth, 433 ) 434 } 435 436 val vfSchdParams = { 437 implicit val schdType: SchedulerType = VfScheduler() 438 SchdBlockParams(Seq( 439 IssueBlockParams(Seq( 440 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 441 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = vfSchdVlWbPort, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 442 ), numEntries = 16, numEnq = 2, numComp = 14), 443 IssueBlockParams(Seq( 444 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 445 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 446 ), numEntries = 16, numEnq = 2, numComp = 14), 447 IssueBlockParams(Seq( 448 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 449 ), numEntries = 10, numEnq = 2, numComp = 8), 450 ), 451 numPregs = vfPreg.numEntries, 452 numDeqOutside = 0, 453 schdType = schdType, 454 rfDataWidth = vfPreg.dataCfg.dataWidth, 455 numUopIn = dpParams.VecDqDeqWidth, 456 ) 457 } 458 459 val memSchdParams = { 460 implicit val schdType: SchedulerType = MemScheduler() 461 val rfDataWidth = 64 462 463 SchdBlockParams(Seq( 464 IssueBlockParams(Seq( 465 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))), 466 ), numEntries = 16, numEnq = 1, numComp = 15), 467 IssueBlockParams(Seq( 468 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))), 469 ), numEntries = 16, numEnq = 1, numComp = 15), 470 IssueBlockParams(Seq( 471 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(8, 0))), true, 2), 472 ), numEntries = 16, numEnq = 1, numComp = 15), 473 IssueBlockParams(Seq( 474 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(9, 0))), true, 2), 475 ), numEntries = 16, numEnq = 1, numComp = 15), 476 IssueBlockParams(Seq( 477 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(10, 0))), true, 2), 478 ), numEntries = 16, numEnq = 1, numComp = 15), 479 IssueBlockParams(Seq( 480 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0), VlWB(port = 2, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 481 ), numEntries = 16, numEnq = 1, numComp = 15), 482 IssueBlockParams(Seq( 483 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0), VlWB(port = 3, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 484 ), numEntries = 16, numEnq = 1, numComp = 15), 485 IssueBlockParams(Seq( 486 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(12, 0)))), 487 ), numEntries = 16, numEnq = 1, numComp = 15), 488 IssueBlockParams(Seq( 489 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(13, 0)))), 490 ), numEntries = 16, numEnq = 1, numComp = 15), 491 ), 492 numPregs = intPreg.numEntries max vfPreg.numEntries, 493 numDeqOutside = 0, 494 schdType = schdType, 495 rfDataWidth = rfDataWidth, 496 numUopIn = dpParams.LsDqDeqWidth, 497 ) 498 } 499 500 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 501 502 def iqWakeUpParams = { 503 Seq( 504 WakeUpConfig( 505 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 506 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 507 ), 508 // TODO: add load -> fp slow wakeup 509 WakeUpConfig( 510 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 511 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 512 ), 513 WakeUpConfig( 514 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 515 Seq("STD0", "STD1") 516 ), 517// WakeUpConfig( 518// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 519// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") 520// ), 521 ).flatten 522 } 523 524 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 525 526 val backendParams: BackendParams = backend.BackendParams( 527 Map( 528 IntScheduler() -> intSchdParams, 529 FpScheduler() -> fpSchdParams, 530 VfScheduler() -> vfSchdParams, 531 MemScheduler() -> memSchdParams, 532 ), 533 Seq( 534 intPreg, 535 fpPreg, 536 vfPreg, 537 v0Preg, 538 vlPreg, 539 fakeIntPreg 540 ), 541 iqWakeUpParams, 542 ) 543 544 // Parameters for trace extension. 545 // Trace parameters is useful for XSTOP. 546 val TraceGroupNum = 3 // Width to Encoder 547} 548 549case object DebugOptionsKey extends Field[DebugOptions] 550 551case class DebugOptions 552( 553 FPGAPlatform: Boolean = false, 554 ResetGen: Boolean = false, 555 EnableDifftest: Boolean = false, 556 AlwaysBasicDiff: Boolean = true, 557 EnableDebug: Boolean = false, 558 EnablePerfDebug: Boolean = true, 559 UseDRAMSim: Boolean = false, 560 EnableConstantin: Boolean = false, 561 EnableChiselDB: Boolean = false, 562 AlwaysBasicDB: Boolean = true, 563 EnableRollingDB: Boolean = false 564) 565 566trait HasXSParameter { 567 568 implicit val p: Parameters 569 570 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 571 def PmemRanges = p(SoCParamsKey).PmemRanges 572 def PmemLowBounds = PmemRanges.unzip._1 573 def PmemHighBounds = PmemRanges.unzip._2 574 final val PageOffsetWidth = 12 575 def NodeIDWidth = p(SoCParamsKey).NodeIDWidthList(p(CHIIssue)) // NodeID width among NoC 576 577 def coreParams = p(XSCoreParamsKey) 578 def env = p(DebugOptionsKey) 579 580 def XLEN = coreParams.XLEN 581 def VLEN = coreParams.VLEN 582 def ELEN = coreParams.ELEN 583 def HSXLEN = coreParams.HSXLEN 584 val minFLen = 32 585 val fLen = 64 586 def hartIdLen = p(MaxHartIdBits) 587 val xLen = XLEN 588 589 def HasMExtension = coreParams.HasMExtension 590 def HasCExtension = coreParams.HasCExtension 591 def HasHExtension = coreParams.HasHExtension 592 def EnableSv48 = coreParams.EnableSv48 593 def HasDiv = coreParams.HasDiv 594 def HasIcache = coreParams.HasICache 595 def HasDcache = coreParams.HasDCache 596 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 597 def PAddrBitsMax = coreParams.PAddrBitsMax 598 def GPAddrBitsSv39x4 = coreParams.GPAddrBitsSv39x4 599 def GPAddrBitsSv48x4 = coreParams.GPAddrBitsSv48x4 600 def GPAddrBits = { 601 if (EnableSv48) 602 coreParams.GPAddrBitsSv48x4 603 else 604 coreParams.GPAddrBitsSv39x4 605 } 606 def VAddrBits = { 607 if (HasHExtension) { 608 if (EnableSv48) 609 coreParams.GPAddrBitsSv48x4 610 else 611 coreParams.GPAddrBitsSv39x4 612 } else { 613 if (EnableSv48) 614 coreParams.VAddrBitsSv48 615 else 616 coreParams.VAddrBitsSv39 617 } 618 } // VAddrBits is Virtual Memory addr bits 619 620 def VAddrMaxBits = { 621 if(EnableSv48) { 622 coreParams.VAddrBitsSv48 max coreParams.GPAddrBitsSv48x4 623 } else { 624 coreParams.VAddrBitsSv39 max coreParams.GPAddrBitsSv39x4 625 } 626 } 627 628 def AsidLength = coreParams.AsidLength 629 def VmidLength = coreParams.VmidLength 630 def ReSelectLen = coreParams.ReSelectLen 631 def AddrBytes = AddrBits / 8 // unused 632 def DataBits = XLEN 633 def DataBytes = DataBits / 8 634 def VDataBytes = VLEN / 8 635 def HasFPU = coreParams.HasFPU 636 def HasVPU = coreParams.HasVPU 637 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 638 def FetchWidth = coreParams.FetchWidth 639 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 640 def EnableBPU = coreParams.EnableBPU 641 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 642 def EnableRAS = coreParams.EnableRAS 643 def EnableLB = coreParams.EnableLB 644 def EnableLoop = coreParams.EnableLoop 645 def EnableSC = coreParams.EnableSC 646 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 647 def HistoryLength = coreParams.HistoryLength 648 def EnableGHistDiff = coreParams.EnableGHistDiff 649 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 650 def EnableClockGate = coreParams.EnableClockGate 651 def UbtbGHRLength = coreParams.UbtbGHRLength 652 def UbtbSize = coreParams.UbtbSize 653 def EnableFauFTB = coreParams.EnableFauFTB 654 def FtbSize = coreParams.FtbSize 655 def FtbWays = coreParams.FtbWays 656 def FtbTagLength = coreParams.FtbTagLength 657 def RasSize = coreParams.RasSize 658 def RasSpecSize = coreParams.RasSpecSize 659 def RasCtrSize = coreParams.RasCtrSize 660 661 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 662 coreParams.branchPredictor(resp_in, p) 663 } 664 def numBr = coreParams.numBr 665 def TageTableInfos = coreParams.TageTableInfos 666 def TageBanks = coreParams.numBr 667 def SCNRows = coreParams.SCNRows 668 def SCCtrBits = coreParams.SCCtrBits 669 def SCHistLens = coreParams.SCHistLens 670 def SCNTables = coreParams.SCNTables 671 672 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 673 case ((n, cb), h) => (n, cb, h) 674 } 675 def ITTageTableInfos = coreParams.ITTageTableInfos 676 type FoldedHistoryInfo = Tuple2[Int, Int] 677 def foldedGHistInfos = 678 (TageTableInfos.map{ case (nRows, h, t) => 679 if (h > 0) 680 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 681 else 682 Set[FoldedHistoryInfo]() 683 }.reduce(_++_).toSet ++ 684 SCTableInfos.map{ case (nRows, _, h) => 685 if (h > 0) 686 Set((h, min(log2Ceil(nRows/TageBanks), h))) 687 else 688 Set[FoldedHistoryInfo]() 689 }.reduce(_++_).toSet ++ 690 ITTageTableInfos.map{ case (nRows, h, t) => 691 if (h > 0) 692 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 693 else 694 Set[FoldedHistoryInfo]() 695 }.reduce(_++_) ++ 696 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 697 ).toList 698 699 700 701 def CacheLineSize = coreParams.CacheLineSize 702 def CacheLineHalfWord = CacheLineSize / 16 703 def ExtHistoryLength = HistoryLength + 64 704 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 705 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 706 def IBufSize = coreParams.IBufSize 707 def IBufNBank = coreParams.IBufNBank 708 def backendParams: BackendParams = coreParams.backendParams 709 def DecodeWidth = coreParams.DecodeWidth 710 def RenameWidth = coreParams.RenameWidth 711 def CommitWidth = coreParams.CommitWidth 712 def RobCommitWidth = coreParams.RobCommitWidth 713 def RabCommitWidth = coreParams.RabCommitWidth 714 def MaxUopSize = coreParams.MaxUopSize 715 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 716 def RenameSnapshotNum = coreParams.RenameSnapshotNum 717 def FtqSize = coreParams.FtqSize 718 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 719 def IntLogicRegs = coreParams.IntLogicRegs 720 def FpLogicRegs = coreParams.FpLogicRegs 721 def VecLogicRegs = coreParams.VecLogicRegs 722 def V0LogicRegs = coreParams.V0LogicRegs 723 def VlLogicRegs = coreParams.VlLogicRegs 724 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 725 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 726 def V0_IDX = coreParams.V0_IDX 727 def Vl_IDX = coreParams.Vl_IDX 728 def IntPhyRegs = coreParams.intPreg.numEntries 729 def FpPhyRegs = coreParams.fpPreg.numEntries 730 def VfPhyRegs = coreParams.vfPreg.numEntries 731 def V0PhyRegs = coreParams.v0Preg.numEntries 732 def VlPhyRegs = coreParams.vlPreg.numEntries 733 def MaxPhyRegs = Seq(IntPhyRegs, FpPhyRegs, VfPhyRegs, V0PhyRegs, VlPhyRegs).max 734 def IntPhyRegIdxWidth = log2Up(IntPhyRegs) 735 def FpPhyRegIdxWidth = log2Up(FpPhyRegs) 736 def VfPhyRegIdxWidth = log2Up(VfPhyRegs) 737 def V0PhyRegIdxWidth = log2Up(V0PhyRegs) 738 def VlPhyRegIdxWidth = log2Up(VlPhyRegs) 739 def PhyRegIdxWidth = Seq(IntPhyRegIdxWidth, FpPhyRegIdxWidth, VfPhyRegIdxWidth, V0PhyRegIdxWidth, VlPhyRegIdxWidth).max 740 def RobSize = coreParams.RobSize 741 def RabSize = coreParams.RabSize 742 def VTypeBufferSize = coreParams.VTypeBufferSize 743 def IntRegCacheSize = coreParams.IntRegCacheSize 744 def MemRegCacheSize = coreParams.MemRegCacheSize 745 def RegCacheSize = coreParams.RegCacheSize 746 def RegCacheIdxWidth = coreParams.RegCacheIdxWidth 747 /** 748 * the minimum element length of vector elements 749 */ 750 def minVecElen: Int = coreParams.minVecElen 751 752 /** 753 * the maximum number of elements in vector register 754 */ 755 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 756 757 def IntRefCounterWidth = log2Ceil(RobSize) 758 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 759 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 760 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 761 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 762 def LoadQueueRARSize = coreParams.LoadQueueRARSize 763 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 764 def RollbackGroupSize = coreParams.RollbackGroupSize 765 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 766 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 767 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 768 def StoreQueueSize = coreParams.StoreQueueSize 769 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 770 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 771 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 772 def VlsQueueSize = coreParams.VlsQueueSize 773 def dpParams = coreParams.dpParams 774 775 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 776 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 777 778 def NumRedirect = backendParams.numRedirect 779 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 780 def FtqRedirectAheadNum = NumRedirect 781 def IfuRedirectNum = coreParams.IfuRedirectNum 782 def LoadPipelineWidth = coreParams.LoadPipelineWidth 783 def StorePipelineWidth = coreParams.StorePipelineWidth 784 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 785 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 786 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 787 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 788 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 789 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 790 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 791 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 792 def StoreBufferSize = coreParams.StoreBufferSize 793 def StoreBufferThreshold = coreParams.StoreBufferThreshold 794 def EnsbufferWidth = coreParams.EnsbufferWidth 795 def LoadDependencyWidth = coreParams.LoadDependencyWidth 796 def VlMergeBufferSize = coreParams.VlMergeBufferSize 797 def VsMergeBufferSize = coreParams.VsMergeBufferSize 798 def UopWritebackWidth = coreParams.UopWritebackWidth 799 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 800 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 801 def VSegmentBufferSize = coreParams.VSegmentBufferSize 802 def VFOFBufferSize = coreParams.VFOFBufferSize 803 def UncacheBufferSize = coreParams.UncacheBufferSize 804 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 805 def EnableFastForward = coreParams.EnableFastForward 806 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 807 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 808 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 809 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 810 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 811 def EnableHardwareStoreMisalign = coreParams.EnableHardwareStoreMisalign 812 def EnableHardwareLoadMisalign = coreParams.EnableHardwareLoadMisalign 813 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 814 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 815 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 816 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 817 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 818 def HasCMO = coreParams.HasCMO && p(EnableCHI) 819 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 820 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 821 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 822 def asidLen = coreParams.MMUAsidLen 823 def vmidLen = coreParams.MMUVmidLen 824 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 825 def refillBothTlb = coreParams.refillBothTlb 826 def iwpuParam = coreParams.iwpuParameters 827 def dwpuParam = coreParams.dwpuParameters 828 def itlbParams = coreParams.itlbParameters 829 def ldtlbParams = coreParams.ldtlbParameters 830 def sttlbParams = coreParams.sttlbParameters 831 def hytlbParams = coreParams.hytlbParameters 832 def pftlbParams = coreParams.pftlbParameters 833 def l2ToL1Params = coreParams.l2ToL1tlbParameters 834 def btlbParams = coreParams.btlbParameters 835 def l2tlbParams = coreParams.l2tlbParameters 836 def NumPerfCounters = coreParams.NumPerfCounters 837 838 def instBytes = if (HasCExtension) 2 else 4 839 def instOffsetBits = log2Ceil(instBytes) 840 841 def icacheParameters = coreParams.icacheParameters 842 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 843 844 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 845 // for constrained LR/SC loop 846 def LRSCCycles = 64 847 // for lr storm 848 def LRSCBackOff = 8 849 850 // cache hierarchy configurations 851 def l1BusDataWidth = 256 852 853 // load violation predict 854 def ResetTimeMax2Pow = 20 //1078576 855 def ResetTimeMin2Pow = 10 //1024 856 // wait table parameters 857 def WaitTableSize = 1024 858 def MemPredPCWidth = log2Up(WaitTableSize) 859 def LWTUse2BitCounter = true 860 // store set parameters 861 def SSITSize = WaitTableSize 862 def LFSTSize = 32 863 def SSIDWidth = log2Up(LFSTSize) 864 def LFSTWidth = 4 865 def StoreSetEnable = true // LWT will be disabled if SS is enabled 866 def LFSTEnable = true 867 868 def PCntIncrStep: Int = 6 869 def numPCntHc: Int = 12 870 def numPCntPtw: Int = 19 871 872 def numCSRPCntFrontend = 8 873 def numCSRPCntCtrl = 8 874 def numCSRPCntLsu = 8 875 def numCSRPCntHc = 5 876 def printEventCoding = true 877 def printCriticalError = false 878 def maxCommitStuck = pow(2, 21).toInt 879 880 // Vector load exception 881 def maxMergeNumPerCycle = 4 882 883 // Parameters for Sdtrig extension 884 protected def TriggerNum = 4 885 protected def TriggerChainMaxLength = 2 886 887 // Parameters for Trace extension 888 def TraceGroupNum = coreParams.TraceGroupNum 889} 890