1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import coupledL2.tl2chi._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.{max, min, pow} 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 PAddrBitsMax: Int = 56, // The bits of physical address from Sv39/Sv48/Sv57 virtual address translation. 72 VAddrBitsSv39: Int = 39, 73 GPAddrBitsSv39x4: Int = 41, 74 VAddrBitsSv48: Int = 48, 75 GPAddrBitsSv48x4: Int = 50, 76 HasFPU: Boolean = true, 77 HasVPU: Boolean = true, 78 HasCustomCSRCacheOp: Boolean = true, 79 FetchWidth: Int = 8, 80 AsidLength: Int = 16, 81 VmidLength: Int = 14, 82 EnableBPU: Boolean = true, 83 EnableBPD: Boolean = true, 84 EnableRAS: Boolean = true, 85 EnableLB: Boolean = false, 86 EnableLoop: Boolean = true, 87 EnableSC: Boolean = true, 88 EnbaleTlbDebug: Boolean = false, 89 EnableClockGate: Boolean = true, 90 EnableJal: Boolean = false, 91 EnableFauFTB: Boolean = true, 92 EnableSv48: Boolean = true, 93 UbtbGHRLength: Int = 4, 94 // HistoryLength: Int = 512, 95 EnableGHistDiff: Boolean = true, 96 EnableCommitGHistDiff: Boolean = true, 97 UbtbSize: Int = 256, 98 FtbSize: Int = 2048, 99 FtbWays: Int = 4, 100 FtbTagLength: Int = 20, 101 RasSize: Int = 16, 102 RasSpecSize: Int = 32, 103 RasCtrSize: Int = 3, 104 CacheLineSize: Int = 512, 105 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 106 // Sets Hist Tag 107 Seq(( 4096, 8, 8), 108 ( 4096, 13, 8), 109 ( 4096, 32, 8), 110 ( 4096, 119, 8)), 111 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 112 // Sets Hist Tag 113 Seq(( 256, 4, 9), 114 ( 256, 8, 9), 115 ( 512, 13, 9), 116 ( 512, 16, 9), 117 ( 512, 32, 9)), 118 SCNRows: Int = 512, 119 SCNTables: Int = 4, 120 SCCtrBits: Int = 6, 121 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 122 numBr: Int = 2, 123 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 124 (resp_in: BranchPredictionResp, p: Parameters) => { 125 val ftb = Module(new FTB()(p)) 126 val uftb = Module(new FauFTB()(p)) 127 val tage = Module(new Tage_SC()(p)) 128 val ras = Module(new RAS()(p)) 129 val ittage = Module(new ITTage()(p)) 130 val preds = Seq(uftb, tage, ftb, ittage, ras) 131 preds.map(_.io := DontCare) 132 133 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 134 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 135 136 uftb.io.in.bits.resp_in(0) := resp_in 137 tage.io.in.bits.resp_in(0) := uftb.io.out 138 ftb.io.in.bits.resp_in(0) := tage.io.out 139 ittage.io.in.bits.resp_in(0) := ftb.io.out 140 ras.io.in.bits.resp_in(0) := ittage.io.out 141 142 (preds, ras.io.out) 143 }, 144 ICacheForceMetaECCError: Boolean = false, 145 ICacheForceDataECCError: Boolean = false, 146 IBufSize: Int = 48, 147 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 148 DecodeWidth: Int = 6, 149 RenameWidth: Int = 6, 150 CommitWidth: Int = 8, 151 RobCommitWidth: Int = 8, 152 RabCommitWidth: Int = 6, 153 MaxUopSize: Int = 65, 154 EnableRenameSnapshot: Boolean = true, 155 RenameSnapshotNum: Int = 4, 156 FtqSize: Int = 64, 157 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 158 IntLogicRegs: Int = 32, 159 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 160 VecLogicRegs: Int = 32 + 15, // 15: tmp 161 V0LogicRegs: Int = 1, // V0 162 VlLogicRegs: Int = 1, // Vl 163 V0_IDX: Int = 0, 164 Vl_IDX: Int = 0, 165 NRPhyRegs: Int = 192, 166 VirtualLoadQueueSize: Int = 72, 167 LoadQueueRARSize: Int = 72, 168 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 169 RollbackGroupSize: Int = 8, 170 LoadQueueReplaySize: Int = 72, 171 LoadUncacheBufferSize: Int = 20, 172 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 173 StoreQueueSize: Int = 64, 174 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 175 StoreQueueForwardWithMask: Boolean = true, 176 VlsQueueSize: Int = 8, 177 RobSize: Int = 160, 178 RabSize: Int = 256, 179 VTypeBufferSize: Int = 64, // used to reorder vtype 180 IssueQueueSize: Int = 24, 181 IssueQueueCompEntrySize: Int = 16, 182 dpParams: DispatchParameters = DispatchParameters( 183 IntDqSize = 16, 184 FpDqSize = 16, 185 LsDqSize = 18, 186 IntDqDeqWidth = 8, 187 FpDqDeqWidth = 6, 188 VecDqDeqWidth = 6, 189 LsDqDeqWidth = 6, 190 ), 191 intPreg: PregParams = IntPregParams( 192 numEntries = 224, 193 numRead = None, 194 numWrite = None, 195 ), 196 fpPreg: PregParams = FpPregParams( 197 numEntries = 192, 198 numRead = None, 199 numWrite = None, 200 ), 201 vfPreg: VfPregParams = VfPregParams( 202 numEntries = 128, 203 numRead = None, 204 numWrite = None, 205 ), 206 v0Preg: V0PregParams = V0PregParams( 207 numEntries = 22, 208 numRead = None, 209 numWrite = None, 210 ), 211 vlPreg: VlPregParams = VlPregParams( 212 numEntries = 32, 213 numRead = None, 214 numWrite = None, 215 ), 216 IntRegCacheSize: Int = 16, 217 MemRegCacheSize: Int = 12, 218 intSchdVlWbPort: Int = 0, 219 vfSchdVlWbPort: Int = 1, 220 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 221 IfuRedirectNum: Int = 1, 222 LoadPipelineWidth: Int = 3, 223 StorePipelineWidth: Int = 2, 224 VecLoadPipelineWidth: Int = 2, 225 VecStorePipelineWidth: Int = 2, 226 VecMemSrcInWidth: Int = 2, 227 VecMemInstWbWidth: Int = 1, 228 VecMemDispatchWidth: Int = 1, 229 VecMemDispatchMaxNumber: Int = 16, 230 VecMemUnitStrideMaxFlowNum: Int = 2, 231 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 2, 2, 2, 2, 2), 232 StoreBufferSize: Int = 16, 233 StoreBufferThreshold: Int = 7, 234 EnsbufferWidth: Int = 2, 235 LoadDependencyWidth: Int = 2, 236 // ============ VLSU ============ 237 VlMergeBufferSize: Int = 16, 238 VsMergeBufferSize: Int = 16, 239 UopWritebackWidth: Int = 2, 240 VLUopWritebackWidth: Int = 2, 241 VSUopWritebackWidth: Int = 1, 242 VSegmentBufferSize: Int = 8, 243 VFOFBufferSize: Int = 8, 244 VLFOFWritebackWidth: Int = 1, 245 // ============================== 246 UncacheBufferSize: Int = 4, 247 EnableLoadToLoadForward: Boolean = false, 248 EnableFastForward: Boolean = true, 249 EnableLdVioCheckAfterReset: Boolean = true, 250 EnableSoftPrefetchAfterReset: Boolean = true, 251 EnableCacheErrorAfterReset: Boolean = true, 252 EnableAccurateLoadError: Boolean = false, 253 EnableUncacheWriteOutstanding: Boolean = false, 254 EnableHardwareStoreMisalign: Boolean = true, 255 EnableHardwareLoadMisalign: Boolean = true, 256 EnableStorePrefetchAtIssue: Boolean = false, 257 EnableStorePrefetchAtCommit: Boolean = false, 258 EnableAtCommitMissTrigger: Boolean = true, 259 EnableStorePrefetchSMS: Boolean = false, 260 EnableStorePrefetchSPB: Boolean = false, 261 HasCMO: Boolean = true, 262 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 263 MMUVmidLen: Int = 14, 264 ReSelectLen: Int = 7, // load replay queue replay select counter len 265 iwpuParameters: WPUParameters = WPUParameters( 266 enWPU = false, 267 algoName = "mmru", 268 isICache = true, 269 ), 270 dwpuParameters: WPUParameters = WPUParameters( 271 enWPU = false, 272 algoName = "mmru", 273 enCfPred = false, 274 isICache = false, 275 ), 276 itlbParameters: TLBParameters = TLBParameters( 277 name = "itlb", 278 fetchi = true, 279 useDmode = false, 280 NWays = 48, 281 ), 282 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 283 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 284 ldtlbParameters: TLBParameters = TLBParameters( 285 name = "ldtlb", 286 NWays = 48, 287 outReplace = false, 288 partialStaticPMP = true, 289 outsideRecvFlush = true, 290 saveLevel = false, 291 lgMaxSize = 4 292 ), 293 sttlbParameters: TLBParameters = TLBParameters( 294 name = "sttlb", 295 NWays = 48, 296 outReplace = false, 297 partialStaticPMP = true, 298 outsideRecvFlush = true, 299 saveLevel = false, 300 lgMaxSize = 4 301 ), 302 hytlbParameters: TLBParameters = TLBParameters( 303 name = "hytlb", 304 NWays = 48, 305 outReplace = false, 306 partialStaticPMP = true, 307 outsideRecvFlush = true, 308 saveLevel = false, 309 lgMaxSize = 4 310 ), 311 pftlbParameters: TLBParameters = TLBParameters( 312 name = "pftlb", 313 NWays = 48, 314 outReplace = false, 315 partialStaticPMP = true, 316 outsideRecvFlush = true, 317 saveLevel = false, 318 lgMaxSize = 4 319 ), 320 l2ToL1tlbParameters: TLBParameters = TLBParameters( 321 name = "l2tlb", 322 NWays = 48, 323 outReplace = false, 324 partialStaticPMP = true, 325 outsideRecvFlush = true, 326 saveLevel = false 327 ), 328 refillBothTlb: Boolean = false, 329 btlbParameters: TLBParameters = TLBParameters( 330 name = "btlb", 331 NWays = 48, 332 ), 333 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 334 NumPerfCounters: Int = 16, 335 icacheParameters: ICacheParameters = ICacheParameters( 336 tagECC = Some("parity"), 337 dataECC = Some("parity"), 338 replacer = Some("setplru"), 339 ), 340 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 341 tagECC = Some("secded"), 342 dataECC = Some("secded"), 343 replacer = Some("setplru"), 344 nMissEntries = 16, 345 nProbeEntries = 8, 346 nReleaseEntries = 18, 347 nMaxPrefetchEntry = 6, 348 enableTagEcc = true, 349 enableDataEcc = true 350 )), 351 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 352 name = "l2", 353 ways = 8, 354 sets = 1024, // default 512KB L2 355 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 356 coupledL2.prefetch.TPParameters()), 357 )), 358 L2NBanks: Int = 1, 359 usePTWRepeater: Boolean = false, 360 softTLB: Boolean = false, // dpi-c l1tlb debug only 361 softPTW: Boolean = false, // dpi-c l2tlb debug only 362 softPTWDelay: Int = 1 363){ 364 def ISABase = "rv64i" 365 def ISAExtensions = Seq( 366 // single letter extensions, in canonical order 367 "i", "m", "a", "f", "d", "c", /* "b", */ "v", "h", 368 // multi-letter extensions, sorted alphanumerically 369 "sdtrig", "sha", "shcounterenw", "shgatpa", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", 370 "smaia", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "ssstateen", 371 "sstc", "sstvala", "sstvecd", "ssu64xl", "sv39", "sv48", "svade", "svbare", "svinval", 372 "svpbmt", "za64rs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", 373 "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", "ziccif", "zicclsm", 374 "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zimop", "zkn", 375 "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", 376 "zvl128b", "zvl32b", "zvl64b" 377 ) 378 379 def vlWidth = log2Up(VLEN) + 1 380 381 /** 382 * the minimum element length of vector elements 383 */ 384 val minVecElen: Int = 8 385 386 /** 387 * the maximum number of elements in vector register 388 */ 389 val maxElemPerVreg: Int = VLEN / minVecElen 390 391 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 392 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 393 394 val RegCacheSize = IntRegCacheSize + MemRegCacheSize 395 val RegCacheIdxWidth = log2Up(RegCacheSize) 396 397 val intSchdParams = { 398 implicit val schdType: SchedulerType = IntScheduler() 399 SchdBlockParams(Seq( 400 IssueBlockParams(Seq( 401 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 402 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1))), true, 2), 403 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 404 IssueBlockParams(Seq( 405 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 406 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1))), true, 2), 407 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 408 IssueBlockParams(Seq( 409 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 410 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = intSchdVlWbPort, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 411 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 412 IssueBlockParams(Seq( 413 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 414 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 415 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 416 ), 417 numPregs = intPreg.numEntries, 418 numDeqOutside = 0, 419 schdType = schdType, 420 rfDataWidth = intPreg.dataCfg.dataWidth, 421 numUopIn = dpParams.IntDqDeqWidth, 422 ) 423 } 424 425 val fpSchdParams = { 426 implicit val schdType: SchedulerType = FpScheduler() 427 SchdBlockParams(Seq( 428 IssueBlockParams(Seq( 429 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 430 ), numEntries = 18, numEnq = 2, numComp = 16), 431 IssueBlockParams(Seq( 432 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 433 ), numEntries = 18, numEnq = 2, numComp = 16), 434 IssueBlockParams(Seq( 435 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 436 ), numEntries = 18, numEnq = 2, numComp = 16), 437 IssueBlockParams(Seq( 438 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 439 ), numEntries = 18, numEnq = 2, numComp = 16), 440 IssueBlockParams(Seq( 441 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 442 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 443 ), numEntries = 18, numEnq = 2, numComp = 16), 444 ), 445 numPregs = fpPreg.numEntries, 446 numDeqOutside = 0, 447 schdType = schdType, 448 rfDataWidth = fpPreg.dataCfg.dataWidth, 449 numUopIn = dpParams.FpDqDeqWidth, 450 ) 451 } 452 453 val vfSchdParams = { 454 implicit val schdType: SchedulerType = VfScheduler() 455 SchdBlockParams(Seq( 456 IssueBlockParams(Seq( 457 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 458 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = vfSchdVlWbPort, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 459 ), numEntries = 16, numEnq = 2, numComp = 14), 460 IssueBlockParams(Seq( 461 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 462 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 463 ), numEntries = 16, numEnq = 2, numComp = 14), 464 IssueBlockParams(Seq( 465 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 466 ), numEntries = 10, numEnq = 2, numComp = 8), 467 ), 468 numPregs = vfPreg.numEntries, 469 numDeqOutside = 0, 470 schdType = schdType, 471 rfDataWidth = vfPreg.dataCfg.dataWidth, 472 numUopIn = dpParams.VecDqDeqWidth, 473 ) 474 } 475 476 val memSchdParams = { 477 implicit val schdType: SchedulerType = MemScheduler() 478 val rfDataWidth = 64 479 480 SchdBlockParams(Seq( 481 IssueBlockParams(Seq( 482 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))), 483 ), numEntries = 16, numEnq = 1, numComp = 15), 484 IssueBlockParams(Seq( 485 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))), 486 ), numEntries = 16, numEnq = 1, numComp = 15), 487 IssueBlockParams(Seq( 488 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(8, 0))), true, 2), 489 ), numEntries = 16, numEnq = 1, numComp = 15), 490 IssueBlockParams(Seq( 491 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(9, 0))), true, 2), 492 ), numEntries = 16, numEnq = 1, numComp = 15), 493 IssueBlockParams(Seq( 494 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(10, 0))), true, 2), 495 ), numEntries = 16, numEnq = 1, numComp = 15), 496 IssueBlockParams(Seq( 497 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0), VlWB(port = 2, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 498 ), numEntries = 16, numEnq = 1, numComp = 15), 499 IssueBlockParams(Seq( 500 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0), VlWB(port = 3, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 501 ), numEntries = 16, numEnq = 1, numComp = 15), 502 IssueBlockParams(Seq( 503 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(12, 0)))), 504 ), numEntries = 16, numEnq = 1, numComp = 15), 505 IssueBlockParams(Seq( 506 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(13, 0)))), 507 ), numEntries = 16, numEnq = 1, numComp = 15), 508 ), 509 numPregs = intPreg.numEntries max vfPreg.numEntries, 510 numDeqOutside = 0, 511 schdType = schdType, 512 rfDataWidth = rfDataWidth, 513 numUopIn = dpParams.LsDqDeqWidth, 514 ) 515 } 516 517 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 518 519 def iqWakeUpParams = { 520 Seq( 521 WakeUpConfig( 522 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 523 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 524 ), 525 // TODO: add load -> fp slow wakeup 526 WakeUpConfig( 527 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 528 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 529 ), 530 WakeUpConfig( 531 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 532 Seq("STD0", "STD1") 533 ), 534// WakeUpConfig( 535// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 536// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") 537// ), 538 ).flatten 539 } 540 541 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 542 543 val backendParams: BackendParams = backend.BackendParams( 544 Map( 545 IntScheduler() -> intSchdParams, 546 FpScheduler() -> fpSchdParams, 547 VfScheduler() -> vfSchdParams, 548 MemScheduler() -> memSchdParams, 549 ), 550 Seq( 551 intPreg, 552 fpPreg, 553 vfPreg, 554 v0Preg, 555 vlPreg, 556 fakeIntPreg 557 ), 558 iqWakeUpParams, 559 ) 560 561 // Parameters for trace extension. 562 // Trace parameters is useful for XSTOP. 563 val TraceGroupNum = 3 // Width to Encoder 564} 565 566case object DebugOptionsKey extends Field[DebugOptions] 567 568case class DebugOptions 569( 570 FPGAPlatform: Boolean = false, 571 ResetGen: Boolean = false, 572 EnableDifftest: Boolean = false, 573 AlwaysBasicDiff: Boolean = true, 574 EnableDebug: Boolean = false, 575 EnablePerfDebug: Boolean = true, 576 UseDRAMSim: Boolean = false, 577 EnableConstantin: Boolean = false, 578 EnableChiselDB: Boolean = false, 579 AlwaysBasicDB: Boolean = true, 580 EnableRollingDB: Boolean = false 581) 582 583trait HasXSParameter { 584 585 implicit val p: Parameters 586 587 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 588 def PmemRanges = p(SoCParamsKey).PmemRanges 589 def PmemLowBounds = PmemRanges.unzip._1 590 def PmemHighBounds = PmemRanges.unzip._2 591 final val PageOffsetWidth = 12 592 def NodeIDWidth = p(SoCParamsKey).NodeIDWidthList(p(CHIIssue)) // NodeID width among NoC 593 594 def coreParams = p(XSCoreParamsKey) 595 def env = p(DebugOptionsKey) 596 597 def ISABase = coreParams.ISABase 598 def ISAExtensions = coreParams.ISAExtensions 599 def XLEN = coreParams.XLEN 600 def VLEN = coreParams.VLEN 601 def ELEN = coreParams.ELEN 602 def HSXLEN = coreParams.HSXLEN 603 val minFLen = 32 604 val fLen = 64 605 def hartIdLen = p(MaxHartIdBits) 606 val xLen = XLEN 607 608 def HasMExtension = coreParams.HasMExtension 609 def HasCExtension = coreParams.HasCExtension 610 def HasHExtension = coreParams.HasHExtension 611 def EnableSv48 = coreParams.EnableSv48 612 def HasDiv = coreParams.HasDiv 613 def HasIcache = coreParams.HasICache 614 def HasDcache = coreParams.HasDCache 615 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 616 def PAddrBitsMax = coreParams.PAddrBitsMax 617 def GPAddrBitsSv39x4 = coreParams.GPAddrBitsSv39x4 618 def GPAddrBitsSv48x4 = coreParams.GPAddrBitsSv48x4 619 def GPAddrBits = { 620 if (EnableSv48) 621 coreParams.GPAddrBitsSv48x4 622 else 623 coreParams.GPAddrBitsSv39x4 624 } 625 def VAddrBits = { 626 if (HasHExtension) { 627 if (EnableSv48) 628 coreParams.GPAddrBitsSv48x4 629 else 630 coreParams.GPAddrBitsSv39x4 631 } else { 632 if (EnableSv48) 633 coreParams.VAddrBitsSv48 634 else 635 coreParams.VAddrBitsSv39 636 } 637 } // VAddrBits is Virtual Memory addr bits 638 639 def VAddrMaxBits = { 640 if(EnableSv48) { 641 coreParams.VAddrBitsSv48 max coreParams.GPAddrBitsSv48x4 642 } else { 643 coreParams.VAddrBitsSv39 max coreParams.GPAddrBitsSv39x4 644 } 645 } 646 647 def AsidLength = coreParams.AsidLength 648 def VmidLength = coreParams.VmidLength 649 def ReSelectLen = coreParams.ReSelectLen 650 def AddrBytes = AddrBits / 8 // unused 651 def DataBits = XLEN 652 def DataBytes = DataBits / 8 653 def VDataBytes = VLEN / 8 654 def HasFPU = coreParams.HasFPU 655 def HasVPU = coreParams.HasVPU 656 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 657 def FetchWidth = coreParams.FetchWidth 658 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 659 def EnableBPU = coreParams.EnableBPU 660 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 661 def EnableRAS = coreParams.EnableRAS 662 def EnableLB = coreParams.EnableLB 663 def EnableLoop = coreParams.EnableLoop 664 def EnableSC = coreParams.EnableSC 665 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 666 def HistoryLength = coreParams.HistoryLength 667 def EnableGHistDiff = coreParams.EnableGHistDiff 668 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 669 def EnableClockGate = coreParams.EnableClockGate 670 def UbtbGHRLength = coreParams.UbtbGHRLength 671 def UbtbSize = coreParams.UbtbSize 672 def EnableFauFTB = coreParams.EnableFauFTB 673 def FtbSize = coreParams.FtbSize 674 def FtbWays = coreParams.FtbWays 675 def FtbTagLength = coreParams.FtbTagLength 676 def RasSize = coreParams.RasSize 677 def RasSpecSize = coreParams.RasSpecSize 678 def RasCtrSize = coreParams.RasCtrSize 679 680 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 681 coreParams.branchPredictor(resp_in, p) 682 } 683 def numBr = coreParams.numBr 684 def TageTableInfos = coreParams.TageTableInfos 685 def TageBanks = coreParams.numBr 686 def SCNRows = coreParams.SCNRows 687 def SCCtrBits = coreParams.SCCtrBits 688 def SCHistLens = coreParams.SCHistLens 689 def SCNTables = coreParams.SCNTables 690 691 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 692 case ((n, cb), h) => (n, cb, h) 693 } 694 def ITTageTableInfos = coreParams.ITTageTableInfos 695 type FoldedHistoryInfo = Tuple2[Int, Int] 696 def foldedGHistInfos = 697 (TageTableInfos.map{ case (nRows, h, t) => 698 if (h > 0) 699 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 700 else 701 Set[FoldedHistoryInfo]() 702 }.reduce(_++_).toSet ++ 703 SCTableInfos.map{ case (nRows, _, h) => 704 if (h > 0) 705 Set((h, min(log2Ceil(nRows/TageBanks), h))) 706 else 707 Set[FoldedHistoryInfo]() 708 }.reduce(_++_).toSet ++ 709 ITTageTableInfos.map{ case (nRows, h, t) => 710 if (h > 0) 711 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 712 else 713 Set[FoldedHistoryInfo]() 714 }.reduce(_++_) ++ 715 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 716 ).toList 717 718 719 720 def CacheLineSize = coreParams.CacheLineSize 721 def CacheLineHalfWord = CacheLineSize / 16 722 def ExtHistoryLength = HistoryLength + 64 723 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 724 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 725 def IBufSize = coreParams.IBufSize 726 def IBufNBank = coreParams.IBufNBank 727 def backendParams: BackendParams = coreParams.backendParams 728 def DecodeWidth = coreParams.DecodeWidth 729 def RenameWidth = coreParams.RenameWidth 730 def CommitWidth = coreParams.CommitWidth 731 def RobCommitWidth = coreParams.RobCommitWidth 732 def RabCommitWidth = coreParams.RabCommitWidth 733 def MaxUopSize = coreParams.MaxUopSize 734 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 735 def RenameSnapshotNum = coreParams.RenameSnapshotNum 736 def FtqSize = coreParams.FtqSize 737 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 738 def IntLogicRegs = coreParams.IntLogicRegs 739 def FpLogicRegs = coreParams.FpLogicRegs 740 def VecLogicRegs = coreParams.VecLogicRegs 741 def V0LogicRegs = coreParams.V0LogicRegs 742 def VlLogicRegs = coreParams.VlLogicRegs 743 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 744 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 745 def V0_IDX = coreParams.V0_IDX 746 def Vl_IDX = coreParams.Vl_IDX 747 def IntPhyRegs = coreParams.intPreg.numEntries 748 def FpPhyRegs = coreParams.fpPreg.numEntries 749 def VfPhyRegs = coreParams.vfPreg.numEntries 750 def V0PhyRegs = coreParams.v0Preg.numEntries 751 def VlPhyRegs = coreParams.vlPreg.numEntries 752 def MaxPhyRegs = Seq(IntPhyRegs, FpPhyRegs, VfPhyRegs, V0PhyRegs, VlPhyRegs).max 753 def IntPhyRegIdxWidth = log2Up(IntPhyRegs) 754 def FpPhyRegIdxWidth = log2Up(FpPhyRegs) 755 def VfPhyRegIdxWidth = log2Up(VfPhyRegs) 756 def V0PhyRegIdxWidth = log2Up(V0PhyRegs) 757 def VlPhyRegIdxWidth = log2Up(VlPhyRegs) 758 def PhyRegIdxWidth = Seq(IntPhyRegIdxWidth, FpPhyRegIdxWidth, VfPhyRegIdxWidth, V0PhyRegIdxWidth, VlPhyRegIdxWidth).max 759 def RobSize = coreParams.RobSize 760 def RabSize = coreParams.RabSize 761 def VTypeBufferSize = coreParams.VTypeBufferSize 762 def IntRegCacheSize = coreParams.IntRegCacheSize 763 def MemRegCacheSize = coreParams.MemRegCacheSize 764 def RegCacheSize = coreParams.RegCacheSize 765 def RegCacheIdxWidth = coreParams.RegCacheIdxWidth 766 /** 767 * the minimum element length of vector elements 768 */ 769 def minVecElen: Int = coreParams.minVecElen 770 771 /** 772 * the maximum number of elements in vector register 773 */ 774 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 775 776 def IntRefCounterWidth = log2Ceil(RobSize) 777 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 778 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 779 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 780 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 781 def LoadQueueRARSize = coreParams.LoadQueueRARSize 782 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 783 def RollbackGroupSize = coreParams.RollbackGroupSize 784 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 785 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 786 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 787 def StoreQueueSize = coreParams.StoreQueueSize 788 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 789 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 790 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 791 def VlsQueueSize = coreParams.VlsQueueSize 792 def dpParams = coreParams.dpParams 793 794 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 795 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 796 797 def NumRedirect = backendParams.numRedirect 798 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 799 def FtqRedirectAheadNum = NumRedirect 800 def IfuRedirectNum = coreParams.IfuRedirectNum 801 def LoadPipelineWidth = coreParams.LoadPipelineWidth 802 def StorePipelineWidth = coreParams.StorePipelineWidth 803 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 804 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 805 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 806 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 807 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 808 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 809 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 810 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 811 def StoreBufferSize = coreParams.StoreBufferSize 812 def StoreBufferThreshold = coreParams.StoreBufferThreshold 813 def EnsbufferWidth = coreParams.EnsbufferWidth 814 def LoadDependencyWidth = coreParams.LoadDependencyWidth 815 def VlMergeBufferSize = coreParams.VlMergeBufferSize 816 def VsMergeBufferSize = coreParams.VsMergeBufferSize 817 def UopWritebackWidth = coreParams.UopWritebackWidth 818 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 819 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 820 def VSegmentBufferSize = coreParams.VSegmentBufferSize 821 def VFOFBufferSize = coreParams.VFOFBufferSize 822 def UncacheBufferSize = coreParams.UncacheBufferSize 823 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 824 def EnableFastForward = coreParams.EnableFastForward 825 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 826 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 827 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 828 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 829 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 830 def EnableHardwareStoreMisalign = coreParams.EnableHardwareStoreMisalign 831 def EnableHardwareLoadMisalign = coreParams.EnableHardwareLoadMisalign 832 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 833 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 834 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 835 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 836 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 837 def HasCMO = coreParams.HasCMO && p(EnableCHI) 838 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 839 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 840 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 841 def asidLen = coreParams.MMUAsidLen 842 def vmidLen = coreParams.MMUVmidLen 843 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 844 def refillBothTlb = coreParams.refillBothTlb 845 def iwpuParam = coreParams.iwpuParameters 846 def dwpuParam = coreParams.dwpuParameters 847 def itlbParams = coreParams.itlbParameters 848 def ldtlbParams = coreParams.ldtlbParameters 849 def sttlbParams = coreParams.sttlbParameters 850 def hytlbParams = coreParams.hytlbParameters 851 def pftlbParams = coreParams.pftlbParameters 852 def l2ToL1Params = coreParams.l2ToL1tlbParameters 853 def btlbParams = coreParams.btlbParameters 854 def l2tlbParams = coreParams.l2tlbParameters 855 def NumPerfCounters = coreParams.NumPerfCounters 856 857 def instBytes = if (HasCExtension) 2 else 4 858 def instOffsetBits = log2Ceil(instBytes) 859 860 def icacheParameters = coreParams.icacheParameters 861 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 862 863 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 864 // for constrained LR/SC loop 865 def LRSCCycles = 64 866 // for lr storm 867 def LRSCBackOff = 8 868 869 // cache hierarchy configurations 870 def l1BusDataWidth = 256 871 872 // load violation predict 873 def ResetTimeMax2Pow = 20 //1078576 874 def ResetTimeMin2Pow = 10 //1024 875 // wait table parameters 876 def WaitTableSize = 1024 877 def MemPredPCWidth = log2Up(WaitTableSize) 878 def LWTUse2BitCounter = true 879 // store set parameters 880 def SSITSize = WaitTableSize 881 def LFSTSize = 32 882 def SSIDWidth = log2Up(LFSTSize) 883 def LFSTWidth = 4 884 def StoreSetEnable = true // LWT will be disabled if SS is enabled 885 def LFSTEnable = true 886 887 def PCntIncrStep: Int = 6 888 def numPCntHc: Int = 12 889 def numPCntPtw: Int = 19 890 891 def numCSRPCntFrontend = 8 892 def numCSRPCntCtrl = 8 893 def numCSRPCntLsu = 8 894 def numCSRPCntHc = 5 895 def printEventCoding = true 896 def printCriticalError = false 897 def maxCommitStuck = pow(2, 21).toInt 898 899 // Vector load exception 900 def maxMergeNumPerCycle = 4 901 902 // Parameters for Sdtrig extension 903 protected def TriggerNum = 4 904 protected def TriggerChainMaxLength = 2 905 906 // Parameters for Trace extension 907 def TraceGroupNum = coreParams.TraceGroupNum 908} 909