1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import freechips.rocketchip.tile.MaxHartIdBits 42import system.SoCParamsKey 43import huancun._ 44import huancun.debug._ 45import xiangshan.cache.wpu.WPUParameters 46import coupledL2._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.min 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBits: Int = 39, 72 GPAddrBits: Int = 41, 73 HasFPU: Boolean = true, 74 HasVPU: Boolean = true, 75 HasCustomCSRCacheOp: Boolean = true, 76 FetchWidth: Int = 8, 77 AsidLength: Int = 16, 78 VmidLength: Int = 14, 79 EnableBPU: Boolean = true, 80 EnableBPD: Boolean = true, 81 EnableRAS: Boolean = true, 82 EnableLB: Boolean = false, 83 EnableLoop: Boolean = true, 84 EnableSC: Boolean = true, 85 EnbaleTlbDebug: Boolean = false, 86 EnableClockGate: Boolean = true, 87 EnableJal: Boolean = false, 88 EnableFauFTB: Boolean = true, 89 UbtbGHRLength: Int = 4, 90 // HistoryLength: Int = 512, 91 EnableGHistDiff: Boolean = true, 92 EnableCommitGHistDiff: Boolean = true, 93 UbtbSize: Int = 256, 94 FtbSize: Int = 2048, 95 RasSize: Int = 16, 96 RasSpecSize: Int = 32, 97 RasCtrSize: Int = 3, 98 CacheLineSize: Int = 512, 99 FtbWays: Int = 4, 100 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 101 // Sets Hist Tag 102 Seq(( 4096, 8, 8), 103 ( 4096, 13, 8), 104 ( 4096, 32, 8), 105 ( 4096, 119, 8)), 106 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 107 // Sets Hist Tag 108 Seq(( 256, 4, 9), 109 ( 256, 8, 9), 110 ( 512, 13, 9), 111 ( 512, 16, 9), 112 ( 512, 32, 9)), 113 SCNRows: Int = 512, 114 SCNTables: Int = 4, 115 SCCtrBits: Int = 6, 116 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 117 numBr: Int = 2, 118 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 119 (resp_in: BranchPredictionResp, p: Parameters) => { 120 val ftb = Module(new FTB()(p)) 121 val uftb = Module(new FauFTB()(p)) 122 val tage = Module(new Tage_SC()(p)) 123 val ras = Module(new RAS()(p)) 124 val ittage = Module(new ITTage()(p)) 125 val preds = Seq(uftb, tage, ftb, ittage, ras) 126 preds.map(_.io := DontCare) 127 128 uftb.io.in.bits.resp_in(0) := resp_in 129 tage.io.in.bits.resp_in(0) := uftb.io.out 130 ftb.io.in.bits.resp_in(0) := tage.io.out 131 ittage.io.in.bits.resp_in(0) := ftb.io.out 132 ras.io.in.bits.resp_in(0) := ittage.io.out 133 134 (preds, ras.io.out) 135 }, 136 ICacheECCForceError: Boolean = false, 137 IBufSize: Int = 48, 138 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 139 DecodeWidth: Int = 6, 140 RenameWidth: Int = 6, 141 CommitWidth: Int = 8, 142 RobCommitWidth: Int = 8, 143 RabCommitWidth: Int = 6, 144 MaxUopSize: Int = 65, 145 EnableRenameSnapshot: Boolean = true, 146 RenameSnapshotNum: Int = 4, 147 FtqSize: Int = 64, 148 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 149 IntLogicRegs: Int = 32, 150 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 151 VecLogicRegs: Int = 32 + 15, // 15: tmp 152 V0LogicRegs: Int = 1, // V0 153 VlLogicRegs: Int = 1, // Vl 154 V0_IDX: Int = 0, 155 Vl_IDX: Int = 0, 156 NRPhyRegs: Int = 192, 157 VirtualLoadQueueSize: Int = 72, 158 LoadQueueRARSize: Int = 72, 159 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 160 RollbackGroupSize: Int = 8, 161 LoadQueueReplaySize: Int = 72, 162 LoadUncacheBufferSize: Int = 20, 163 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 164 StoreQueueSize: Int = 64, 165 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 166 StoreQueueForwardWithMask: Boolean = true, 167 VlsQueueSize: Int = 8, 168 RobSize: Int = 160, 169 RabSize: Int = 256, 170 VTypeBufferSize: Int = 64, // used to reorder vtype 171 IssueQueueSize: Int = 24, 172 IssueQueueCompEntrySize: Int = 16, 173 dpParams: DispatchParameters = DispatchParameters( 174 IntDqSize = 16, 175 FpDqSize = 16, 176 LsDqSize = 18, 177 IntDqDeqWidth = 8, 178 FpDqDeqWidth = 6, 179 VecDqDeqWidth = 6, 180 LsDqDeqWidth = 6, 181 ), 182 intPreg: PregParams = IntPregParams( 183 numEntries = 224, 184 numRead = None, 185 numWrite = None, 186 ), 187 fpPreg: PregParams = FpPregParams( 188 numEntries = 192, 189 numRead = None, 190 numWrite = None, 191 ), 192 vfPreg: VfPregParams = VfPregParams( 193 numEntries = 128, 194 numRead = None, 195 numWrite = None, 196 ), 197 v0Preg: V0PregParams = V0PregParams( 198 numEntries = 22, 199 numRead = None, 200 numWrite = None, 201 ), 202 vlPreg: VlPregParams = VlPregParams( 203 numEntries = 32, 204 numRead = None, 205 numWrite = None, 206 ), 207 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 208 LoadPipelineWidth: Int = 3, 209 StorePipelineWidth: Int = 2, 210 VecLoadPipelineWidth: Int = 2, 211 VecStorePipelineWidth: Int = 2, 212 VecMemSrcInWidth: Int = 2, 213 VecMemInstWbWidth: Int = 1, 214 VecMemDispatchWidth: Int = 1, 215 VecMemDispatchMaxNumber: Int = 16, 216 StoreBufferSize: Int = 16, 217 StoreBufferThreshold: Int = 7, 218 EnsbufferWidth: Int = 2, 219 LoadDependencyWidth: Int = 2, 220 // ============ VLSU ============ 221 VlMergeBufferSize: Int = 16, 222 VsMergeBufferSize: Int = 16, 223 UopWritebackWidth: Int = 2, 224 VLUopWritebackWidth: Int = 2, 225 VSUopWritebackWidth: Int = 1, 226 SplitBufferSize: Int = 8, 227 VSegmentBufferSize: Int = 8, 228 // ============================== 229 UncacheBufferSize: Int = 4, 230 EnableLoadToLoadForward: Boolean = false, 231 EnableFastForward: Boolean = true, 232 EnableLdVioCheckAfterReset: Boolean = true, 233 EnableSoftPrefetchAfterReset: Boolean = true, 234 EnableCacheErrorAfterReset: Boolean = true, 235 EnableAccurateLoadError: Boolean = true, 236 EnableUncacheWriteOutstanding: Boolean = false, 237 EnableStorePrefetchAtIssue: Boolean = false, 238 EnableStorePrefetchAtCommit: Boolean = false, 239 EnableAtCommitMissTrigger: Boolean = true, 240 EnableStorePrefetchSMS: Boolean = false, 241 EnableStorePrefetchSPB: Boolean = false, 242 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 243 MMUVmidLen: Int = 14, 244 ReSelectLen: Int = 7, // load replay queue replay select counter len 245 iwpuParameters: WPUParameters = WPUParameters( 246 enWPU = false, 247 algoName = "mmru", 248 isICache = true, 249 ), 250 dwpuParameters: WPUParameters = WPUParameters( 251 enWPU = false, 252 algoName = "mmru", 253 enCfPred = false, 254 isICache = false, 255 ), 256 itlbParameters: TLBParameters = TLBParameters( 257 name = "itlb", 258 fetchi = true, 259 useDmode = false, 260 NWays = 48, 261 ), 262 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 263 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 264 ldtlbParameters: TLBParameters = TLBParameters( 265 name = "ldtlb", 266 NWays = 48, 267 outReplace = false, 268 partialStaticPMP = true, 269 outsideRecvFlush = true, 270 saveLevel = true, 271 lgMaxSize = 4 272 ), 273 sttlbParameters: TLBParameters = TLBParameters( 274 name = "sttlb", 275 NWays = 48, 276 outReplace = false, 277 partialStaticPMP = true, 278 outsideRecvFlush = true, 279 saveLevel = true, 280 lgMaxSize = 4 281 ), 282 hytlbParameters: TLBParameters = TLBParameters( 283 name = "hytlb", 284 NWays = 48, 285 outReplace = false, 286 partialStaticPMP = true, 287 outsideRecvFlush = true, 288 saveLevel = true, 289 lgMaxSize = 4 290 ), 291 pftlbParameters: TLBParameters = TLBParameters( 292 name = "pftlb", 293 NWays = 48, 294 outReplace = false, 295 partialStaticPMP = true, 296 outsideRecvFlush = true, 297 saveLevel = true, 298 lgMaxSize = 4 299 ), 300 l2ToL1tlbParameters: TLBParameters = TLBParameters( 301 name = "l2tlb", 302 NWays = 48, 303 outReplace = false, 304 partialStaticPMP = true, 305 outsideRecvFlush = true, 306 saveLevel = true 307 ), 308 refillBothTlb: Boolean = false, 309 btlbParameters: TLBParameters = TLBParameters( 310 name = "btlb", 311 NWays = 48, 312 ), 313 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 314 NumPerfCounters: Int = 16, 315 icacheParameters: ICacheParameters = ICacheParameters( 316 tagECC = Some("parity"), 317 dataECC = Some("parity"), 318 replacer = Some("setplru"), 319 nMissEntries = 2, 320 nProbeEntries = 2, 321 nPrefetchEntries = 12, 322 nPrefBufferEntries = 32, 323 ), 324 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 325 tagECC = Some("secded"), 326 dataECC = Some("secded"), 327 replacer = Some("setplru"), 328 nMissEntries = 16, 329 nProbeEntries = 8, 330 nReleaseEntries = 18, 331 nMaxPrefetchEntry = 6, 332 )), 333 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 334 name = "l2", 335 ways = 8, 336 sets = 1024, // default 512KB L2 337 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 338 coupledL2.prefetch.TPParameters()), 339 )), 340 L2NBanks: Int = 1, 341 usePTWRepeater: Boolean = false, 342 softTLB: Boolean = false, // dpi-c l1tlb debug only 343 softPTW: Boolean = false, // dpi-c l2tlb debug only 344 softPTWDelay: Int = 1 345){ 346 def vlWidth = log2Up(VLEN) + 1 347 348 /** 349 * the minimum element length of vector elements 350 */ 351 val minVecElen: Int = 8 352 353 /** 354 * the maximum number of elements in vector register 355 */ 356 val maxElemPerVreg: Int = VLEN / minVecElen 357 358 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 359 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 360 361 val intSchdParams = { 362 implicit val schdType: SchedulerType = IntScheduler() 363 SchdBlockParams(Seq( 364 IssueBlockParams(Seq( 365 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 366 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(1, 1))), true, 2), 367 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 368 IssueBlockParams(Seq( 369 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 370 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(3, 1))), true, 2), 371 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 372 IssueBlockParams(Seq( 373 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 374 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = 0, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(5, 1)))), 375 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 376 IssueBlockParams(Seq( 377 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 378 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(7, 1)))), 379 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 380 ), 381 numPregs = intPreg.numEntries, 382 numDeqOutside = 0, 383 schdType = schdType, 384 rfDataWidth = intPreg.dataCfg.dataWidth, 385 numUopIn = dpParams.IntDqDeqWidth, 386 ) 387 } 388 389 val fpSchdParams = { 390 implicit val schdType: SchedulerType = FpScheduler() 391 SchdBlockParams(Seq( 392 IssueBlockParams(Seq( 393 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 394 ), numEntries = 18, numEnq = 2, numComp = 16), 395 IssueBlockParams(Seq( 396 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 397 ), numEntries = 18, numEnq = 2, numComp = 16), 398 IssueBlockParams(Seq( 399 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 400 ), numEntries = 18, numEnq = 2, numComp = 16), 401 IssueBlockParams(Seq( 402 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 403 ), numEntries = 18, numEnq = 2, numComp = 16), 404 IssueBlockParams(Seq( 405 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 406 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 407 ), numEntries = 18, numEnq = 2, numComp = 16), 408 ), 409 numPregs = fpPreg.numEntries, 410 numDeqOutside = 0, 411 schdType = schdType, 412 rfDataWidth = fpPreg.dataCfg.dataWidth, 413 numUopIn = dpParams.VecDqDeqWidth, 414 ) 415 } 416 417 val vfSchdParams = { 418 implicit val schdType: SchedulerType = VfScheduler() 419 SchdBlockParams(Seq( 420 IssueBlockParams(Seq( 421 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 422 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = 1, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 423 ), numEntries = 16, numEnq = 2, numComp = 14), 424 IssueBlockParams(Seq( 425 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 426 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 427 ), numEntries = 16, numEnq = 2, numComp = 14), 428 IssueBlockParams(Seq( 429 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 430 ), numEntries = 10, numEnq = 2, numComp = 8), 431 ), 432 numPregs = vfPreg.numEntries, 433 numDeqOutside = 0, 434 schdType = schdType, 435 rfDataWidth = vfPreg.dataCfg.dataWidth, 436 numUopIn = dpParams.VecDqDeqWidth, 437 ) 438 } 439 440 val memSchdParams = { 441 implicit val schdType: SchedulerType = MemScheduler() 442 val rfDataWidth = 64 443 444 SchdBlockParams(Seq( 445 IssueBlockParams(Seq( 446 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(11, 1)))), 447 ), numEntries = 16, numEnq = 2, numComp = 14), 448 IssueBlockParams(Seq( 449 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(8, 1)))), 450 ), numEntries = 16, numEnq = 2, numComp = 14), 451 IssueBlockParams(Seq( 452 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 453 ), numEntries = 16, numEnq = 2, numComp = 14), 454 IssueBlockParams(Seq( 455 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 456 ), numEntries = 16, numEnq = 2, numComp = 14), 457 IssueBlockParams(Seq( 458 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 459 ), numEntries = 16, numEnq = 2, numComp = 14), 460 IssueBlockParams(Seq( 461 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 462 ), numEntries = 16, numEnq = 2, numComp = 14), 463 IssueBlockParams(Seq( 464 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 465 ), numEntries = 16, numEnq = 2, numComp = 14), 466 IssueBlockParams(Seq( 467 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(10, 1), FpRD(12, 0)))), 468 ), numEntries = 16, numEnq = 2, numComp = 14), 469 IssueBlockParams(Seq( 470 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(11, 1), FpRD(13, 0)))), 471 ), numEntries = 16, numEnq = 2, numComp = 14), 472 ), 473 numPregs = intPreg.numEntries max vfPreg.numEntries, 474 numDeqOutside = 0, 475 schdType = schdType, 476 rfDataWidth = rfDataWidth, 477 numUopIn = dpParams.LsDqDeqWidth, 478 ) 479 } 480 481 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 482 483 def iqWakeUpParams = { 484 Seq( 485 WakeUpConfig( 486 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 487 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 488 ), 489 WakeUpConfig( 490 Seq("FEX0", "FEX1", "FEX2", "FEX3", "LDU0", "LDU1", "LDU2") -> 491 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 492 ), 493 WakeUpConfig( 494 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 495 Seq("STD0", "STD1") 496 ), 497 WakeUpConfig( 498 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 499 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "VFEX4") 500 ), 501 ).flatten 502 } 503 504 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 505 506 val backendParams: BackendParams = backend.BackendParams( 507 Map( 508 IntScheduler() -> intSchdParams, 509 FpScheduler() -> fpSchdParams, 510 VfScheduler() -> vfSchdParams, 511 MemScheduler() -> memSchdParams, 512 ), 513 Seq( 514 intPreg, 515 fpPreg, 516 vfPreg, 517 v0Preg, 518 vlPreg, 519 fakeIntPreg 520 ), 521 iqWakeUpParams, 522 ) 523} 524 525case object DebugOptionsKey extends Field[DebugOptions] 526 527case class DebugOptions 528( 529 FPGAPlatform: Boolean = false, 530 ResetGen: Boolean = false, 531 EnableDifftest: Boolean = false, 532 AlwaysBasicDiff: Boolean = true, 533 EnableDebug: Boolean = false, 534 EnablePerfDebug: Boolean = true, 535 UseDRAMSim: Boolean = false, 536 EnableConstantin: Boolean = false, 537 EnableChiselDB: Boolean = false, 538 AlwaysBasicDB: Boolean = true, 539 EnableTopDown: Boolean = false, 540 EnableRollingDB: Boolean = false 541) 542 543trait HasXSParameter { 544 545 implicit val p: Parameters 546 547 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 548 def NodeIDWidth = p(SoCParamsKey).NodeIDWidth // NodeID width among NoC 549 550 def coreParams = p(XSCoreParamsKey) 551 def env = p(DebugOptionsKey) 552 553 def XLEN = coreParams.XLEN 554 def VLEN = coreParams.VLEN 555 def ELEN = coreParams.ELEN 556 def HSXLEN = coreParams.HSXLEN 557 val minFLen = 32 558 val fLen = 64 559 def hartIdLen = p(MaxHartIdBits) 560 val xLen = XLEN 561 562 def HasMExtension = coreParams.HasMExtension 563 def HasCExtension = coreParams.HasCExtension 564 def HasHExtension = coreParams.HasHExtension 565 def HasDiv = coreParams.HasDiv 566 def HasIcache = coreParams.HasICache 567 def HasDcache = coreParams.HasDCache 568 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 569 def GPAddrBits = coreParams.GPAddrBits 570 def VAddrBits = { 571 if(HasHExtension){ 572 coreParams.GPAddrBits 573 }else{ 574 coreParams.VAddrBits 575 } 576 } // VAddrBits is Virtual Memory addr bits 577 578 def AsidLength = coreParams.AsidLength 579 def VmidLength = coreParams.VmidLength 580 def ReSelectLen = coreParams.ReSelectLen 581 def AddrBytes = AddrBits / 8 // unused 582 def DataBits = XLEN 583 def DataBytes = DataBits / 8 584 def VDataBytes = VLEN / 8 585 def HasFPU = coreParams.HasFPU 586 def HasVPU = coreParams.HasVPU 587 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 588 def FetchWidth = coreParams.FetchWidth 589 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 590 def EnableBPU = coreParams.EnableBPU 591 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 592 def EnableRAS = coreParams.EnableRAS 593 def EnableLB = coreParams.EnableLB 594 def EnableLoop = coreParams.EnableLoop 595 def EnableSC = coreParams.EnableSC 596 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 597 def HistoryLength = coreParams.HistoryLength 598 def EnableGHistDiff = coreParams.EnableGHistDiff 599 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 600 def EnableClockGate = coreParams.EnableClockGate 601 def UbtbGHRLength = coreParams.UbtbGHRLength 602 def UbtbSize = coreParams.UbtbSize 603 def EnableFauFTB = coreParams.EnableFauFTB 604 def FtbSize = coreParams.FtbSize 605 def FtbWays = coreParams.FtbWays 606 def RasSize = coreParams.RasSize 607 def RasSpecSize = coreParams.RasSpecSize 608 def RasCtrSize = coreParams.RasCtrSize 609 610 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 611 coreParams.branchPredictor(resp_in, p) 612 } 613 def numBr = coreParams.numBr 614 def TageTableInfos = coreParams.TageTableInfos 615 def TageBanks = coreParams.numBr 616 def SCNRows = coreParams.SCNRows 617 def SCCtrBits = coreParams.SCCtrBits 618 def SCHistLens = coreParams.SCHistLens 619 def SCNTables = coreParams.SCNTables 620 621 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 622 case ((n, cb), h) => (n, cb, h) 623 } 624 def ITTageTableInfos = coreParams.ITTageTableInfos 625 type FoldedHistoryInfo = Tuple2[Int, Int] 626 def foldedGHistInfos = 627 (TageTableInfos.map{ case (nRows, h, t) => 628 if (h > 0) 629 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 630 else 631 Set[FoldedHistoryInfo]() 632 }.reduce(_++_).toSet ++ 633 SCTableInfos.map{ case (nRows, _, h) => 634 if (h > 0) 635 Set((h, min(log2Ceil(nRows/TageBanks), h))) 636 else 637 Set[FoldedHistoryInfo]() 638 }.reduce(_++_).toSet ++ 639 ITTageTableInfos.map{ case (nRows, h, t) => 640 if (h > 0) 641 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 642 else 643 Set[FoldedHistoryInfo]() 644 }.reduce(_++_) ++ 645 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 646 ).toList 647 648 649 650 def CacheLineSize = coreParams.CacheLineSize 651 def CacheLineHalfWord = CacheLineSize / 16 652 def ExtHistoryLength = HistoryLength + 64 653 def ICacheECCForceError = coreParams.ICacheECCForceError 654 def IBufSize = coreParams.IBufSize 655 def IBufNBank = coreParams.IBufNBank 656 def backendParams: BackendParams = coreParams.backendParams 657 def DecodeWidth = coreParams.DecodeWidth 658 def RenameWidth = coreParams.RenameWidth 659 def CommitWidth = coreParams.CommitWidth 660 def RobCommitWidth = coreParams.RobCommitWidth 661 def RabCommitWidth = coreParams.RabCommitWidth 662 def MaxUopSize = coreParams.MaxUopSize 663 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 664 def RenameSnapshotNum = coreParams.RenameSnapshotNum 665 def FtqSize = coreParams.FtqSize 666 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 667 def IntLogicRegs = coreParams.IntLogicRegs 668 def FpLogicRegs = coreParams.FpLogicRegs 669 def VecLogicRegs = coreParams.VecLogicRegs 670 def V0LogicRegs = coreParams.V0LogicRegs 671 def VlLogicRegs = coreParams.VlLogicRegs 672 def V0_IDX = coreParams.V0_IDX 673 def Vl_IDX = coreParams.Vl_IDX 674 def IntPhyRegs = coreParams.intPreg.numEntries 675 def FpPhyRegs = coreParams.fpPreg.numEntries 676 def VfPhyRegs = coreParams.vfPreg.numEntries 677 def V0PhyRegs = coreParams.v0Preg.numEntries 678 def VlPhyRegs = coreParams.vlPreg.numEntries 679 def MaxPhyPregs = IntPhyRegs max VfPhyRegs 680 def PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(FpPhyRegs) max log2Up(VfPhyRegs) 681 def RobSize = coreParams.RobSize 682 def RabSize = coreParams.RabSize 683 def VTypeBufferSize = coreParams.VTypeBufferSize 684 /** 685 * the minimum element length of vector elements 686 */ 687 def minVecElen: Int = coreParams.minVecElen 688 689 /** 690 * the maximum number of elements in vector register 691 */ 692 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 693 694 def IntRefCounterWidth = log2Ceil(RobSize) 695 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 696 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 697 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 698 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 699 def LoadQueueRARSize = coreParams.LoadQueueRARSize 700 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 701 def RollbackGroupSize = coreParams.RollbackGroupSize 702 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 703 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 704 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 705 def StoreQueueSize = coreParams.StoreQueueSize 706 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 707 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 708 def VlsQueueSize = coreParams.VlsQueueSize 709 def dpParams = coreParams.dpParams 710 711 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 712 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 713 714 def NumRedirect = backendParams.numRedirect 715 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 716 def FtqRedirectAheadNum = NumRedirect 717 def LoadPipelineWidth = coreParams.LoadPipelineWidth 718 def StorePipelineWidth = coreParams.StorePipelineWidth 719 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 720 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 721 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 722 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 723 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 724 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 725 def StoreBufferSize = coreParams.StoreBufferSize 726 def StoreBufferThreshold = coreParams.StoreBufferThreshold 727 def EnsbufferWidth = coreParams.EnsbufferWidth 728 def LoadDependencyWidth = coreParams.LoadDependencyWidth 729 def VlMergeBufferSize = coreParams.VlMergeBufferSize 730 def VsMergeBufferSize = coreParams.VsMergeBufferSize 731 def UopWritebackWidth = coreParams.UopWritebackWidth 732 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 733 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 734 def SplitBufferSize = coreParams.SplitBufferSize 735 def VSegmentBufferSize = coreParams.VSegmentBufferSize 736 def UncacheBufferSize = coreParams.UncacheBufferSize 737 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 738 def EnableFastForward = coreParams.EnableFastForward 739 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 740 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 741 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 742 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 743 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 744 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 745 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 746 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 747 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 748 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 749 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 750 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 751 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 752 def asidLen = coreParams.MMUAsidLen 753 def vmidLen = coreParams.MMUVmidLen 754 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 755 def refillBothTlb = coreParams.refillBothTlb 756 def iwpuParam = coreParams.iwpuParameters 757 def dwpuParam = coreParams.dwpuParameters 758 def itlbParams = coreParams.itlbParameters 759 def ldtlbParams = coreParams.ldtlbParameters 760 def sttlbParams = coreParams.sttlbParameters 761 def hytlbParams = coreParams.hytlbParameters 762 def pftlbParams = coreParams.pftlbParameters 763 def l2ToL1Params = coreParams.l2ToL1tlbParameters 764 def btlbParams = coreParams.btlbParameters 765 def l2tlbParams = coreParams.l2tlbParameters 766 def NumPerfCounters = coreParams.NumPerfCounters 767 768 def instBytes = if (HasCExtension) 2 else 4 769 def instOffsetBits = log2Ceil(instBytes) 770 771 def icacheParameters = coreParams.icacheParameters 772 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 773 774 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 775 // for constrained LR/SC loop 776 def LRSCCycles = 64 777 // for lr storm 778 def LRSCBackOff = 8 779 780 // cache hierarchy configurations 781 def l1BusDataWidth = 256 782 783 // load violation predict 784 def ResetTimeMax2Pow = 20 //1078576 785 def ResetTimeMin2Pow = 10 //1024 786 // wait table parameters 787 def WaitTableSize = 1024 788 def MemPredPCWidth = log2Up(WaitTableSize) 789 def LWTUse2BitCounter = true 790 // store set parameters 791 def SSITSize = WaitTableSize 792 def LFSTSize = 32 793 def SSIDWidth = log2Up(LFSTSize) 794 def LFSTWidth = 4 795 def StoreSetEnable = true // LWT will be disabled if SS is enabled 796 def LFSTEnable = true 797 798 def PCntIncrStep: Int = 6 799 def numPCntHc: Int = 25 800 def numPCntPtw: Int = 19 801 802 def numCSRPCntFrontend = 8 803 def numCSRPCntCtrl = 8 804 def numCSRPCntLsu = 8 805 def numCSRPCntHc = 5 806 def printEventCoding = true 807 808 // Parameters for Sdtrig extension 809 protected def TriggerNum = 4 810 protected def TriggerChainMaxLength = 2 811} 812