1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import xiangshan.cache.wpu.WPUParameters 34import coupledL2._ 35import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 36 37import scala.math.min 38 39case object XSTileKey extends Field[Seq[XSCoreParameters]] 40 41case object XSCoreParamsKey extends Field[XSCoreParameters] 42 43case class XSCoreParameters 44( 45 HasPrefetch: Boolean = false, 46 HartId: Int = 0, 47 XLEN: Int = 64, 48 VLEN: Int = 128, 49 HasMExtension: Boolean = true, 50 HasCExtension: Boolean = true, 51 HasDiv: Boolean = true, 52 HasICache: Boolean = true, 53 HasDCache: Boolean = true, 54 AddrBits: Int = 64, 55 VAddrBits: Int = 39, 56 HasFPU: Boolean = true, 57 HasCustomCSRCacheOp: Boolean = true, 58 FetchWidth: Int = 8, 59 AsidLength: Int = 16, 60 EnableBPU: Boolean = true, 61 EnableBPD: Boolean = true, 62 EnableRAS: Boolean = true, 63 EnableLB: Boolean = false, 64 EnableLoop: Boolean = true, 65 EnableSC: Boolean = true, 66 EnbaleTlbDebug: Boolean = false, 67 EnableJal: Boolean = false, 68 EnableFauFTB: Boolean = true, 69 UbtbGHRLength: Int = 4, 70 // HistoryLength: Int = 512, 71 EnableGHistDiff: Boolean = true, 72 EnableCommitGHistDiff: Boolean = true, 73 UbtbSize: Int = 256, 74 FtbSize: Int = 2048, 75 RasSize: Int = 32, 76 CacheLineSize: Int = 512, 77 FtbWays: Int = 4, 78 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 79 // Sets Hist Tag 80 // Seq(( 2048, 2, 8), 81 // ( 2048, 9, 8), 82 // ( 2048, 13, 8), 83 // ( 2048, 20, 8), 84 // ( 2048, 26, 8), 85 // ( 2048, 44, 8), 86 // ( 2048, 73, 8), 87 // ( 2048, 256, 8)), 88 Seq(( 4096, 8, 8), 89 ( 4096, 13, 8), 90 ( 4096, 32, 8), 91 ( 4096, 119, 8)), 92 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 93 // Sets Hist Tag 94 Seq(( 256, 4, 9), 95 ( 256, 8, 9), 96 ( 512, 13, 9), 97 ( 512, 16, 9), 98 ( 512, 32, 9)), 99 SCNRows: Int = 512, 100 SCNTables: Int = 4, 101 SCCtrBits: Int = 6, 102 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 103 numBr: Int = 2, 104 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 105 ((resp_in: BranchPredictionResp, p: Parameters) => { 106 val ftb = Module(new FTB()(p)) 107 val ubtb =Module(new FauFTB()(p)) 108 // val bim = Module(new BIM()(p)) 109 val tage = Module(new Tage_SC()(p)) 110 val ras = Module(new RAS()(p)) 111 val ittage = Module(new ITTage()(p)) 112 val preds = Seq(ubtb, tage, ftb, ittage, ras) 113 preds.map(_.io := DontCare) 114 115 // ubtb.io.resp_in(0) := resp_in 116 // bim.io.resp_in(0) := ubtb.io.resp 117 // btb.io.resp_in(0) := bim.io.resp 118 // tage.io.resp_in(0) := btb.io.resp 119 // loop.io.resp_in(0) := tage.io.resp 120 ubtb.io.in.bits.resp_in(0) := resp_in 121 tage.io.in.bits.resp_in(0) := ubtb.io.out 122 ftb.io.in.bits.resp_in(0) := tage.io.out 123 ittage.io.in.bits.resp_in(0) := ftb.io.out 124 ras.io.in.bits.resp_in(0) := ittage.io.out 125 126 (preds, ras.io.out) 127 }), 128 IBufSize: Int = 48, 129 DecodeWidth: Int = 6, 130 RenameWidth: Int = 6, 131 CommitWidth: Int = 6, 132 EnableRenameSnapshot: Boolean = true, 133 RenameSnapshotNum: Int = 4, 134 FtqSize: Int = 64, 135 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 136 IssQueSize: Int = 16, 137 NRPhyRegs: Int = 192, 138 VirtualLoadQueueSize: Int = 80, 139 LoadQueueRARSize: Int = 80, 140 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 141 RollbackGroupSize: Int = 8, 142 LoadQueueReplaySize: Int = 72, 143 LoadUncacheBufferSize: Int = 20, 144 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 145 StoreQueueSize: Int = 64, 146 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 147 StoreQueueForwardWithMask: Boolean = true, 148 VlsQueueSize: Int = 8, 149 RobSize: Int = 256, 150 dpParams: DispatchParameters = DispatchParameters( 151 IntDqSize = 16, 152 FpDqSize = 16, 153 LsDqSize = 16, 154 IntDqDeqWidth = 4, 155 FpDqDeqWidth = 4, 156 LsDqDeqWidth = 4 157 ), 158 exuParameters: ExuParameters = ExuParameters( 159 JmpCnt = 1, 160 AluCnt = 4, 161 MulCnt = 0, 162 MduCnt = 2, 163 FmacCnt = 4, 164 FmiscCnt = 2, 165 FmiscDivSqrtCnt = 0, 166 LduCnt = 2, 167 StuCnt = 2 168 ), 169 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 170 LoadPipelineWidth: Int = 2, 171 StorePipelineWidth: Int = 2, 172 VecMemSrcInWidth: Int = 2, 173 VecMemInstWbWidth: Int = 1, 174 VecMemDispatchWidth: Int = 1, 175 StoreBufferSize: Int = 16, 176 StoreBufferThreshold: Int = 7, 177 EnsbufferWidth: Int = 2, 178 UncacheBufferSize: Int = 4, 179 EnableLoadToLoadForward: Boolean = true, 180 EnableFastForward: Boolean = true, 181 EnableLdVioCheckAfterReset: Boolean = true, 182 EnableSoftPrefetchAfterReset: Boolean = true, 183 EnableCacheErrorAfterReset: Boolean = true, 184 EnableAccurateLoadError: Boolean = true, 185 EnableUncacheWriteOutstanding: Boolean = false, 186 EnableStorePrefetchAtIssue: Boolean = false, 187 EnableStorePrefetchAtCommit: Boolean = false, 188 EnableAtCommitMissTrigger: Boolean = true, 189 EnableStorePrefetchSMS: Boolean = false, 190 EnableStorePrefetchSPB: Boolean = false, 191 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 192 ReSelectLen: Int = 7, // load replay queue replay select counter len 193 iwpuParameters: WPUParameters = WPUParameters( 194 enWPU = false, 195 algoName = "mmru", 196 isICache = true, 197 ), 198 dwpuParameters: WPUParameters = WPUParameters( 199 enWPU = false, 200 algoName = "mmru", 201 enCfPred = false, 202 isICache = false, 203 ), 204 itlbParameters: TLBParameters = TLBParameters( 205 name = "itlb", 206 fetchi = true, 207 useDmode = false, 208 normalNWays = 32, 209 normalReplacer = Some("plru"), 210 superNWays = 4, 211 superReplacer = Some("plru") 212 ), 213 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 214 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 215 ldtlbParameters: TLBParameters = TLBParameters( 216 name = "ldtlb", 217 normalNSets = 64, 218 normalNWays = 1, 219 normalAssociative = "sa", 220 normalReplacer = Some("setplru"), 221 superNWays = 16, 222 normalAsVictim = true, 223 outReplace = false, 224 partialStaticPMP = true, 225 outsideRecvFlush = true, 226 saveLevel = true 227 ), 228 sttlbParameters: TLBParameters = TLBParameters( 229 name = "sttlb", 230 normalNSets = 64, 231 normalNWays = 1, 232 normalAssociative = "sa", 233 normalReplacer = Some("setplru"), 234 superNWays = 16, 235 normalAsVictim = true, 236 outReplace = false, 237 partialStaticPMP = true, 238 outsideRecvFlush = true, 239 saveLevel = true 240 ), 241 pftlbParameters: TLBParameters = TLBParameters( 242 name = "pftlb", 243 normalNSets = 64, 244 normalNWays = 1, 245 normalAssociative = "sa", 246 normalReplacer = Some("setplru"), 247 superNWays = 16, 248 normalAsVictim = true, 249 outReplace = false, 250 partialStaticPMP = true, 251 outsideRecvFlush = true, 252 saveLevel = true 253 ), 254 refillBothTlb: Boolean = false, 255 btlbParameters: TLBParameters = TLBParameters( 256 name = "btlb", 257 normalNSets = 1, 258 normalNWays = 64, 259 superNWays = 4, 260 ), 261 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 262 NumPerfCounters: Int = 16, 263 icacheParameters: ICacheParameters = ICacheParameters( 264 tagECC = Some("parity"), 265 dataECC = Some("parity"), 266 replacer = Some("setplru"), 267 nMissEntries = 2, 268 nProbeEntries = 2, 269 nPrefetchEntries = 12, 270 nPrefBufferEntries = 32, 271 hasPrefetch = true, 272 ), 273 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 274 tagECC = Some("secded"), 275 dataECC = Some("secded"), 276 replacer = Some("setplru"), 277 nMissEntries = 16, 278 nProbeEntries = 8, 279 nReleaseEntries = 18, 280 nMaxPrefetchEntry = 6, 281 )), 282 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 283 name = "l2", 284 ways = 8, 285 sets = 1024, // default 512KB L2 286 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 287 )), 288 L2NBanks: Int = 1, 289 usePTWRepeater: Boolean = false, 290 softTLB: Boolean = false, // dpi-c l1tlb debug only 291 softPTW: Boolean = false, // dpi-c l2tlb debug only 292 softPTWDelay: Int = 1 293){ 294 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 295 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 296 297 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 298 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 299 300 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 301 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 302 303 val fpExuConfigs = 304 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 305 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 306 307 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 308} 309 310case object DebugOptionsKey extends Field[DebugOptions] 311 312case class DebugOptions 313( 314 FPGAPlatform: Boolean = false, 315 EnableDifftest: Boolean = false, 316 AlwaysBasicDiff: Boolean = true, 317 EnableDebug: Boolean = false, 318 EnablePerfDebug: Boolean = true, 319 UseDRAMSim: Boolean = false, 320 EnableConstantin: Boolean = false, 321 EnableChiselDB: Boolean = false, 322 AlwaysBasicDB: Boolean = true, 323 EnableRollingDB: Boolean = false 324) 325 326trait HasXSParameter { 327 328 implicit val p: Parameters 329 330 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 331 332 val coreParams = p(XSCoreParamsKey) 333 val env = p(DebugOptionsKey) 334 335 val XLEN = coreParams.XLEN 336 val VLEN = coreParams.VLEN 337 val minFLen = 32 338 val fLen = 64 339 def xLen = XLEN 340 341 val HasMExtension = coreParams.HasMExtension 342 val HasCExtension = coreParams.HasCExtension 343 val HasDiv = coreParams.HasDiv 344 val HasIcache = coreParams.HasICache 345 val HasDcache = coreParams.HasDCache 346 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 347 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 348 val AsidLength = coreParams.AsidLength 349 val ReSelectLen = coreParams.ReSelectLen 350 val AddrBytes = AddrBits / 8 // unused 351 val DataBits = XLEN 352 val DataBytes = DataBits / 8 353 val VDataBytes = VLEN / 8 354 val HasFPU = coreParams.HasFPU 355 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 356 val FetchWidth = coreParams.FetchWidth 357 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 358 val EnableBPU = coreParams.EnableBPU 359 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 360 val EnableRAS = coreParams.EnableRAS 361 val EnableLB = coreParams.EnableLB 362 val EnableLoop = coreParams.EnableLoop 363 val EnableSC = coreParams.EnableSC 364 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 365 val HistoryLength = coreParams.HistoryLength 366 val EnableGHistDiff = coreParams.EnableGHistDiff 367 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 368 val UbtbGHRLength = coreParams.UbtbGHRLength 369 val UbtbSize = coreParams.UbtbSize 370 val EnableFauFTB = coreParams.EnableFauFTB 371 val FtbSize = coreParams.FtbSize 372 val FtbWays = coreParams.FtbWays 373 val RasSize = coreParams.RasSize 374 375 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 376 coreParams.branchPredictor(resp_in, p) 377 } 378 val numBr = coreParams.numBr 379 val TageTableInfos = coreParams.TageTableInfos 380 val TageBanks = coreParams.numBr 381 val SCNRows = coreParams.SCNRows 382 val SCCtrBits = coreParams.SCCtrBits 383 val SCHistLens = coreParams.SCHistLens 384 val SCNTables = coreParams.SCNTables 385 386 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 387 case ((n, cb), h) => (n, cb, h) 388 } 389 val ITTageTableInfos = coreParams.ITTageTableInfos 390 type FoldedHistoryInfo = Tuple2[Int, Int] 391 val foldedGHistInfos = 392 (TageTableInfos.map{ case (nRows, h, t) => 393 if (h > 0) 394 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 395 else 396 Set[FoldedHistoryInfo]() 397 }.reduce(_++_).toSet ++ 398 SCTableInfos.map{ case (nRows, _, h) => 399 if (h > 0) 400 Set((h, min(log2Ceil(nRows/TageBanks), h))) 401 else 402 Set[FoldedHistoryInfo]() 403 }.reduce(_++_).toSet ++ 404 ITTageTableInfos.map{ case (nRows, h, t) => 405 if (h > 0) 406 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 407 else 408 Set[FoldedHistoryInfo]() 409 }.reduce(_++_) ++ 410 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 411 ).toList 412 413 414 415 val CacheLineSize = coreParams.CacheLineSize 416 val CacheLineHalfWord = CacheLineSize / 16 417 val ExtHistoryLength = HistoryLength + 64 418 val IBufSize = coreParams.IBufSize 419 val DecodeWidth = coreParams.DecodeWidth 420 val RenameWidth = coreParams.RenameWidth 421 val CommitWidth = coreParams.CommitWidth 422 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 423 val RenameSnapshotNum = coreParams.RenameSnapshotNum 424 val FtqSize = coreParams.FtqSize 425 val IssQueSize = coreParams.IssQueSize 426 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 427 val NRPhyRegs = coreParams.NRPhyRegs 428 val PhyRegIdxWidth = log2Up(NRPhyRegs) 429 val RobSize = coreParams.RobSize 430 val IntRefCounterWidth = log2Ceil(RobSize) 431 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 432 val LoadQueueRARSize = coreParams.LoadQueueRARSize 433 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 434 val RollbackGroupSize = coreParams.RollbackGroupSize 435 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 436 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 437 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 438 val StoreQueueSize = coreParams.StoreQueueSize 439 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 440 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 441 val VlsQueueSize = coreParams.VlsQueueSize 442 val dpParams = coreParams.dpParams 443 val exuParameters = coreParams.exuParameters 444 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 445 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 446 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 447 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 448 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 449 val LoadPipelineWidth = coreParams.LoadPipelineWidth 450 val StorePipelineWidth = coreParams.StorePipelineWidth 451 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 452 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 453 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 454 val StoreBufferSize = coreParams.StoreBufferSize 455 val StoreBufferThreshold = coreParams.StoreBufferThreshold 456 val EnsbufferWidth = coreParams.EnsbufferWidth 457 val UncacheBufferSize = coreParams.UncacheBufferSize 458 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 459 val EnableFastForward = coreParams.EnableFastForward 460 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 461 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 462 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 463 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 464 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 465 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 466 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 467 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 468 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 469 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 470 val asidLen = coreParams.MMUAsidLen 471 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 472 val refillBothTlb = coreParams.refillBothTlb 473 val iwpuParam = coreParams.iwpuParameters 474 val dwpuParam = coreParams.dwpuParameters 475 val itlbParams = coreParams.itlbParameters 476 val ldtlbParams = coreParams.ldtlbParameters 477 val sttlbParams = coreParams.sttlbParameters 478 val pftlbParams = coreParams.pftlbParameters 479 val btlbParams = coreParams.btlbParameters 480 val l2tlbParams = coreParams.l2tlbParameters 481 val NumPerfCounters = coreParams.NumPerfCounters 482 483 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 484 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 485 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 486 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 487 488 val instBytes = if (HasCExtension) 2 else 4 489 val instOffsetBits = log2Ceil(instBytes) 490 491 val icacheParameters = coreParams.icacheParameters 492 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 493 494 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 495 // for constrained LR/SC loop 496 val LRSCCycles = 64 497 // for lr storm 498 val LRSCBackOff = 8 499 500 // cache hierarchy configurations 501 val l1BusDataWidth = 256 502 503 // load violation predict 504 val ResetTimeMax2Pow = 20 //1078576 505 val ResetTimeMin2Pow = 10 //1024 506 // wait table parameters 507 val WaitTableSize = 1024 508 val MemPredPCWidth = log2Up(WaitTableSize) 509 val LWTUse2BitCounter = true 510 // store set parameters 511 val SSITSize = WaitTableSize 512 val LFSTSize = 32 513 val SSIDWidth = log2Up(LFSTSize) 514 val LFSTWidth = 4 515 val StoreSetEnable = true // LWT will be disabled if SS is enabled 516 val LFSTEnable = false 517 val loadExuConfigs = coreParams.loadExuConfigs 518 val storeExuConfigs = coreParams.storeExuConfigs 519 520 val intExuConfigs = coreParams.intExuConfigs 521 522 val fpExuConfigs = coreParams.fpExuConfigs 523 524 val exuConfigs = coreParams.exuConfigs 525 526 val PCntIncrStep: Int = 6 527 val numPCntHc: Int = 25 528 val numPCntPtw: Int = 19 529 530 val numCSRPCntFrontend = 8 531 val numCSRPCntCtrl = 8 532 val numCSRPCntLsu = 8 533 val numCSRPCntHc = 5 534} 535