1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan 18 19import chisel3._ 20import chisel3.util._ 21import org.chipsalliance.cde.config._ 22import chisel3.util.{Valid, ValidIO} 23import freechips.rocketchip.diplomacy._ 24import freechips.rocketchip.interrupts._ 25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, MaxHartIdBits} 26import freechips.rocketchip.tilelink._ 27import coupledL2.{L2ParamKey, EnableCHI} 28import coupledL2.tl2tl.TL2TLCoupledL2 29import coupledL2.tl2chi.{TL2CHICoupledL2, PortIO} 30import huancun.BankBitsKey 31import system.HasSoCParameter 32import top.BusPerfMonitor 33import utility.{DelayN, ResetGen, TLClientsMerger, TLEdgeBuffer, TLLogger} 34import xiangshan.cache.mmu.TlbRequestIO 35 36class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter { 37 val ecc_error = Valid(UInt(soc.PAddrBits.W)) 38} 39 40class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors { 41 val icache = new L1BusErrorUnitInfo 42 val dcache = new L1BusErrorUnitInfo 43 val l2 = new L1BusErrorUnitInfo 44 45 override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] = 46 List( 47 Some(icache.ecc_error, "I_ECC", "Icache ecc error"), 48 Some(dcache.ecc_error, "D_ECC", "Dcache ecc error"), 49 Some(l2.ecc_error, "L2_ECC", "L2Cache ecc error") 50 ) 51} 52 53/** 54 * L2Top contains everything between Core and XSTile-IO 55 */ 56class L2Top()(implicit p: Parameters) extends LazyModule 57 with HasXSParameter 58 with HasSoCParameter 59{ 60 def chainBuffer(depth: Int, n: String): (Seq[LazyModule], TLNode) = { 61 val buffers = Seq.fill(depth){ LazyModule(new TLBuffer()) } 62 buffers.zipWithIndex.foreach{ case (b, i) => { 63 b.suggestName(s"${n}_${i}") 64 }} 65 val node = buffers.map(_.node.asInstanceOf[TLNode]).reduce(_ :*=* _) 66 (buffers, node) 67 } 68 val enableL2 = coreParams.L2CacheParamsOpt.isDefined 69 // =========== Components ============ 70 val l1_xbar = TLXbar() 71 val mmio_xbar = TLXbar() 72 val mmio_port = TLIdentityNode() // to L3 73 val memory_port = if (enableCHI && enableL2) None else Some(TLIdentityNode()) 74 val beu = LazyModule(new BusErrorUnit( 75 new XSL1BusErrors(), BusErrorUnitParams(0x38010000) 76 )) 77 78 val i_mmio_port = TLTempNode() 79 val d_mmio_port = TLTempNode() 80 81 val misc_l2_pmu = BusPerfMonitor(name = "Misc_L2", enable = !debugOpts.FPGAPlatform) // l1D & l1I & PTW 82 val l2_l3_pmu = BusPerfMonitor(name = "L2_L3", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true) 83 val xbar_l2_buffer = TLBuffer() 84 85 val enbale_tllog = !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB 86 val l1d_logger = TLLogger(s"L2_L1D_${coreParams.HartId}", enbale_tllog) 87 val l1i_logger = TLLogger(s"L2_L1I_${coreParams.HartId}", enbale_tllog) 88 val ptw_logger = TLLogger(s"L2_PTW_${coreParams.HartId}", enbale_tllog) 89 val ptw_to_l2_buffer = LazyModule(new TLBuffer) 90 val i_mmio_buffer = LazyModule(new TLBuffer) 91 92 val clint_int_node = IntIdentityNode() 93 val debug_int_node = IntIdentityNode() 94 val plic_int_node = IntIdentityNode() 95 96 println(s"enableCHI: ${enableCHI}") 97 val l2cache = if (enableL2) { 98 val config = new Config((_, _, _) => { 99 case L2ParamKey => coreParams.L2CacheParamsOpt.get.copy( 100 hartId = p(XSCoreParamsKey).HartId, 101 FPGAPlatform = debugOpts.FPGAPlatform 102 ) 103 case EnableCHI => p(EnableCHI) 104 case BankBitsKey => log2Ceil(coreParams.L2NBanks) 105 case MaxHartIdBits => p(MaxHartIdBits) 106 }) 107 if (enableCHI) Some(LazyModule(new TL2CHICoupledL2()(new Config(config)))) 108 else Some(LazyModule(new TL2TLCoupledL2()(new Config(config)))) 109 } else None 110 val l2_binder = coreParams.L2CacheParamsOpt.map(_ => BankBinder(coreParams.L2NBanks, 64)) 111 112 // =========== Connection ============ 113 // l2 to l2_binder, then to memory_port 114 l2cache match { 115 case Some(l2) => 116 l2_binder.get :*= l2.node :*= xbar_l2_buffer :*= l1_xbar :=* misc_l2_pmu 117 l2 match { 118 case l2: TL2TLCoupledL2 => 119 memory_port.get := l2_l3_pmu := TLClientsMerger() := TLXbar() :=* l2_binder.get 120 case l2: TL2CHICoupledL2 => 121 l2.managerNode := TLXbar() :=* l2_binder.get 122 l2.mmioNode := mmio_port 123 } 124 case None => 125 memory_port.get := l1_xbar 126 } 127 128 mmio_xbar := TLBuffer.chainNode(2) := i_mmio_port 129 mmio_xbar := TLBuffer.chainNode(2) := d_mmio_port 130 beu.node := TLBuffer.chainNode(1) := mmio_xbar 131 mmio_port := TLBuffer() := mmio_xbar 132 133 class L2TopImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 134 val beu_errors = IO(Input(chiselTypeOf(beu.module.io.errors))) 135 val reset_vector = IO(new Bundle { 136 val fromTile = Input(UInt(PAddrBits.W)) 137 val toCore = Output(UInt(PAddrBits.W)) 138 }) 139 val hartId = IO(new Bundle() { 140 val fromTile = Input(UInt(64.W)) 141 val toCore = Output(UInt(64.W)) 142 }) 143 val cpu_halt = IO(new Bundle() { 144 val fromCore = Input(Bool()) 145 val toTile = Output(Bool()) 146 }) 147 val debugTopDown = IO(new Bundle() { 148 val robTrueCommit = Input(UInt(64.W)) 149 val robHeadPaddr = Flipped(Valid(UInt(36.W))) 150 val l2MissMatch = Output(Bool()) 151 }) 152 val chi = if (enableCHI) Some(IO(new PortIO)) else None 153 val nodeID = if (enableCHI) Some(IO(Input(UInt(NodeIDWidth.W)))) else None 154 val l2_tlb_req = IO(new TlbRequestIO(nRespDups = 2)) 155 val l2_hint = IO(ValidIO(new L2ToL1Hint())) 156 157 val resetDelayN = Module(new DelayN(UInt(PAddrBits.W), 5)) 158 159 beu.module.io.errors <> beu_errors 160 resetDelayN.io.in := reset_vector.fromTile 161 reset_vector.toCore := resetDelayN.io.out 162 hartId.toCore := hartId.fromTile 163 cpu_halt.toTile := cpu_halt.fromCore 164 dontTouch(hartId) 165 dontTouch(cpu_halt) 166 if (!chi.isEmpty) { dontTouch(chi.get) } 167 168 if (l2cache.isDefined) { 169 val l2 = l2cache.get.module 170 l2_hint := l2.io.l2_hint 171 l2.io.debugTopDown.robHeadPaddr := DontCare 172 l2.io.hartId := hartId.fromTile 173 l2.io.debugTopDown.robHeadPaddr := debugTopDown.robHeadPaddr 174 l2.io.debugTopDown.robTrueCommit := debugTopDown.robTrueCommit 175 debugTopDown.l2MissMatch := l2.io.debugTopDown.l2MissMatch 176 177 /* l2 tlb */ 178 l2_tlb_req.req.bits := DontCare 179 l2_tlb_req.req.valid := l2.io.l2_tlb_req.req.valid 180 l2_tlb_req.resp.ready := l2.io.l2_tlb_req.resp.ready 181 l2_tlb_req.req.bits.vaddr := l2.io.l2_tlb_req.req.bits.vaddr 182 l2_tlb_req.req.bits.cmd := l2.io.l2_tlb_req.req.bits.cmd 183 l2_tlb_req.req.bits.size := l2.io.l2_tlb_req.req.bits.size 184 l2_tlb_req.req.bits.kill := l2.io.l2_tlb_req.req.bits.kill 185 l2_tlb_req.req.bits.no_translate := l2.io.l2_tlb_req.req.bits.no_translate 186 l2_tlb_req.req_kill := l2.io.l2_tlb_req.req_kill 187 l2.io.l2_tlb_req.resp.valid := l2_tlb_req.resp.valid 188 l2.io.l2_tlb_req.req.ready := l2_tlb_req.req.ready 189 l2.io.l2_tlb_req.resp.bits.paddr.head := l2_tlb_req.resp.bits.paddr.head 190 l2.io.l2_tlb_req.resp.bits.miss := l2_tlb_req.resp.bits.miss 191 l2.io.l2_tlb_req.resp.bits.excp.head <> l2_tlb_req.resp.bits.excp.head 192 193 l2cache.get match { 194 case l2cache: TL2CHICoupledL2 => 195 val l2 = l2cache.module 196 l2.io_nodeID := nodeID.get 197 chi.get <> l2.io_chi 198 case l2cache: TL2TLCoupledL2 => 199 } 200 } else { 201 l2_hint := 0.U.asTypeOf(l2_hint) 202 debugTopDown <> DontCare 203 204 l2_tlb_req.req.valid := false.B 205 l2_tlb_req.req.bits := DontCare 206 l2_tlb_req.req_kill := DontCare 207 l2_tlb_req.resp.ready := true.B 208 } 209 } 210 211 lazy val module = new L2TopImp(this) 212} 213