xref: /XiangShan/src/main/scala/xiangshan/L2Top.scala (revision 5c06072729ebf9577a23fe84f4eb39de6932028f) 
1/***************************************************************************************
2  * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3  * Copyright (c) 2020-2021 Peng Cheng Laboratory
4  *
5  * XiangShan is licensed under Mulan PSL v2.
6  * You can use this software according to the terms and conditions of the Mulan PSL v2.
7  * You may obtain a copy of Mulan PSL v2 at:
8  *          http://license.coscl.org.cn/MulanPSL2
9  *
10  * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11  * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12  * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13  *
14  * See the Mulan PSL v2 for more details.
15  ***************************************************************************************/
16
17package xiangshan
18
19import chisel3._
20import chisel3.util._
21import org.chipsalliance.cde.config._
22import chisel3.util.{Valid, ValidIO}
23import freechips.rocketchip.diplomacy._
24import freechips.rocketchip.interrupts._
25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, MaxHartIdBits}
26import freechips.rocketchip.tilelink._
27import coupledL2.{L2ParamKey, EnableCHI}
28import coupledL2.tl2tl.TL2TLCoupledL2
29import coupledL2.tl2chi.{TL2CHICoupledL2, PortIO, CHIIssue}
30import huancun.BankBitsKey
31import system.HasSoCParameter
32import top.BusPerfMonitor
33import utility._
34import xiangshan.cache.mmu.TlbRequestIO
35import xiangshan.backend.fu.PMPRespBundle
36
37class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {
38  val ecc_error = Valid(UInt(soc.PAddrBits.W))
39}
40
41class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors {
42  val icache = new L1BusErrorUnitInfo
43  val dcache = new L1BusErrorUnitInfo
44  val l2 = new L1BusErrorUnitInfo
45
46  override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] =
47    List(
48      Some(icache.ecc_error, "I_ECC", "Icache ecc error"),
49      Some(dcache.ecc_error, "D_ECC", "Dcache ecc error"),
50      Some(l2.ecc_error, "L2_ECC", "L2Cache ecc error")
51    )
52}
53
54/**
55  *   L2Top contains everything between Core and XSTile-IO
56  */
57class L2TopInlined()(implicit p: Parameters) extends LazyModule
58  with HasXSParameter
59  with HasSoCParameter
60{
61  override def shouldBeInlined: Boolean = true
62
63  def chainBuffer(depth: Int, n: String): (Seq[LazyModule], TLNode) = {
64    val buffers = Seq.fill(depth){ LazyModule(new TLBuffer()) }
65    buffers.zipWithIndex.foreach{ case (b, i) => {
66      b.suggestName(s"${n}_${i}")
67    }}
68    val node = buffers.map(_.node.asInstanceOf[TLNode]).reduce(_ :*=* _)
69    (buffers, node)
70  }
71  val enableL2 = coreParams.L2CacheParamsOpt.isDefined
72  // =========== Components ============
73  val l1_xbar = TLXbar()
74  val mmio_xbar = TLXbar()
75  val mmio_port = TLIdentityNode() // to L3
76  val memory_port = if (enableCHI && enableL2) None else Some(TLIdentityNode())
77  val beu = LazyModule(new BusErrorUnit(
78    new XSL1BusErrors(),
79    BusErrorUnitParams(soc.BEURange.base, soc.BEURange.mask.toInt + 1)
80  ))
81
82  val i_mmio_port = TLTempNode()
83  val d_mmio_port = TLTempNode()
84
85  val misc_l2_pmu = BusPerfMonitor(name = "Misc_L2", enable = !debugOpts.FPGAPlatform) // l1D & l1I & PTW
86  val l2_l3_pmu = BusPerfMonitor(name = "L2_L3", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
87  val xbar_l2_buffer = TLBuffer()
88
89  val enbale_tllog = !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB
90  val l1d_logger = TLLogger(s"L2_L1D_${coreParams.HartId}", enbale_tllog)
91  val l1i_logger = TLLogger(s"L2_L1I_${coreParams.HartId}", enbale_tllog)
92  val ptw_logger = TLLogger(s"L2_PTW_${coreParams.HartId}", enbale_tllog)
93  val ptw_to_l2_buffer = LazyModule(new TLBuffer)
94  val i_mmio_buffer = LazyModule(new TLBuffer)
95
96  val clint_int_node = IntIdentityNode()
97  val debug_int_node = IntIdentityNode()
98  val plic_int_node = IntIdentityNode()
99  val nmi_int_node = IntIdentityNode()
100
101  println(s"enableCHI: ${enableCHI}")
102  val l2cache = if (enableL2) {
103    val config = new Config((_, _, _) => {
104      case L2ParamKey => coreParams.L2CacheParamsOpt.get.copy(
105        hartId = p(XSCoreParamsKey).HartId,
106        FPGAPlatform = debugOpts.FPGAPlatform
107      )
108      case EnableCHI => p(EnableCHI)
109      case CHIIssue => p(CHIIssue)
110      case BankBitsKey => log2Ceil(coreParams.L2NBanks)
111      case MaxHartIdBits => p(MaxHartIdBits)
112      case LogUtilsOptionsKey => p(LogUtilsOptionsKey)
113      case PerfCounterOptionsKey => p(PerfCounterOptionsKey)
114    })
115    if (enableCHI) Some(LazyModule(new TL2CHICoupledL2()(new Config(config))))
116    else Some(LazyModule(new TL2TLCoupledL2()(new Config(config))))
117  } else None
118  val l2_binder = coreParams.L2CacheParamsOpt.map(_ => BankBinder(coreParams.L2NBanks, 64))
119
120  // =========== Connection ============
121  // l2 to l2_binder, then to memory_port
122  l2cache match {
123    case Some(l2) =>
124      l2_binder.get :*= l2.node :*= xbar_l2_buffer :*= l1_xbar :=* misc_l2_pmu
125      l2 match {
126        case l2: TL2TLCoupledL2 =>
127          memory_port.get := l2_l3_pmu := TLClientsMerger() := TLXbar() :=* l2_binder.get
128        case l2: TL2CHICoupledL2 =>
129          l2.managerNode := TLXbar() :=* l2_binder.get
130          l2.mmioNode := mmio_port
131      }
132    case None =>
133      memory_port.get := l1_xbar
134  }
135
136  mmio_xbar := TLBuffer.chainNode(2) := i_mmio_port
137  mmio_xbar := TLBuffer.chainNode(2) := d_mmio_port
138  beu.node := TLBuffer.chainNode(1) := mmio_xbar
139  mmio_port := TLBuffer() := mmio_xbar
140
141  class Imp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
142    val io = IO(new Bundle {
143      val beu_errors = Input(chiselTypeOf(beu.module.io.errors))
144      val reset_vector = new Bundle {
145        val fromTile = Input(UInt(PAddrBits.W))
146        val toCore = Output(UInt(PAddrBits.W))
147      }
148      val hartId = new Bundle() {
149        val fromTile = Input(UInt(64.W))
150        val toCore = Output(UInt(64.W))
151      }
152      val cpu_halt = new Bundle() {
153        val fromCore = Input(Bool())
154        val toTile = Output(Bool())
155      }
156      val hartIsInReset = new Bundle() {
157        val resetInFrontend = Input(Bool())
158        val toTile = Output(Bool())
159      }
160      val debugTopDown = new Bundle() {
161        val robTrueCommit = Input(UInt(64.W))
162        val robHeadPaddr = Flipped(Valid(UInt(36.W)))
163        val l2MissMatch = Output(Bool())
164      }
165      val chi = if (enableCHI) Some(new PortIO) else None
166      val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None
167      val l2_tlb_req = new TlbRequestIO(nRespDups = 2)
168      val l2_pmp_resp = Flipped(new PMPRespBundle)
169      val l2_hint = ValidIO(new L2ToL1Hint())
170      val perfEvents = Output(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent))
171      // val reset_core = IO(Output(Reset()))
172    })
173
174    val resetDelayN = Module(new DelayN(UInt(PAddrBits.W), 5))
175
176    beu.module.io.errors <> io.beu_errors
177    resetDelayN.io.in := io.reset_vector.fromTile
178    io.reset_vector.toCore := resetDelayN.io.out
179    io.hartId.toCore := io.hartId.fromTile
180    io.cpu_halt.toTile := io.cpu_halt.fromCore
181    dontTouch(io.hartId)
182    dontTouch(io.cpu_halt)
183    if (!io.chi.isEmpty) { dontTouch(io.chi.get) }
184
185    val hartIsInReset = RegInit(true.B)
186    hartIsInReset := io.hartIsInReset.resetInFrontend || reset.asBool
187    io.hartIsInReset.toTile := hartIsInReset
188
189    if (l2cache.isDefined) {
190      val l2 = l2cache.get.module
191      io.l2_hint := l2.io.l2_hint
192      l2.io.debugTopDown.robHeadPaddr := DontCare
193      l2.io.hartId := io.hartId.fromTile
194      l2.io.debugTopDown.robHeadPaddr := io.debugTopDown.robHeadPaddr
195      l2.io.debugTopDown.robTrueCommit := io.debugTopDown.robTrueCommit
196      io.debugTopDown.l2MissMatch := l2.io.debugTopDown.l2MissMatch
197
198      /* l2 tlb */
199      io.l2_tlb_req.req.bits := DontCare
200      io.l2_tlb_req.req.valid := l2.io.l2_tlb_req.req.valid
201      io.l2_tlb_req.resp.ready := l2.io.l2_tlb_req.resp.ready
202      io.l2_tlb_req.req.bits.vaddr := l2.io.l2_tlb_req.req.bits.vaddr
203      io.l2_tlb_req.req.bits.cmd := l2.io.l2_tlb_req.req.bits.cmd
204      io.l2_tlb_req.req.bits.size := l2.io.l2_tlb_req.req.bits.size
205      io.l2_tlb_req.req.bits.kill := l2.io.l2_tlb_req.req.bits.kill
206      io.l2_tlb_req.req.bits.no_translate := l2.io.l2_tlb_req.req.bits.no_translate
207      io.l2_tlb_req.req_kill := l2.io.l2_tlb_req.req_kill
208      io.perfEvents := l2.io_perf
209
210      val allPerfEvents = l2.getPerfEvents
211      if (printEventCoding) {
212        for (((name, inc), i) <- allPerfEvents.zipWithIndex) {
213          println("L2 Cache perfEvents Set", name, inc, i)
214        }
215      }
216
217      l2.io.l2_tlb_req.resp.valid := io.l2_tlb_req.resp.valid
218      l2.io.l2_tlb_req.req.ready := io.l2_tlb_req.req.ready
219      l2.io.l2_tlb_req.resp.bits.paddr.head := io.l2_tlb_req.resp.bits.paddr.head
220      l2.io.l2_tlb_req.resp.bits.pbmt := io.l2_tlb_req.resp.bits.pbmt.head
221      l2.io.l2_tlb_req.resp.bits.miss := io.l2_tlb_req.resp.bits.miss
222      l2.io.l2_tlb_req.resp.bits.excp.head.gpf := io.l2_tlb_req.resp.bits.excp.head.gpf
223      l2.io.l2_tlb_req.resp.bits.excp.head.pf := io.l2_tlb_req.resp.bits.excp.head.pf
224      l2.io.l2_tlb_req.resp.bits.excp.head.af := io.l2_tlb_req.resp.bits.excp.head.af
225      l2.io.l2_tlb_req.pmp_resp.ld := io.l2_pmp_resp.ld
226      l2.io.l2_tlb_req.pmp_resp.st := io.l2_pmp_resp.st
227      l2.io.l2_tlb_req.pmp_resp.instr := io.l2_pmp_resp.instr
228      l2.io.l2_tlb_req.pmp_resp.mmio := io.l2_pmp_resp.mmio
229      l2.io.l2_tlb_req.pmp_resp.atomic := io.l2_pmp_resp.atomic
230      l2cache.get match {
231        case l2cache: TL2CHICoupledL2 =>
232          val l2 = l2cache.module
233          l2.io_nodeID := io.nodeID.get
234          io.chi.get <> l2.io_chi
235        case l2cache: TL2TLCoupledL2 =>
236      }
237    } else {
238      io.l2_hint := 0.U.asTypeOf(io.l2_hint)
239      io.debugTopDown <> DontCare
240
241      io.l2_tlb_req.req.valid := false.B
242      io.l2_tlb_req.req.bits := DontCare
243      io.l2_tlb_req.req_kill := DontCare
244      io.l2_tlb_req.resp.ready := true.B
245      io.perfEvents := DontCare
246    }
247  }
248
249  lazy val module = new Imp(this)
250}
251
252class L2Top()(implicit p: Parameters) extends LazyModule
253  with HasXSParameter
254  with HasSoCParameter {
255
256  override def shouldBeInlined: Boolean = false
257
258  val inner = LazyModule(new L2TopInlined())
259
260  class Imp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
261    val io = IO(inner.module.io.cloneType)
262    val reset_core = IO(Output(Reset()))
263    io <> inner.module.io
264
265    if (debugOpts.ResetGen) {
266      ResetGen(ResetGenNode(Seq(
267        CellNode(reset_core),
268        ModuleNode(inner.module)
269      )), reset, sim = false)
270    } else {
271      reset_core := DontCare
272    }
273  }
274
275  lazy val module = new Imp(this)
276}