1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan 18 19import chisel3._ 20import chisel3.util._ 21import org.chipsalliance.cde.config._ 22import chisel3.util.{Valid, ValidIO} 23import freechips.rocketchip.diplomacy._ 24import freechips.rocketchip.interrupts._ 25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, MaxHartIdBits} 26import freechips.rocketchip.tilelink._ 27import coupledL2.{L2ParamKey, EnableCHI} 28import coupledL2.tl2tl.TL2TLCoupledL2 29import coupledL2.tl2chi.{TL2CHICoupledL2, PortIO, CHIIssue} 30import huancun.BankBitsKey 31import system.HasSoCParameter 32import top.BusPerfMonitor 33import utility._ 34import xiangshan.cache.mmu.TlbRequestIO 35import xiangshan.backend.fu.PMPRespBundle 36 37class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter { 38 val ecc_error = Valid(UInt(soc.PAddrBits.W)) 39} 40 41class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors { 42 val icache = new L1BusErrorUnitInfo 43 val dcache = new L1BusErrorUnitInfo 44 val l2 = new L1BusErrorUnitInfo 45 46 override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] = 47 List( 48 Some(icache.ecc_error, "I_ECC", "Icache ecc error"), 49 Some(dcache.ecc_error, "D_ECC", "Dcache ecc error"), 50 Some(l2.ecc_error, "L2_ECC", "L2Cache ecc error") 51 ) 52} 53 54/** 55 * L2Top contains everything between Core and XSTile-IO 56 */ 57class L2Top()(implicit p: Parameters) extends LazyModule 58 with HasXSParameter 59 with HasSoCParameter 60{ 61 def chainBuffer(depth: Int, n: String): (Seq[LazyModule], TLNode) = { 62 val buffers = Seq.fill(depth){ LazyModule(new TLBuffer()) } 63 buffers.zipWithIndex.foreach{ case (b, i) => { 64 b.suggestName(s"${n}_${i}") 65 }} 66 val node = buffers.map(_.node.asInstanceOf[TLNode]).reduce(_ :*=* _) 67 (buffers, node) 68 } 69 val enableL2 = coreParams.L2CacheParamsOpt.isDefined 70 // =========== Components ============ 71 val l1_xbar = TLXbar() 72 val mmio_xbar = TLXbar() 73 val mmio_port = TLIdentityNode() // to L3 74 val memory_port = if (enableCHI && enableL2) None else Some(TLIdentityNode()) 75 val beu = LazyModule(new BusErrorUnit( 76 new XSL1BusErrors(), BusErrorUnitParams(0x38010000) 77 )) 78 79 val i_mmio_port = TLTempNode() 80 val d_mmio_port = TLTempNode() 81 82 val misc_l2_pmu = BusPerfMonitor(name = "Misc_L2", enable = !debugOpts.FPGAPlatform) // l1D & l1I & PTW 83 val l2_l3_pmu = BusPerfMonitor(name = "L2_L3", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true) 84 val xbar_l2_buffer = TLBuffer() 85 86 val enbale_tllog = !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB 87 val l1d_logger = TLLogger(s"L2_L1D_${coreParams.HartId}", enbale_tllog) 88 val l1i_logger = TLLogger(s"L2_L1I_${coreParams.HartId}", enbale_tllog) 89 val ptw_logger = TLLogger(s"L2_PTW_${coreParams.HartId}", enbale_tllog) 90 val ptw_to_l2_buffer = LazyModule(new TLBuffer) 91 val i_mmio_buffer = LazyModule(new TLBuffer) 92 93 val clint_int_node = IntIdentityNode() 94 val debug_int_node = IntIdentityNode() 95 val plic_int_node = IntIdentityNode() 96 97 println(s"enableCHI: ${enableCHI}") 98 val l2cache = if (enableL2) { 99 val config = new Config((_, _, _) => { 100 case L2ParamKey => coreParams.L2CacheParamsOpt.get.copy( 101 hartId = p(XSCoreParamsKey).HartId, 102 FPGAPlatform = debugOpts.FPGAPlatform 103 ) 104 case EnableCHI => p(EnableCHI) 105 case CHIIssue => p(CHIIssue) 106 case BankBitsKey => log2Ceil(coreParams.L2NBanks) 107 case MaxHartIdBits => p(MaxHartIdBits) 108 case LogUtilsOptionsKey => p(LogUtilsOptionsKey) 109 case PerfCounterOptionsKey => p(PerfCounterOptionsKey) 110 }) 111 if (enableCHI) Some(LazyModule(new TL2CHICoupledL2()(new Config(config)))) 112 else Some(LazyModule(new TL2TLCoupledL2()(new Config(config)))) 113 } else None 114 val l2_binder = coreParams.L2CacheParamsOpt.map(_ => BankBinder(coreParams.L2NBanks, 64)) 115 116 // =========== Connection ============ 117 // l2 to l2_binder, then to memory_port 118 l2cache match { 119 case Some(l2) => 120 l2_binder.get :*= l2.node :*= xbar_l2_buffer :*= l1_xbar :=* misc_l2_pmu 121 l2 match { 122 case l2: TL2TLCoupledL2 => 123 memory_port.get := l2_l3_pmu := TLClientsMerger() := TLXbar() :=* l2_binder.get 124 case l2: TL2CHICoupledL2 => 125 l2.managerNode := TLXbar() :=* l2_binder.get 126 l2.mmioNode := mmio_port 127 } 128 case None => 129 memory_port.get := l1_xbar 130 } 131 132 mmio_xbar := TLBuffer.chainNode(2) := i_mmio_port 133 mmio_xbar := TLBuffer.chainNode(2) := d_mmio_port 134 beu.node := TLBuffer.chainNode(1) := mmio_xbar 135 mmio_port := TLBuffer() := mmio_xbar 136 137 class L2TopImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 138 val beu_errors = IO(Input(chiselTypeOf(beu.module.io.errors))) 139 val reset_vector = IO(new Bundle { 140 val fromTile = Input(UInt(PAddrBits.W)) 141 val toCore = Output(UInt(PAddrBits.W)) 142 }) 143 val hartId = IO(new Bundle() { 144 val fromTile = Input(UInt(64.W)) 145 val toCore = Output(UInt(64.W)) 146 }) 147 val cpu_halt = IO(new Bundle() { 148 val fromCore = Input(Bool()) 149 val toTile = Output(Bool()) 150 }) 151 val debugTopDown = IO(new Bundle() { 152 val robTrueCommit = Input(UInt(64.W)) 153 val robHeadPaddr = Flipped(Valid(UInt(36.W))) 154 val l2MissMatch = Output(Bool()) 155 }) 156 val chi = if (enableCHI) Some(IO(new PortIO)) else None 157 val nodeID = if (enableCHI) Some(IO(Input(UInt(NodeIDWidth.W)))) else None 158 val l2_tlb_req = IO(new TlbRequestIO(nRespDups = 2)) 159 val l2_pmp_resp = IO(Flipped(new PMPRespBundle)) 160 val l2_hint = IO(ValidIO(new L2ToL1Hint())) 161 val reset_core = IO(Output(Reset())) 162 163 val resetDelayN = Module(new DelayN(UInt(PAddrBits.W), 5)) 164 165 beu.module.io.errors <> beu_errors 166 resetDelayN.io.in := reset_vector.fromTile 167 reset_vector.toCore := resetDelayN.io.out 168 hartId.toCore := hartId.fromTile 169 cpu_halt.toTile := cpu_halt.fromCore 170 dontTouch(hartId) 171 dontTouch(cpu_halt) 172 if (!chi.isEmpty) { dontTouch(chi.get) } 173 174 if (l2cache.isDefined) { 175 val l2 = l2cache.get.module 176 l2_hint := l2.io.l2_hint 177 l2.io.debugTopDown.robHeadPaddr := DontCare 178 l2.io.hartId := hartId.fromTile 179 l2.io.debugTopDown.robHeadPaddr := debugTopDown.robHeadPaddr 180 l2.io.debugTopDown.robTrueCommit := debugTopDown.robTrueCommit 181 debugTopDown.l2MissMatch := l2.io.debugTopDown.l2MissMatch 182 183 /* l2 tlb */ 184 l2_tlb_req.req.bits := DontCare 185 l2_tlb_req.req.valid := l2.io.l2_tlb_req.req.valid 186 l2_tlb_req.resp.ready := l2.io.l2_tlb_req.resp.ready 187 l2_tlb_req.req.bits.vaddr := l2.io.l2_tlb_req.req.bits.vaddr 188 l2_tlb_req.req.bits.cmd := l2.io.l2_tlb_req.req.bits.cmd 189 l2_tlb_req.req.bits.size := l2.io.l2_tlb_req.req.bits.size 190 l2_tlb_req.req.bits.kill := l2.io.l2_tlb_req.req.bits.kill 191 l2_tlb_req.req.bits.no_translate := l2.io.l2_tlb_req.req.bits.no_translate 192 l2_tlb_req.req_kill := l2.io.l2_tlb_req.req_kill 193 l2.io.l2_tlb_req.resp.valid := l2_tlb_req.resp.valid 194 l2.io.l2_tlb_req.req.ready := l2_tlb_req.req.ready 195 l2.io.l2_tlb_req.resp.bits.paddr.head := l2_tlb_req.resp.bits.paddr.head 196 l2.io.l2_tlb_req.resp.bits.miss := l2_tlb_req.resp.bits.miss 197 l2.io.l2_tlb_req.resp.bits.excp.head <> l2_tlb_req.resp.bits.excp.head 198 l2.io.l2_tlb_req.pmp_resp.ld := l2_pmp_resp.ld 199 l2.io.l2_tlb_req.pmp_resp.st := l2_pmp_resp.st 200 l2.io.l2_tlb_req.pmp_resp.instr := l2_pmp_resp.instr 201 l2.io.l2_tlb_req.pmp_resp.mmio := l2_pmp_resp.mmio 202 l2.io.l2_tlb_req.pmp_resp.atomic := l2_pmp_resp.atomic 203 l2cache.get match { 204 case l2cache: TL2CHICoupledL2 => 205 val l2 = l2cache.module 206 l2.io_nodeID := nodeID.get 207 chi.get <> l2.io_chi 208 case l2cache: TL2TLCoupledL2 => 209 } 210 } else { 211 l2_hint := 0.U.asTypeOf(l2_hint) 212 debugTopDown <> DontCare 213 214 l2_tlb_req.req.valid := false.B 215 l2_tlb_req.req.bits := DontCare 216 l2_tlb_req.req_kill := DontCare 217 l2_tlb_req.resp.ready := true.B 218 } 219 220 if (debugOpts.ResetGen) { 221 val resetTree = ResetGenNode(Seq(CellNode(reset_core))) 222 ResetGen(resetTree, reset, sim = false) 223 } else { 224 reset_core := DontCare 225 } 226 } 227 228 lazy val module = new L2TopImp(this) 229} 230