1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan 18 19import chisel3._ 20import chisel3.util._ 21import org.chipsalliance.cde.config._ 22import chisel3.util.{Valid, ValidIO} 23import freechips.rocketchip.diplomacy._ 24import freechips.rocketchip.interrupts._ 25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, MaxHartIdBits} 26import freechips.rocketchip.tilelink._ 27import coupledL2.{L2ParamKey, EnableCHI} 28import coupledL2.tl2tl.TL2TLCoupledL2 29import coupledL2.tl2chi.{TL2CHICoupledL2, PortIO, CHIIssue} 30import huancun.BankBitsKey 31import system.HasSoCParameter 32import top.BusPerfMonitor 33import utility._ 34import xiangshan.cache.mmu.TlbRequestIO 35import xiangshan.backend.fu.PMPRespBundle 36 37class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter { 38 val ecc_error = Valid(UInt(soc.PAddrBits.W)) 39} 40 41class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors { 42 val icache = new L1BusErrorUnitInfo 43 val dcache = new L1BusErrorUnitInfo 44 val l2 = new L1BusErrorUnitInfo 45 46 override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] = 47 List( 48 Some(icache.ecc_error, "I_ECC", "Icache ecc error"), 49 Some(dcache.ecc_error, "D_ECC", "Dcache ecc error"), 50 Some(l2.ecc_error, "L2_ECC", "L2Cache ecc error") 51 ) 52} 53 54/** 55 * L2Top contains everything between Core and XSTile-IO 56 */ 57class L2TopInlined()(implicit p: Parameters) extends LazyModule 58 with HasXSParameter 59 with HasSoCParameter 60{ 61 override def shouldBeInlined: Boolean = true 62 63 def chainBuffer(depth: Int, n: String): (Seq[LazyModule], TLNode) = { 64 val buffers = Seq.fill(depth){ LazyModule(new TLBuffer()) } 65 buffers.zipWithIndex.foreach{ case (b, i) => { 66 b.suggestName(s"${n}_${i}") 67 }} 68 val node = buffers.map(_.node.asInstanceOf[TLNode]).reduce(_ :*=* _) 69 (buffers, node) 70 } 71 val enableL2 = coreParams.L2CacheParamsOpt.isDefined 72 // =========== Components ============ 73 val l1_xbar = TLXbar() 74 val mmio_xbar = TLXbar() 75 val mmio_port = TLIdentityNode() // to L3 76 val memory_port = if (enableCHI && enableL2) None else Some(TLIdentityNode()) 77 val beu = LazyModule(new BusErrorUnit( 78 new XSL1BusErrors(), BusErrorUnitParams(0x38010000) 79 )) 80 81 val i_mmio_port = TLTempNode() 82 val d_mmio_port = TLTempNode() 83 84 val misc_l2_pmu = BusPerfMonitor(name = "Misc_L2", enable = !debugOpts.FPGAPlatform) // l1D & l1I & PTW 85 val l2_l3_pmu = BusPerfMonitor(name = "L2_L3", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true) 86 val xbar_l2_buffer = TLBuffer() 87 88 val enbale_tllog = !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB 89 val l1d_logger = TLLogger(s"L2_L1D_${coreParams.HartId}", enbale_tllog) 90 val l1i_logger = TLLogger(s"L2_L1I_${coreParams.HartId}", enbale_tllog) 91 val ptw_logger = TLLogger(s"L2_PTW_${coreParams.HartId}", enbale_tllog) 92 val ptw_to_l2_buffer = LazyModule(new TLBuffer) 93 val i_mmio_buffer = LazyModule(new TLBuffer) 94 95 val clint_int_node = IntIdentityNode() 96 val debug_int_node = IntIdentityNode() 97 val plic_int_node = IntIdentityNode() 98 val nmi_int_node = IntIdentityNode() 99 100 println(s"enableCHI: ${enableCHI}") 101 val l2cache = if (enableL2) { 102 val config = new Config((_, _, _) => { 103 case L2ParamKey => coreParams.L2CacheParamsOpt.get.copy( 104 hartId = p(XSCoreParamsKey).HartId, 105 FPGAPlatform = debugOpts.FPGAPlatform 106 ) 107 case EnableCHI => p(EnableCHI) 108 case CHIIssue => p(CHIIssue) 109 case BankBitsKey => log2Ceil(coreParams.L2NBanks) 110 case MaxHartIdBits => p(MaxHartIdBits) 111 case LogUtilsOptionsKey => p(LogUtilsOptionsKey) 112 case PerfCounterOptionsKey => p(PerfCounterOptionsKey) 113 }) 114 if (enableCHI) Some(LazyModule(new TL2CHICoupledL2()(new Config(config)))) 115 else Some(LazyModule(new TL2TLCoupledL2()(new Config(config)))) 116 } else None 117 val l2_binder = coreParams.L2CacheParamsOpt.map(_ => BankBinder(coreParams.L2NBanks, 64)) 118 119 // =========== Connection ============ 120 // l2 to l2_binder, then to memory_port 121 l2cache match { 122 case Some(l2) => 123 l2_binder.get :*= l2.node :*= xbar_l2_buffer :*= l1_xbar :=* misc_l2_pmu 124 l2 match { 125 case l2: TL2TLCoupledL2 => 126 memory_port.get := l2_l3_pmu := TLClientsMerger() := TLXbar() :=* l2_binder.get 127 case l2: TL2CHICoupledL2 => 128 l2.managerNode := TLXbar() :=* l2_binder.get 129 l2.mmioNode := mmio_port 130 } 131 case None => 132 memory_port.get := l1_xbar 133 } 134 135 mmio_xbar := TLBuffer.chainNode(2) := i_mmio_port 136 mmio_xbar := TLBuffer.chainNode(2) := d_mmio_port 137 beu.node := TLBuffer.chainNode(1) := mmio_xbar 138 mmio_port := TLBuffer() := mmio_xbar 139 140 class Imp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 141 val io = IO(new Bundle { 142 val beu_errors = Input(chiselTypeOf(beu.module.io.errors)) 143 val reset_vector = new Bundle { 144 val fromTile = Input(UInt(PAddrBits.W)) 145 val toCore = Output(UInt(PAddrBits.W)) 146 } 147 val hartId = new Bundle() { 148 val fromTile = Input(UInt(64.W)) 149 val toCore = Output(UInt(64.W)) 150 } 151 val cpu_halt = new Bundle() { 152 val fromCore = Input(Bool()) 153 val toTile = Output(Bool()) 154 } 155 val hartIsInReset = new Bundle() { 156 val resetInFrontend = Input(Bool()) 157 val toTile = Output(Bool()) 158 } 159 val debugTopDown = new Bundle() { 160 val robTrueCommit = Input(UInt(64.W)) 161 val robHeadPaddr = Flipped(Valid(UInt(36.W))) 162 val l2MissMatch = Output(Bool()) 163 } 164 val chi = if (enableCHI) Some(new PortIO) else None 165 val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None 166 val l2_tlb_req = new TlbRequestIO(nRespDups = 2) 167 val l2_pmp_resp = Flipped(new PMPRespBundle) 168 val l2_hint = ValidIO(new L2ToL1Hint()) 169 // val reset_core = IO(Output(Reset())) 170 }) 171 172 val resetDelayN = Module(new DelayN(UInt(PAddrBits.W), 5)) 173 174 beu.module.io.errors <> io.beu_errors 175 resetDelayN.io.in := io.reset_vector.fromTile 176 io.reset_vector.toCore := resetDelayN.io.out 177 io.hartId.toCore := io.hartId.fromTile 178 io.cpu_halt.toTile := io.cpu_halt.fromCore 179 dontTouch(io.hartId) 180 dontTouch(io.cpu_halt) 181 if (!io.chi.isEmpty) { dontTouch(io.chi.get) } 182 183 val hartIsInReset = RegInit(true.B) 184 hartIsInReset := io.hartIsInReset.resetInFrontend || reset.asBool 185 io.hartIsInReset.toTile := hartIsInReset 186 187 if (l2cache.isDefined) { 188 val l2 = l2cache.get.module 189 io.l2_hint := l2.io.l2_hint 190 l2.io.debugTopDown.robHeadPaddr := DontCare 191 l2.io.hartId := io.hartId.fromTile 192 l2.io.debugTopDown.robHeadPaddr := io.debugTopDown.robHeadPaddr 193 l2.io.debugTopDown.robTrueCommit := io.debugTopDown.robTrueCommit 194 io.debugTopDown.l2MissMatch := l2.io.debugTopDown.l2MissMatch 195 196 /* l2 tlb */ 197 io.l2_tlb_req.req.bits := DontCare 198 io.l2_tlb_req.req.valid := l2.io.l2_tlb_req.req.valid 199 io.l2_tlb_req.resp.ready := l2.io.l2_tlb_req.resp.ready 200 io.l2_tlb_req.req.bits.vaddr := l2.io.l2_tlb_req.req.bits.vaddr 201 io.l2_tlb_req.req.bits.cmd := l2.io.l2_tlb_req.req.bits.cmd 202 io.l2_tlb_req.req.bits.size := l2.io.l2_tlb_req.req.bits.size 203 io.l2_tlb_req.req.bits.kill := l2.io.l2_tlb_req.req.bits.kill 204 io.l2_tlb_req.req.bits.no_translate := l2.io.l2_tlb_req.req.bits.no_translate 205 io.l2_tlb_req.req_kill := l2.io.l2_tlb_req.req_kill 206 l2.io.l2_tlb_req.resp.valid := io.l2_tlb_req.resp.valid 207 l2.io.l2_tlb_req.req.ready := io.l2_tlb_req.req.ready 208 l2.io.l2_tlb_req.resp.bits.paddr.head := io.l2_tlb_req.resp.bits.paddr.head 209 l2.io.l2_tlb_req.resp.bits.pbmt := io.l2_tlb_req.resp.bits.pbmt.head 210 l2.io.l2_tlb_req.resp.bits.miss := io.l2_tlb_req.resp.bits.miss 211 l2.io.l2_tlb_req.resp.bits.excp.head.gpf := io.l2_tlb_req.resp.bits.excp.head.gpf 212 l2.io.l2_tlb_req.resp.bits.excp.head.pf := io.l2_tlb_req.resp.bits.excp.head.pf 213 l2.io.l2_tlb_req.resp.bits.excp.head.af := io.l2_tlb_req.resp.bits.excp.head.af 214 l2.io.l2_tlb_req.pmp_resp.ld := io.l2_pmp_resp.ld 215 l2.io.l2_tlb_req.pmp_resp.st := io.l2_pmp_resp.st 216 l2.io.l2_tlb_req.pmp_resp.instr := io.l2_pmp_resp.instr 217 l2.io.l2_tlb_req.pmp_resp.mmio := io.l2_pmp_resp.mmio 218 l2.io.l2_tlb_req.pmp_resp.atomic := io.l2_pmp_resp.atomic 219 l2cache.get match { 220 case l2cache: TL2CHICoupledL2 => 221 val l2 = l2cache.module 222 l2.io_nodeID := io.nodeID.get 223 io.chi.get <> l2.io_chi 224 case l2cache: TL2TLCoupledL2 => 225 } 226 } else { 227 io.l2_hint := 0.U.asTypeOf(io.l2_hint) 228 io.debugTopDown <> DontCare 229 230 io.l2_tlb_req.req.valid := false.B 231 io.l2_tlb_req.req.bits := DontCare 232 io.l2_tlb_req.req_kill := DontCare 233 io.l2_tlb_req.resp.ready := true.B 234 } 235 } 236 237 lazy val module = new Imp(this) 238} 239 240class L2Top()(implicit p: Parameters) extends LazyModule 241 with HasXSParameter 242 with HasSoCParameter { 243 244 override def shouldBeInlined: Boolean = false 245 246 val inner = LazyModule(new L2TopInlined()) 247 248 class Imp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 249 val io = IO(inner.module.io.cloneType) 250 val reset_core = IO(Output(Reset())) 251 io <> inner.module.io 252 253 if (debugOpts.ResetGen) { 254 ResetGen(ResetGenNode(Seq( 255 CellNode(reset_core), 256 ModuleNode(inner.module) 257 )), reset, sim = false) 258 } else { 259 reset_core := DontCare 260 } 261 } 262 263 lazy val module = new Imp(this) 264}