xref: /XiangShan/src/main/scala/xiangshan/L2Top.scala (revision 1697a48eea0de9d216d8fa7537d967f8ef351e49) 
1/***************************************************************************************
2  * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3  * Copyright (c) 2020-2021 Peng Cheng Laboratory
4  *
5  * XiangShan is licensed under Mulan PSL v2.
6  * You can use this software according to the terms and conditions of the Mulan PSL v2.
7  * You may obtain a copy of Mulan PSL v2 at:
8  *          http://license.coscl.org.cn/MulanPSL2
9  *
10  * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11  * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12  * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13  *
14  * See the Mulan PSL v2 for more details.
15  ***************************************************************************************/
16
17package xiangshan
18
19import chisel3._
20import chisel3.util._
21import org.chipsalliance.cde.config._
22import chisel3.util.{Valid, ValidIO}
23import freechips.rocketchip.diplomacy._
24import freechips.rocketchip.interrupts._
25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, MaxHartIdBits}
26import freechips.rocketchip.tilelink._
27import coupledL2.{L2ParamKey, EnableCHI}
28import coupledL2.tl2tl.TL2TLCoupledL2
29import coupledL2.tl2chi.{TL2CHICoupledL2, PortIO, CHIIssue}
30import huancun.BankBitsKey
31import system.HasSoCParameter
32import top.BusPerfMonitor
33import utility._
34import xiangshan.cache.mmu.TlbRequestIO
35import xiangshan.backend.fu.PMPRespBundle
36import xiangshan.backend.trace.{Itype, TraceCoreInterface}
37
38class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {
39  val ecc_error = Valid(UInt(soc.PAddrBits.W))
40}
41
42class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors {
43  val icache = new L1BusErrorUnitInfo
44  val dcache = new L1BusErrorUnitInfo
45  val l2 = new L1BusErrorUnitInfo
46
47  override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] =
48    List(
49      Some(icache.ecc_error, "I_ECC", "Icache ecc error"),
50      Some(dcache.ecc_error, "D_ECC", "Dcache ecc error"),
51      Some(l2.ecc_error, "L2_ECC", "L2Cache ecc error")
52    )
53}
54
55/**
56  *   L2Top contains everything between Core and XSTile-IO
57  */
58class L2TopInlined()(implicit p: Parameters) extends LazyModule
59  with HasXSParameter
60  with HasSoCParameter
61{
62  override def shouldBeInlined: Boolean = true
63
64  def chainBuffer(depth: Int, n: String): (Seq[LazyModule], TLNode) = {
65    val buffers = Seq.fill(depth){ LazyModule(new TLBuffer()) }
66    buffers.zipWithIndex.foreach{ case (b, i) => {
67      b.suggestName(s"${n}_${i}")
68    }}
69    val node = buffers.map(_.node.asInstanceOf[TLNode]).reduce(_ :*=* _)
70    (buffers, node)
71  }
72  val enableL2 = coreParams.L2CacheParamsOpt.isDefined
73  // =========== Components ============
74  val l1_xbar = TLXbar()
75  val mmio_xbar = TLXbar()
76  val mmio_port = TLIdentityNode() // to L3
77  val memory_port = if (enableCHI && enableL2) None else Some(TLIdentityNode())
78  val beu = LazyModule(new BusErrorUnit(
79    new XSL1BusErrors(),
80    BusErrorUnitParams(soc.BEURange.base, soc.BEURange.mask.toInt + 1)
81  ))
82
83  val i_mmio_port = TLTempNode()
84  val icachectrl_port_opt = if(icacheParameters.cacheCtrlAddressOpt.nonEmpty) Option(TLTempNode()) else None
85  val d_mmio_port = TLTempNode()
86
87  val misc_l2_pmu = BusPerfMonitor(name = "Misc_L2", enable = !debugOpts.FPGAPlatform) // l1D & l1I & PTW
88  val l2_l3_pmu = BusPerfMonitor(name = "L2_L3", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
89  val xbar_l2_buffer = TLBuffer()
90
91  val enbale_tllog = !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB
92  val l1d_logger = TLLogger(s"L2_L1D_${coreParams.HartId}", enbale_tllog)
93  val l1i_logger = TLLogger(s"L2_L1I_${coreParams.HartId}", enbale_tllog)
94  val ptw_logger = TLLogger(s"L2_PTW_${coreParams.HartId}", enbale_tllog)
95  val ptw_to_l2_buffer = LazyModule(new TLBuffer)
96  val i_mmio_buffer = LazyModule(new TLBuffer)
97
98  val clint_int_node = IntIdentityNode()
99  val debug_int_node = IntIdentityNode()
100  val plic_int_node = IntIdentityNode()
101  val nmi_int_node = IntIdentityNode()
102
103  println(s"enableCHI: ${enableCHI}")
104  val l2cache = if (enableL2) {
105    val config = new Config((_, _, _) => {
106      case L2ParamKey => coreParams.L2CacheParamsOpt.get.copy(
107        hartId = p(XSCoreParamsKey).HartId,
108        FPGAPlatform = debugOpts.FPGAPlatform
109      )
110      case EnableCHI => p(EnableCHI)
111      case CHIIssue => p(CHIIssue)
112      case BankBitsKey => log2Ceil(coreParams.L2NBanks)
113      case MaxHartIdBits => p(MaxHartIdBits)
114      case LogUtilsOptionsKey => p(LogUtilsOptionsKey)
115      case PerfCounterOptionsKey => p(PerfCounterOptionsKey)
116    })
117    if (enableCHI) Some(LazyModule(new TL2CHICoupledL2()(new Config(config))))
118    else Some(LazyModule(new TL2TLCoupledL2()(new Config(config))))
119  } else None
120  val l2_binder = coreParams.L2CacheParamsOpt.map(_ => BankBinder(coreParams.L2NBanks, 64))
121
122  // =========== Connection ============
123  // l2 to l2_binder, then to memory_port
124  l2cache match {
125    case Some(l2) =>
126      l2_binder.get :*= l2.node :*= xbar_l2_buffer :*= l1_xbar :=* misc_l2_pmu
127      l2 match {
128        case l2: TL2TLCoupledL2 =>
129          memory_port.get := l2_l3_pmu := TLClientsMerger() := TLXbar() :=* l2_binder.get
130        case l2: TL2CHICoupledL2 =>
131          l2.managerNode := TLXbar() :=* l2_binder.get
132          l2.mmioNode := mmio_port
133      }
134    case None =>
135      memory_port.get := l1_xbar
136  }
137
138  mmio_xbar := TLBuffer.chainNode(2) := i_mmio_port
139  mmio_xbar := TLBuffer.chainNode(2) := d_mmio_port
140  beu.node := TLBuffer.chainNode(1) := mmio_xbar
141  if (icacheParameters.cacheCtrlAddressOpt.nonEmpty) {
142    icachectrl_port_opt.get := TLBuffer.chainNode(1) := mmio_xbar
143  }
144
145  // filter out in-core addresses before sent to mmio_port
146  // Option[AddressSet] ++ Option[AddressSet] => List[AddressSet]
147  private def mmioFilters: Seq[AddressSet] =
148    (icacheParameters.cacheCtrlAddressOpt ++ dcacheParameters.cacheCtrlAddressOpt).toSeq
149  mmio_port :=
150    TLFilter(TLFilter.mSubtract(mmioFilters)) :=
151    TLBuffer() :=
152    mmio_xbar
153
154  class Imp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
155    val io = IO(new Bundle {
156      val beu_errors = Input(chiselTypeOf(beu.module.io.errors))
157      val reset_vector = new Bundle {
158        val fromTile = Input(UInt(PAddrBits.W))
159        val toCore = Output(UInt(PAddrBits.W))
160      }
161      val hartId = new Bundle() {
162        val fromTile = Input(UInt(64.W))
163        val toCore = Output(UInt(64.W))
164      }
165      val cpu_halt = new Bundle() {
166        val fromCore = Input(Bool())
167        val toTile = Output(Bool())
168      }
169      val cpu_critical_error = new Bundle() {
170        val fromCore = Input(Bool())
171        val toTile = Output(Bool())
172      }
173      val hartIsInReset = new Bundle() {
174        val resetInFrontend = Input(Bool())
175        val toTile = Output(Bool())
176      }
177      val traceCoreInterface = new Bundle{
178        val fromCore = Flipped(new TraceCoreInterface)
179        val toTile   = new TraceCoreInterface
180      }
181      val debugTopDown = new Bundle() {
182        val robTrueCommit = Input(UInt(64.W))
183        val robHeadPaddr = Flipped(Valid(UInt(36.W)))
184        val l2MissMatch = Output(Bool())
185      }
186      val l2Miss = Output(Bool())
187      val l3Miss = new Bundle {
188        val fromTile = Input(Bool())
189        val toCore = Output(Bool())
190      }
191      val chi = if (enableCHI) Some(new PortIO) else None
192      val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None
193      val l2_tlb_req = new TlbRequestIO(nRespDups = 2)
194      val l2_pmp_resp = Flipped(new PMPRespBundle)
195      val l2_hint = ValidIO(new L2ToL1Hint())
196      val perfEvents = Output(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent))
197      val l2_flush_en = Input(Bool())
198      val l2_flush_done = Output(Bool())
199      // val reset_core = IO(Output(Reset()))
200    })
201
202    val resetDelayN = Module(new DelayN(UInt(PAddrBits.W), 5))
203
204    beu.module.io.errors.icache := io.beu_errors.icache
205    beu.module.io.errors.dcache := io.beu_errors.dcache
206    resetDelayN.io.in := io.reset_vector.fromTile
207    io.reset_vector.toCore := resetDelayN.io.out
208    io.hartId.toCore := io.hartId.fromTile
209    io.cpu_halt.toTile := io.cpu_halt.fromCore
210    io.cpu_critical_error.toTile := io.cpu_critical_error.fromCore
211    io.l2_flush_done := true.B //TODO connect CoupleedL2
212    io.l3Miss.toCore := io.l3Miss.fromTile
213    // trace interface
214    val traceToTile = io.traceCoreInterface.toTile
215    val traceFromCore = io.traceCoreInterface.fromCore
216    traceFromCore.fromEncoder := RegNext(traceToTile.fromEncoder)
217    traceToTile.toEncoder.trap := RegEnable(
218      traceFromCore.toEncoder.trap,
219      traceFromCore.toEncoder.groups(0).valid && Itype.isTrap(traceFromCore.toEncoder.groups(0).bits.itype)
220    )
221    traceToTile.toEncoder.priv := RegEnable(
222      traceFromCore.toEncoder.priv,
223      traceFromCore.toEncoder.groups(0).valid
224    )
225    (0 until TraceGroupNum).foreach{ i =>
226      traceToTile.toEncoder.groups(i).valid := RegNext(traceFromCore.toEncoder.groups(i).valid)
227      traceToTile.toEncoder.groups(i).bits.iretire := RegNext(traceFromCore.toEncoder.groups(i).bits.iretire)
228      traceToTile.toEncoder.groups(i).bits.itype := RegNext(traceFromCore.toEncoder.groups(i).bits.itype)
229      traceToTile.toEncoder.groups(i).bits.ilastsize := RegEnable(
230        traceFromCore.toEncoder.groups(i).bits.ilastsize,
231        traceFromCore.toEncoder.groups(i).valid
232      )
233      traceToTile.toEncoder.groups(i).bits.iaddr := RegEnable(
234        traceFromCore.toEncoder.groups(i).bits.iaddr,
235        traceFromCore.toEncoder.groups(i).valid
236      )
237    }
238
239    dontTouch(io.hartId)
240    dontTouch(io.cpu_halt)
241    dontTouch(io.cpu_critical_error)
242    if (!io.chi.isEmpty) { dontTouch(io.chi.get) }
243
244    val hartIsInReset = RegInit(true.B)
245    hartIsInReset := io.hartIsInReset.resetInFrontend || reset.asBool
246    io.hartIsInReset.toTile := hartIsInReset
247
248    if (l2cache.isDefined) {
249      val l2 = l2cache.get.module
250      io.l2_hint := l2.io.l2_hint
251      l2.io.debugTopDown.robHeadPaddr := DontCare
252      l2.io.hartId := io.hartId.fromTile
253      l2.io.debugTopDown.robHeadPaddr := io.debugTopDown.robHeadPaddr
254      l2.io.debugTopDown.robTrueCommit := io.debugTopDown.robTrueCommit
255      io.debugTopDown.l2MissMatch := l2.io.debugTopDown.l2MissMatch
256      io.l2Miss := l2.io.l2Miss
257
258      /* l2 tlb */
259      io.l2_tlb_req.req.bits := DontCare
260      io.l2_tlb_req.req.valid := l2.io.l2_tlb_req.req.valid
261      io.l2_tlb_req.resp.ready := l2.io.l2_tlb_req.resp.ready
262      io.l2_tlb_req.req.bits.vaddr := l2.io.l2_tlb_req.req.bits.vaddr
263      io.l2_tlb_req.req.bits.cmd := l2.io.l2_tlb_req.req.bits.cmd
264      io.l2_tlb_req.req.bits.size := l2.io.l2_tlb_req.req.bits.size
265      io.l2_tlb_req.req.bits.kill := l2.io.l2_tlb_req.req.bits.kill
266      io.l2_tlb_req.req.bits.no_translate := l2.io.l2_tlb_req.req.bits.no_translate
267      io.l2_tlb_req.req_kill := l2.io.l2_tlb_req.req_kill
268      io.perfEvents := l2.io_perf
269
270      val allPerfEvents = l2.getPerfEvents
271      if (printEventCoding) {
272        for (((name, inc), i) <- allPerfEvents.zipWithIndex) {
273          println("L2 Cache perfEvents Set", name, inc, i)
274        }
275      }
276
277      l2.io.l2_tlb_req.resp.valid := io.l2_tlb_req.resp.valid
278      l2.io.l2_tlb_req.req.ready := io.l2_tlb_req.req.ready
279      l2.io.l2_tlb_req.resp.bits.paddr.head := io.l2_tlb_req.resp.bits.paddr.head
280      l2.io.l2_tlb_req.resp.bits.pbmt := io.l2_tlb_req.resp.bits.pbmt.head
281      l2.io.l2_tlb_req.resp.bits.miss := io.l2_tlb_req.resp.bits.miss
282      l2.io.l2_tlb_req.resp.bits.excp.head.gpf := io.l2_tlb_req.resp.bits.excp.head.gpf
283      l2.io.l2_tlb_req.resp.bits.excp.head.pf := io.l2_tlb_req.resp.bits.excp.head.pf
284      l2.io.l2_tlb_req.resp.bits.excp.head.af := io.l2_tlb_req.resp.bits.excp.head.af
285      l2.io.l2_tlb_req.pmp_resp.ld := io.l2_pmp_resp.ld
286      l2.io.l2_tlb_req.pmp_resp.st := io.l2_pmp_resp.st
287      l2.io.l2_tlb_req.pmp_resp.instr := io.l2_pmp_resp.instr
288      l2.io.l2_tlb_req.pmp_resp.mmio := io.l2_pmp_resp.mmio
289      l2.io.l2_tlb_req.pmp_resp.atomic := io.l2_pmp_resp.atomic
290      l2cache.get match {
291        case l2cache: TL2CHICoupledL2 =>
292          val l2 = l2cache.module
293          l2.io_nodeID := io.nodeID.get
294          io.chi.get <> l2.io_chi
295        case l2cache: TL2TLCoupledL2 =>
296      }
297
298      beu.module.io.errors.l2.ecc_error.valid := l2.io.error.valid
299      beu.module.io.errors.l2.ecc_error.bits := l2.io.error.address
300    } else {
301      io.l2_hint := 0.U.asTypeOf(io.l2_hint)
302      io.debugTopDown <> DontCare
303      io.l2Miss := false.B
304
305      io.l2_tlb_req.req.valid := false.B
306      io.l2_tlb_req.req.bits := DontCare
307      io.l2_tlb_req.req_kill := DontCare
308      io.l2_tlb_req.resp.ready := true.B
309      io.perfEvents := DontCare
310
311      beu.module.io.errors.l2 := 0.U.asTypeOf(beu.module.io.errors.l2)
312    }
313  }
314
315  lazy val module = new Imp(this)
316}
317
318class L2Top()(implicit p: Parameters) extends LazyModule
319  with HasXSParameter
320  with HasSoCParameter {
321
322  override def shouldBeInlined: Boolean = false
323
324  val inner = LazyModule(new L2TopInlined())
325
326  class Imp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
327    val io = IO(inner.module.io.cloneType)
328    val reset_core = IO(Output(Reset()))
329    io <> inner.module.io
330
331    if (debugOpts.ResetGen) {
332      ResetGen(ResetGenNode(Seq(
333        CellNode(reset_core),
334        ModuleNode(inner.module)
335      )), reset, sim = false)
336    } else {
337      reset_core := DontCare
338    }
339  }
340
341  lazy val module = new Imp(this)
342}
343