xref: /XiangShan/src/main/scala/xiangshan/DbEntry.scala (revision f7063a43ab34da917ba6c670d21871314340c550) 
1package xiangshan
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util.log2Ceil
6import xiangshan.backend.ctrlblock.{DebugLsInfo, DebugMdpInfo}
7import xiangshan.cache.DCacheBundle
8import xiangshan.backend.fu.FuType
9
10/** Mem */
11class LoadMissEntry(implicit p: Parameters) extends DCacheBundle {
12  val timeCnt = UInt(XLEN.W)
13  val robIdx = UInt(log2Ceil(RobSize).W)
14  val paddr = UInt(PAddrBits.W)
15  val vaddr = UInt(VAddrBits.W)
16  // 1:first hit, 2:first miss, 3:second miss
17  val missState = UInt(3.W)
18}
19
20class LoadAccessEntry(implicit p: Parameters) extends LoadMissEntry{
21  val pred_way_num = UInt(XLEN.W)
22  val dm_way_num = UInt(XLEN.W)
23  val real_way_num = UInt(XLEN.W)
24}
25
26class InstInfoEntry(implicit p: Parameters) extends XSBundle{
27  val globalID = UInt(XLEN.W)
28  val robIdx = UInt(log2Ceil(RobSize).W)
29  val instType = FuType()
30  val exceptType = UInt(ExceptionVec.ExceptionVecSize.W)
31  val ivaddr = UInt(VAddrBits.W)
32  val dvaddr = UInt(VAddrBits.W) // the l/s access address
33  val dpaddr = UInt(VAddrBits.W) // need the physical address when the TLB is valid
34  val tlbLatency = UInt(XLEN.W)  // original requirements is L1toL2TlbLatency
35  val accessLatency = UInt(XLEN.W)  // RS out time --> write back time
36  val executeLatency = UInt(XLEN.W)
37  val issueLatency = UInt(XLEN.W)
38  val lsInfo = new DebugLsInfo
39  val mdpInfo = new DebugMdpInfo
40  val issueTime = UInt(XLEN.W)
41  val writebackTime = UInt(XLEN.W)
42}
43
44class LoadInfoEntry(implicit p: Parameters) extends XSBundle{
45  val pc = UInt(VAddrBits.W)
46  val vaddr = UInt(VAddrBits.W)
47  val paddr = UInt(PAddrBits.W)
48  val cacheMiss = Bool()
49  val tlbQueryLatency = UInt(64.W)
50  val exeLatency = UInt(64.W)
51}