xref: /XiangShan/src/main/scala/xiangshan/DbEntry.scala (revision 0d32f7132f120ac0b32ab552fe0da4934208dd01) 
1package xiangshan
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3._
5import chisel3.util.log2Ceil
6import xiangshan.backend.rob.{DebugLsInfo, DebugMdpInfo}
7import xiangshan.cache.DCacheBundle
8
9/** Mem */
10class LoadMissEntry(implicit p: Parameters) extends DCacheBundle {
11  val timeCnt = UInt(XLEN.W)
12  val robIdx = UInt(log2Ceil(RobSize).W)
13  val paddr = UInt(PAddrBits.W)
14  val vaddr = UInt(VAddrBits.W)
15  // 1:first hit, 2:first miss, 3:second miss
16  val missState = UInt(3.W)
17}
18
19class LoadAccessEntry(implicit p: Parameters) extends LoadMissEntry{
20  val pred_way_num = UInt(XLEN.W)
21  val dm_way_num = UInt(XLEN.W)
22  val real_way_num = UInt(XLEN.W)
23}
24
25class InstInfoEntry(implicit p: Parameters) extends XSBundle{
26  val globalID = UInt(XLEN.W)
27  val robIdx = UInt(log2Ceil(RobSize).W)
28  val instType = FuType()
29  val exceptType = UInt(ExceptionVec.ExceptionVecSize.W)
30  val ivaddr = UInt(VAddrBits.W)
31  val dvaddr = UInt(VAddrBits.W) // the l/s access address
32  val dpaddr = UInt(VAddrBits.W) // need the physical address when the TLB is valid
33  val tlbLatency = UInt(XLEN.W)  // original requirements is L1toL2TlbLatency
34  val accessLatency = UInt(XLEN.W)  // RS out time --> write back time
35  val executeLatency = UInt(XLEN.W)
36  val issueLatency = UInt(XLEN.W)
37  val lsInfo = new DebugLsInfo
38  val mdpInfo = new DebugMdpInfo
39  val issueTime = UInt(XLEN.W)
40  val writebackTime = UInt(XLEN.W)
41}
42
43class LoadInfoEntry(implicit p: Parameters) extends XSBundle{
44  val pc = UInt(VAddrBits.W)
45  val vaddr = UInt(VAddrBits.W)
46  val paddr = UInt(PAddrBits.W)
47  val cacheMiss = Bool()
48  val tlbQueryLatency = UInt(64.W)
49  val exeLatency = UInt(64.W)
50}