1package utils 2 3import chisel3._ 4import chipsalliance.rocketchip.config.Parameters 5import chisel3.util.DecoupledIO 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import freechips.rocketchip.tilelink.{TLBundle, TLClientNode, TLIdentityNode, TLMasterParameters, TLMasterPortParameters} 8 9class DebugIdentityNode()(implicit p: Parameters) extends LazyModule { 10 11 val node = TLIdentityNode() 12 13 val n = TLClientNode(Seq(TLMasterPortParameters.v1( 14 Seq( 15 TLMasterParameters.v1("debug node") 16 ) 17 ))) 18 19 lazy val module = new LazyModuleImp(this) with HasTLDump{ 20 val (out, _) = node.out(0) 21 val (in, _) = node.in(0) 22 23 def debug(t: TLBundle, valid: Boolean = false): Unit ={ 24 def fire[T <: Data](x: DecoupledIO[T]) = if(valid) x.valid else x.fire() 25 val channels = Seq(t.a, t.b, t.c, t.d, t.e) 26 channels.foreach(c => 27 when(fire(c)){ 28 XSDebug(" isFire:%d ",c.fire()) 29 c.bits.dump 30 } 31 ) 32 } 33 debug(in, false) 34 } 35} 36 37object DebugIdentityNode { 38 def apply()(implicit p: Parameters): TLIdentityNode = { 39 val identityNode = LazyModule(new DebugIdentityNode()) 40 identityNode.node 41 } 42} 43